author
int64 658
755k
| date
stringlengths 19
19
| timezone
int64 -46,800
43.2k
| hash
stringlengths 40
40
| message
stringlengths 5
490
| mods
list | language
stringclasses 20
values | license
stringclasses 3
values | repo
stringlengths 5
68
| original_message
stringlengths 12
491
|
|---|---|---|---|---|---|---|---|---|---|
718,770 |
13.10.2018 13:32:25
| 14,400 |
234b57c2b4c525a051d846a77342668d05e99fa4
|
lots of improvement, cleanup, and bug-fixes, including register offsets, unittests, and emulation/analysis improvements.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -240,30 +240,32 @@ PM_hyp = 0b11010\nPM_und = 0b11011\nPM_sys = 0b11111\n+REGS_PER_MODE = 18\n+\n# reg stuff stolen from regs.py to support proc_modes\n# these are in context of reg_table, not reg_data.\n# ie. these are indexes into the lookup table.\n-REG_OFFSET_USR = 17 * (PM_usr&0xf)\n-REG_OFFSET_FIQ = 17 * (PM_fiq&0xf)\n-REG_OFFSET_IRQ = 17 * (PM_irq&0xf)\n-REG_OFFSET_SVC = 17 * (PM_svc&0xf)\n-REG_OFFSET_MON = 17 * (PM_mon&0xf)\n-REG_OFFSET_ABT = 17 * (PM_abt&0xf)\n-REG_OFFSET_HYP = 17 * (PM_hyp&0xf)\n-REG_OFFSET_UND = 17 * (PM_und&0xf)\n-REG_OFFSET_SYS = 17 * (PM_sys&0xf)\n-#REG_OFFSET_CPSR = 17 * 16\n+REG_OFFSET_USR = REGS_PER_MODE * (PM_usr&0xf)\n+REG_OFFSET_FIQ = REGS_PER_MODE * (PM_fiq&0xf)\n+REG_OFFSET_IRQ = REGS_PER_MODE * (PM_irq&0xf)\n+REG_OFFSET_SVC = REGS_PER_MODE * (PM_svc&0xf)\n+REG_OFFSET_MON = REGS_PER_MODE * (PM_mon&0xf)\n+REG_OFFSET_ABT = REGS_PER_MODE * (PM_abt&0xf)\n+REG_OFFSET_HYP = REGS_PER_MODE * (PM_hyp&0xf)\n+REG_OFFSET_UND = REGS_PER_MODE * (PM_und&0xf)\n+REG_OFFSET_SYS = REGS_PER_MODE * (PM_sys&0xf)\n+#REG_OFFSET_CPSR = REGS_PER_MODE * 16\nREG_OFFSET_CPSR = 16 # CPSR is available in every mode, and PM_usr and PM_sys don't have an SPSR.\n-REG_SPSR_usr = REG_OFFSET_USR + 17\n-REG_SPSR_fiq = REG_OFFSET_FIQ + 17\n-REG_SPSR_irq = REG_OFFSET_IRQ + 17\n-REG_SPSR_svc = REG_OFFSET_SVC + 17\n-REG_SPSR_mon = REG_OFFSET_MON + 17\n-REG_SPSR_abt = REG_OFFSET_ABT + 17\n-REG_SPSR_hyp = REG_OFFSET_HYP + 17\n-REG_SPSR_und = REG_OFFSET_UND + 17\n-REG_SPSR_sys = REG_OFFSET_SYS + 17\n+REG_SPSR_usr = REG_OFFSET_USR + REGS_PER_MODE\n+REG_SPSR_fiq = REG_OFFSET_FIQ + REGS_PER_MODE\n+REG_SPSR_irq = REG_OFFSET_IRQ + REGS_PER_MODE\n+REG_SPSR_svc = REG_OFFSET_SVC + REGS_PER_MODE\n+REG_SPSR_mon = REG_OFFSET_MON + REGS_PER_MODE\n+REG_SPSR_abt = REG_OFFSET_ABT + REGS_PER_MODE\n+REG_SPSR_hyp = REG_OFFSET_HYP + REGS_PER_MODE\n+REG_SPSR_und = REG_OFFSET_UND + REGS_PER_MODE\n+REG_SPSR_sys = REG_OFFSET_SYS + REGS_PER_MODE\nREG_PC = 0xf\nREG_LR = 0xe\n@@ -737,7 +739,7 @@ instrnames = [\n'HINT',\n]\n-ins_index = 85\n+ins_index = 0\nfor instr in instrnames:\nglobals()['INS_' + instr] = ins_index\nins_index += 1\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -2077,7 +2077,7 @@ def _do_fp_dp(va, val1, val2):\nelse:\nopers = (\nArmRegOper(rctx.getRegisterIndex(rbase%d)),\n- ArmImmFPOper(0.0),\n+ ArmFloatOper(0.0),\n)\n# VCVT p874\n@@ -3949,8 +3949,11 @@ class ArmRegOper(ArmOperand):\ndef involvesPC(self):\nreturn self.reg == 15\n- def isDeref(self):\n- return False\n+ def isReg(self):\n+ return True\n+\n+ def getWidth(self):\n+ return rctx.getRegisterWidth(self.reg) / 8\ndef getOperValue(self, op, emu=None):\nif self.reg == REG_PC:\n@@ -3998,7 +4001,7 @@ class ArmRegScalarOper(ArmRegOper):\nreturn False\ndef isDeref(self):\n- return False\n+ return True\ndef getOperValue(self, op, emu=None):\nif emu == None:\n@@ -4154,6 +4157,9 @@ class ArmImmOper(ArmOperand):\ndef isDeref(self):\nreturn False\n+ def isImmed(self):\n+ return True\n+\ndef isDiscrete(self):\nreturn True\n@@ -4170,26 +4176,50 @@ class ArmImmOper(ArmOperand):\nreturn '#0x%.2x' % (val)\nclass ArmFloatOper(ArmImmOper):\n+ '''\n+ float operand (of a particular byte-width)\n+ internal storage as N-bit bitfield (like the architecture would)\n+ repr/render provides the appropriate floating point value\n+ '''\ndef __init__(self, val, size=4, endian=envi.ENDIAN_LSB):\n- self.val = val\nself.size = size\nself.endian = endian\n+ self.intfmt = e_bits.fmt_chars[self.endian][self.size]\n+ self.floatfmt = e_bits.fmt_floats[self.endian][self.size]\n+\n+ if type(val) == float:\n+ self.setByFloat(val)\n+ else:\n+ self.setByBitField(val)\n+\n+ def setByFloat(self, val):\n+ val = struct.pack(self.floatfmt, val)\n+ self.val, = struct.unpack(self.intfmt, val)\n+\n+ def setByBitField(self, val):\n+ self.val = val\ndef getOperValue(self, op, emu=None):\n- infmt = e_bits.fmt_chars[self.endian][self.size]\n- outfmt = e_bits.fmt_floats[self.endian][self.size]\n- bytez = struct.pack(infmt, self.val)\n- retval = struct.unpack(outfmt, bytez)[0]\n+ return self.val\n+\n+ def getFloatValue(self, op, emu=None):\n+ '''\n+ helper function to deal with the float values (getOperValue returns a bitfield)\n+ '''\n+ bytez = struct.pack(self.intfmt, self.val)\n+ retval = struct.unpack(self.floatfmt, bytez)[0]\nreturn retval\ndef render(self, mcanv, op, idx):\n- val = self.getOperValue(op)\n+ val = self.getFloatValue(op)\nmcanv.addNameText('#%f' % (val))\ndef repr(self, op):\n- val = self.getOperValue(op)\n+ val = self.getFloatValue(op)\n+\nreturn '#%f' % (val)\n+\"\"\"\nclass ArmImmFPOper(ArmImmOper):\n'''\nWhat's the difference between this and ArmFloatOper??\n@@ -4208,7 +4238,7 @@ class ArmImmFPOper(ArmImmOper):\ndef repr(self, op):\nval = self.getOperValue(op)\nreturn '#%.2f' % (val)\n-\n+\"\"\"\nclass ArmScaledOffsetOper(ArmOperand):\n''' scaled offset operand. see \"addressing mode 2 - load and store word or unsigned byte - scaled register *\" '''\n@@ -4637,6 +4667,9 @@ class ArmPcOffsetOper(ArmOperand):\ndef involvesPC(self):\nreturn True\n+ def isImmed(self):\n+ return True\n+\ndef isDeref(self):\nreturn False\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -57,7 +57,7 @@ class CoProcEmulator: # useful for prototyping, but should be subclassed\ndef _getRegIdx(idx, mode):\nif idx >= MAX_REGS:\nreturn idx\n- ridx = idx + (mode*17) # account for different banks of registers\n+ ridx = idx + (mode*REGS_PER_MODE) # account for different banks of registers\nridx = reg_table[ridx] # magic pointers allowing overlapping banks of registers\nreturn ridx\n@@ -718,7 +718,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# dest is extension reg\nsrc = self.getOperValue(op, 1)\nsrc2 = self.getOperValue(op, 2)\n- src |= (src2 << 32)\n+ src |= (int(src2) << 32)\nself.setOperValue(op, 0, src)\nelif len(op.opers) == 4:\n@@ -736,11 +736,39 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nsrc = self.getOperValue(op, 1)\nself.setOperValue(op, 0, src)\n+ def i_vcmp(self, op):\n+ try:\n+ src1 = self.getOperValue(op, 0)\n+ src2 = self.getOperValue(op, 1)\n+ val = src2 - src1\n+ #print \"vcmpe %r %r %r\" % (src1, src2, val)\n+ fpsrc = self.getRegister(REG_FPSCR)\n+\n+ # taken from VFCompare() from arch ref manual p80\n+ if src1 == src2:\n+ n, z, c, v = 0, 1, 1, 0\n+ elif src1 < src2:\n+ n, z, c, v = 1, 0, 0, 0\n+ else:\n+ n, z, c, v = 0, 0, 1, 0\n+\n+ self.setFpFlag(PSR_N_bit, n)\n+ self.setFpFlag(PSR_Z_bit, z)\n+ self.setFpFlag(PSR_C_bit, c)\n+ self.setFpFlag(PSR_V_bit, v)\n+ except Exception, e:\n+ print(\"vcmp exception: %r\" % e)\n+\ndef i_vcmpe(self, op):\n+ try:\n+ size = (4,8)[bool(op.iflags & IFS_F64)]\n+\nsrc1 = self.getOperValue(op, 0)\nsrc2 = self.getOperValue(op, 1)\n+\nval = src2 - src1\n- print \"vcmpe %r %r %r\" % (src1, src2, val)\n+\n+ #print \"vcmpe %r %r %r %r\" % (op, src1, src2, val)\nfpsrc = self.getRegister(REG_FPSCR)\n# taken from VFCompare() from arch ref manual p80\n@@ -755,6 +783,53 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setFpFlag(PSR_Z_bit, z)\nself.setFpFlag(PSR_C_bit, c)\nself.setFpFlag(PSR_V_bit, v)\n+ except Exception, e:\n+ print(\"vcmpe exception: %r\" % e)\n+\n+ def i_vcvt(self, op):\n+ print op, op.opers\n+ print(\"complete implementing vcvt\")\n+ width = op.opers[0].getWidth()\n+ regcnt = width / 4\n+\n+\n+ if len(op.opers) == 3:\n+ for reg in range(regcnt):\n+ #frac_bits = 64 - op.opers[2].val\n+\n+ if op.simdflags & IFS_F32_S32:\n+ pass\n+ elif op.simdflags & IFS_F32_U32:\n+ pass\n+ elif op.simdflags & IFS_S32_F32:\n+ pass\n+ elif op.simdflags & IFS_U32_F32:\n+ pass\n+\n+ elif len(op.opers) == 2:\n+ for reg in range(regcnt):\n+ #frac_bits = 64 - op.opers[1].val\n+\n+ if op.simdflags & IFS_F32_S32:\n+ pass\n+ elif op.simdflags & IFS_F32_U32:\n+ pass\n+ elif op.simdflags & IFS_S32_F32:\n+ pass\n+ elif op.simdflags & IFS_U32_F32:\n+ pass\n+ elif op.simdflags & IFS_F64_S32:\n+ pass\n+ elif op.simdflags & IFS_F64_U32:\n+ pass\n+ elif op.simdflags & IFS_S32_F64:\n+ pass\n+ elif op.simdflags & IFS_U32_F64:\n+ pass\n+ else:\n+ raise Exception(\"i_vcvt with strange number of opers: %r\" % op.opers)\n+\n+ i_vcvtr = i_vcvt\ndef i_ldm(self, op):\nif len(op.opers) == 2:\n@@ -934,12 +1009,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nmask = e_bits.b_masks[width]\naddit = self.getOperValue(op, 1) & mask\n- print \"bfi: \", lsb, width, bin(mask), bin(addit)\n+ #print \"bfi: \", lsb, width, bin(mask), bin(addit)\nmask <<= lsb\nval = self.getOperValue(op, 0) & ~mask\nval |= addit\n- print \"bfi: 2 \", bin(mask), bin(val)\n+ #print \"bfi: 2 \", bin(mask), bin(val)\nself.setOperValue(op, 0, val)\n@@ -948,10 +1023,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nwidth = self.getOperValue(op, 2)\nmask = e_bits.b_masks[width] << lsb\nmask ^= 0xffffffff\n- print \"bfc: \", lsb, width, bin(mask)\n+ #print \"0x%x: %r %r: \" % (op.va, self.readMemory(op.va, 4).encode('hex'), op), lsb, width, bin(mask)\n- val = self.getOperValue(op, 0) & mask\n- print \"bfc: 2 \", bin(mask), bin(val)\n+ val = self.getOperValue(op, 0)\n+ #print \"bfc: 1.5: \", bin(val)\n+ val &= mask\n+ #print \"bfc: 2 \", bin(mask), bin(val)\nself.setOperValue(op, 0, val)\n@@ -1428,11 +1505,11 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\n- imm5 = self.getOperValue(op, 2)\n+ imm5 = self.getOperValue(op, 2) & 0b11111\nelse:\nsrc = self.getOperValue(op, 0)\n- imm5 = self.getOperValue(op, 1)\n+ imm5 = self.getOperValue(op, 1) & 0b11111\nval = ((src >> imm5) | (src << 32-imm5)) & 0xffffffff\ncarry = (val >> 31) & 1\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/regs.py",
"new_path": "envi/archs/arm/regs.py",
"diff": "@@ -9,7 +9,7 @@ Strategy:\n* Emulator does translation from register/mode to actual storage container\nusing reg_table and some math (see _getRegIdx)\n'''\n-arm_regs = (\n+arm_regs = [\n('r0', 32),\n('r1', 32),\n('r2', 32),\n@@ -29,8 +29,12 @@ arm_regs = (\n('cpsr', 32),\n('nil', 32), # place holder\n# FIXME: need to deal with ELR_hyp\n-)\n+]\nMAX_REGS = 17\n+#arm_regs.extend([('q%d' % x, 128) for x in range(VFP_QWORD_REG_COUNT)])\n+\n+# force them into a tuple for faster run-time access\n+arm_regs = tuple(arm_regs)\narm_metas = [\n(\"r13\", REG_SP, 0, 32),\n@@ -44,7 +48,7 @@ REG_APSR_MASK = 0xffff0000\nmodes = proc_modes.keys()\nmodes.sort()\n-reg_table = [ x for x in range(16 * 18) ]\n+reg_table = [ x for x in range(17 * REGS_PER_MODE) ]\nreg_data = [ (reg, sz) for reg,sz in arm_regs ]\nfor modenum in modes[1:]: # skip first since we're already done\n@@ -61,9 +65,11 @@ for modenum in modes[1:]: # skip first since we're already done\nreg_table[ridx+offset] = idx\n# PC\n- reg_table[PSR_offset-2] = 15\n+ reg_table[PSR_offset-3] = 15\n# CPSR\n- reg_table[PSR_offset-1] = 16\n+ reg_table[PSR_offset-2] = 16 # SPSR....??\n+ # NIL\n+ reg_table[PSR_offset-1] = 17\n# PSR\nreg_table[PSR_offset] = len(reg_data)\nreg_data.append((\"SPSR_\"+msname, 32))\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -475,6 +475,36 @@ class MemoryObject(IMemory):\noff, b = self.getByteDef(va)\nreturn self.imem_archs[ (arch & envi.ARCH_MASK) >> 16 ].archParseOpcode(b, off, va)\n+ def readMemString(self, va, maxlen=0xfffffff):\n+ '''\n+ Returns a C-style string from memory. Stops at Memory Map boundaries, or the first NULL (\\x00) byte.\n+ '''\n+\n+ for mva, mmaxva, mmap, mbytes in self._map_defs:\n+ if va >= mva and va < mmaxva:\n+ mva, msize, mperms, mfname = mmap\n+ if not mperms & MM_READ:\n+ raise envi.SegmentationViolation(va)\n+ offset = va - mva\n+\n+ # now find the end of the string based on either \\x00, maxlen, or end of map\n+ end = mbytes.find('\\x00', offset)\n+\n+ left = end - offset\n+ if end == -1:\n+ # couldn't find the NULL byte\n+ mend = offset + maxlen\n+ cstr = mbytes[offset:mend]\n+ else:\n+ # couldn't find the NULL byte go to the end of the map or maxlen\n+ mend = offset + (maxlen, left)[left < maxlen]\n+ cstr = mbytes[offset:mend]\n+ return cstr\n+\n+ raise envi.SegmentationViolation(va)\n+\n+\n+\nclass MemoryFile:\n'''\nA file like object to wrap around a memory object.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/elfplt.py",
"new_path": "vivisect/analysis/arm/elfplt.py",
"diff": "@@ -6,6 +6,9 @@ Make that apparent.\nimport envi\nimport vivisect\n+import logging\n+logger = logging.getLogger(__name__)\n+\ndef analyze(vw):\n\"\"\"\nDo simple linear disassembly of the .plt section if present.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -31,7 +31,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\ntry:\ntmode = emu.getFlag(PSR_T_bit)\nself.last_tmode = tmode\n- #if self.verbose: print \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op)\n+ #if self.verbose: print( \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op))\n#if op == self.badop:\nif op in self.badops:\nraise Exception(\"Hit known BADOP at 0x%.8x %s (fva: 0x%x)\" % (starteip, repr(op), self.fva))\n@@ -66,7 +66,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nself.switchcases += 1\nemu.vw.setVaSetRow('SwitchCases', (op.va, op.va, count) )\n- if op.opcode == INS_MOV:\n+ elif op.opcode == INS_MOV:\nif len(op.opers) >= 2:\noper0 = op.opers[0]\noper1 = op.opers[1]\n@@ -75,30 +75,47 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nif isinstance(oper1, e_arm.ArmRegOper) and oper1.reg == REG_PC:\nself.last_lr_pc = starteip\n- if op.opcode == INS_BX:\n+ elif op.opcode == INS_BX:\nif starteip - self.last_lr_pc <= 4:\n# this is a call. the compiler updated lr\n- if self.verbose: print \"CALL by mov lr, pc; bx <foo> at 0x%x\" % starteip\n+ if self.verbose: print(\"CALL by mov lr, pc; bx <foo> at 0x%x\" % starteip)\n### DO SOMETHING?? identify new function like emucode.\n+ elif op.opcode == INS_ADD and op.opers[0].reg == REG_PC:\n+ # simple branch code\n+ if emu.vw.getVaSetRow('SwitchCases', op.va) == None:\n+ base, tbl = analyzeADDPC(emu, op, starteip, self)\n+ count = len(tbl)\n+ self.switchcases += 1\n+ emu.vw.setVaSetRow('SwitchCases', (op.va, op.va, count) )\n+\n+ elif op.opcode == INS_SUB and isinstance(op.opers[0], e_arm.ArmRegOper) and op.opers[0].reg == REG_PC:\n+ # simple branch code\n+ if emu.vw.getVaSetRow('SwitchCases', op.va) == None:\n+ base, tbl = analyzeSUBPC(emu, op, starteip, self)\n+ count = len(tbl)\n+ self.switchcases += 1\n+ emu.vw.setVaSetRow('SwitchCases', (op.va, op.va, count) )\n+\n+\nif op.iflags & envi.IF_BRANCH:\ntry:\ntgt = op.getOperValue(0, emu)\n- #if self.verbose: print \"BRANCH: \", hex(tgt), hex(op.va), hex(op.va)\n+ #if self.verbose: print(\"BRANCH: \", hex(tgt), hex(op.va), hex(op.va))\nif tgt == op.va:\n- if self.verbose: print \"+++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\"\n+ if self.verbose: print(\"+++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\")\nif op.va not in self.infloops:\nself.infloops.append(op.va)\nexcept Exception, e:\n# FIXME: make raise Exception?\n- print \"0x%x: ERROR: %s\" % (op.va, e)\n+ print(\"0x%x: ERROR: %s\" % (op.va, e))\nexcept Exception, e:\n# FIXME: make raise Exception?\n- print \"0x%x: (%r) ERROR: %s\" % (op.va, op, e)\n+ print(\"0x%x: (%r) ERROR: %s\" % (op.va, op, e))\nsys.excepthook(*sys.exc_info())\n@@ -161,7 +178,7 @@ def analyzeFunction(vw, fva):\nif (lti & envi.ARCH_MASK) != envi.ARCH_ARMV7:\nemu.setFlag(PSR_T_bit, 1)\nelse:\n- print \"NO LOCATION at FVA: 0x%x\" % fva\n+ print(\"NO LOCATION at FVA: 0x%x\" % fva)\nemu.runFunction(fva, maxhit=1)\n@@ -204,7 +221,7 @@ def analyzeTB(emu, op, starteip, amon):\n######################### FIXME: ADD THIS TO getBranches(emu)\n### DEBUGGING\n#raw_input(\"\\n\\n\\nPRESS ENTER TO START TB: 0x%x\" % op.va)\n- if emu.vw.verbose: print \"\\n\\nTB at 0x%x\" % starteip\n+ if emu.vw.verbose: print(\"\\n\\nTB at 0x%x\" % starteip)\ntsize = op.opers[0].tsize\ntbl = []\nbasereg = op.opers[0].base_reg\n@@ -217,24 +234,24 @@ def analyzeTB(emu, op, starteip, amon):\nval0 = emu.readMemValue(base, tsize)\nif val0 > 0x100 + base:\n- print \"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\"\n+ print(\"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\")\nva = base\nwhile va < base + val0:\nnextoff = emu.readMemValue(va, tsize) * 2\n- if emu.vw.verbose: print \"0x%x: -> 0x%x\" % (va, nextoff + base)\n+ if emu.vw.verbose: print(\"0x%x: -> 0x%x\" % (va, nextoff + base))\nif nextoff == 0:\n- if emu.vw.verbose: print \"Terminating TB at 0-offset\"\n+ if emu.vw.verbose: print(\"Terminating TB at 0-offset\")\nbreak\nif nextoff > 0x500:\n- if emu.vw.verbose: print \"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nextoff\n+ if emu.vw.verbose: print(\"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nextoff)\nbreak\nloc = emu.vw.getLocation(va)\nif loc != None:\n- if emu.vw.verbose: print \"Terminating TB at Location/Reference\"\n- if emu.vw.verbose: print \"%x, %d, %x, %r\" % loc\n+ if emu.vw.verbose: print(\"Terminating TB at Location/Reference\")\n+ if emu.vw.verbose: print(\"%x, %d, %x, %r\" % loc)\nbreak\ntbl.append((va, nextoff))\n@@ -242,7 +259,7 @@ def analyzeTB(emu, op, starteip, amon):\n#sys.stderr.write('.')\nif emu.vw.verbose:\n- print \"%s: \\n\\t\"%op.mnem + '\\n\\t'.join(['0x%x (0x%x)' % (x, base + x) for v,x in tbl])\n+ print(\"%s: \\n\\t\"%op.mnem + '\\n\\t'.join(['0x%x (0x%x)' % (x, base + x) for v,x in tbl]))\n###\n# for workspace emulation analysis, let's check the index register for sanity.\n@@ -255,7 +272,7 @@ def analyzeTB(emu, op, starteip, amon):\njmptblval = emu.getOperAddr(op, 0)\njmptbltgt = (emu.getOperValue(op, 0) * 2) + base\nif emu.vw.verbose:\n- print \"0x%x: %r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\" % (op.va, op, jmptblbase, jmptblval, jmptbltgt)\n+ print(\"0x%x: %r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\" % (op.va, op, jmptblbase, jmptblval, jmptbltgt))\n#raw_input(\"PRESS ENTER TO CONTINUE\")\n# make numbers and xrefs and names\n@@ -281,3 +298,55 @@ def analyzeTB(emu, op, starteip, amon):\nreturn base, tbl\n+def analyzeADDPC(emu, op, starteip, emumon):\n+ count = None\n+\n+ reg = op.opers[-1].reg\n+ cb = emu.vw.getCodeBlock(op.va)\n+ if cb == None:\n+ return None, None\n+\n+ cbva, cbsz, cbfva = cb\n+ off = 0\n+ while off < cbsz:\n+ top = emu.vw.parseOpcode(cbva+off)\n+ if top.opcode == INS_CMP:\n+ for opidx in range(len(top.opers)):\n+ oper = top.opers[opidx]\n+ if isinstance(oper, e_arm.ArmRegOper):\n+ if oper.reg != reg:\n+ continue\n+\n+ #print(\"cmp op: \", top)\n+ cntoidx = (1,0)[opidx]\n+ cntoper = top.opers[cntoidx]\n+ #print(\"cntoper: %d, %r %r\" % (cntoidx, cntoper, vars(cntoper)))\n+ count = cntoper.getOperValue(top, emu)\n+ #print(\"count = \", count)\n+\n+ off += len(top)\n+\n+ if not count or count == None or count > 10000:\n+ return None, None\n+\n+ #print(\"Making ADDPC SwitchCase (count=%d):\" % count)\n+ tbl = []\n+ for x in range(count):\n+ base = op.opers[-2].getOperValue(op, emu)\n+ base_reg = op.opers[-1].reg\n+ emu.setRegister(base_reg, x)\n+ idx = op.opers[-1].getOperValue(op, emu)\n+ nexttgt = base + idx\n+ #print(\"x=%x, base=%x, idx=%x (%x) %r %r %d\" % (x,base,idx, nexttgt, op, op.opers, emu.getRegister(op.opers[-1].reg)))\n+ tbl.append((base+idx, x))\n+ emu.vw.makeCode(nexttgt)\n+ emu.vw.addXref(starteip, nexttgt, REF_CODE)\n+\n+ curname = emu.vw.getName(nexttgt)\n+ if curname == None:\n+ emu.vw.makeName(nexttgt, \"case_%x_%x_%x\" % (x, starteip, nexttgt))\n+ else:\n+ emu.vw.vprint(\"case_%x_%x_%x conflicts with existing name: %r\" % (x, starteip, nexttgt, curname))\n+\n+\n+ return base, tbl\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -56,7 +56,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\n# parse out an opcode\ntmode = self.getFlag(PSR_T_bit)\n- #print \"tmode: %x\" % tmode\n+ #print(\"tmode: %x\" % tmode)\nop = self.parseOpcode(starteip | tmode)\nif self.emumon:\nself.emumon.prehook(self, op, starteip)\n@@ -77,13 +77,13 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif tmode != None:\n# we're forcing thumb or arm mode... update the flag\nself.setFlag(PSR_T_bit, tmode)\n- if verbose: print \"funcva thumb==%d (forced): 0x%x\" % (tmode, funcva)\n+ if verbose: print(\"funcva thumb==%d (forced): 0x%x\" % (tmode, funcva))\nelif funcva & 3:\n# if the va isn't 4-byte aligned, it's gotta be thumb\nself.setFlag(PSR_T_bit, 1)\nfuncva &= -2\n- if verbose: print \"funcva is THUMB(addr): 0x%x\" % funcva\n+ if verbose: print(\"funcva is THUMB(addr): 0x%x\" % funcva)\nelse:\nloc = self.vw.getLocation(funcva)\n@@ -92,8 +92,8 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nlva, lsz, lt, lti = loc\nif (lti & envi.ARCH_MASK) == envi.ARCH_THUMB:\nself.setFlag(PSR_T_bit, 1)\n- if verbose: print \"funcva is THUMB(loc): 0x%x\" % funcva\n- elif verbose: print \"funcva is ARM(loc): 0x%x\" % funcva\n+ if verbose: print(\"funcva is THUMB(loc): 0x%x\" % funcva)\n+ elif verbose: print(\"funcva is ARM(loc): 0x%x\" % funcva)\nelse:\n# otherwise, let's use some heuristics to guess.\n@@ -131,9 +131,9 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nelif armthumb < 0:\nself.setFlag(PSR_T_bit, 1)\n- if verbose: print \"ArmWorkspaceEmulator: Heuristically Determined funcva is THUMB: 0x%x\" % funcva\n+ if verbose: print(\"ArmWorkspaceEmulator: Heuristically Determined funcva is THUMB: 0x%x\" % funcva)\nelse:\n- if verbose: print \"ArmWorkspaceEmulator: Heuristically Determined funcva is ARM: 0x%x\" % funcva\n+ if verbose: print(\"ArmWorkspaceEmulator: Heuristically Determined funcva is ARM: 0x%x\" % funcva)\nself.funcva = funcva\n@@ -196,7 +196,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\ntry:\ntmode = self.getFlag(PSR_T_bit)\n- #print \"tmode: %x\" % tmode\n+ #print(\"tmode: %x\" % tmode)\n# FIXME unify with stepi code...\nop = self.parseOpcode(starteip | tmode)\n@@ -252,17 +252,17 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nexcept envi.UnsupportedInstruction, e:\nif self.strictops:\n- if verbose: print 'runFunction breaking after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\n+ if verbose: print('runFunction breaking after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\nraise e\nelse:\n- if verbose: print 'runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\n+ if verbose: print('runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\nself.setProgramCounter(e.op.va+ e.op.size)\nexcept Exception, e:\n#traceback.print_exc()\nif self.emumon != None:\nself.emumon.logAnomaly(self, starteip, str(e))\n- if verbose: print 'runFunction breaking after exception (fva: 0x%x): %s' % (funcva, e)\n+ if verbose: print('runFunction breaking after exception (fva: 0x%x): %s' % (funcva, e))\nif verbose: sys.excepthook(*sys.exc_info())\nbreak # If we exc during execution, this branch is dead.\n#except:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
lots of improvement, cleanup, and bug-fixes, including register offsets, unittests, and emulation/analysis improvements.
|
718,770 |
27.11.2018 14:56:38
| 18,000 |
efcfe1efa5fad2f9303530d43513342cef7c2f2a
|
update to handle any NULL terminator out of any codepage.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -848,11 +848,6 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nreturn -1\nc1 = bytes[offset+count+1]\n- # If it's not null,char,null,char then it's\n- # not simple unicode...\n- if c1 != charset:\n- return -1\n-\n# If we find our null terminator after more\n# than 4 chars, we're probably a real string\nif ord(c0) == 0:\n@@ -865,6 +860,11 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif c0 not in string.printable:\nreturn -1\n+ # If it's not null,char,null,char then it's\n+ # not simple unicode...\n+ if c1 != charset:\n+ return -1\n+\ncount += 2\nreturn -1\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
update to handle any NULL terminator out of any codepage.
|
718,770 |
28.11.2018 11:52:04
| 18,000 |
c7d583757128cfd3f6b08568d18d7c4518cfa831
|
to super() or to parent()? that is the question. but the issue predates this branch.
|
[
{
"change_type": "MODIFY",
"old_path": "vqt/hotkeys.py",
"new_path": "vqt/hotkeys.py",
"diff": "@@ -163,11 +163,12 @@ class HotKeyMixin(object):\ndef keyPressEvent(self, event):\nif not self.eatKeyPressEvent(event):\n+ # is this a bug? do we call the super? or the parent?\nreturn super(HotKeyMixin, self).keyPressEvent(event)\n- parent = self.parent()\n- if parent != None:\n- return parent.keyPressEvent(event)\n+ #parent = self.parent()\n+ #if parent != None:\n+ # return parent.keyPressEvent(event)\nimport vqt.tree\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
to super() or to parent()? that is the question. but the issue predates this branch.
|
718,770 |
30.11.2018 12:11:16
| 18,000 |
ce79b593c35872617462e957515d4042d6a59519
|
get rid of all codeblocks associated with a function...
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -246,10 +246,19 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nmcb(va, name, value)\ndef _handleDELFUNCTION(self, einfo):\n- self.funcmeta.pop(einfo)\n- self.func_args.pop(einfo, None)\n- self.codeblocks_by_funcva.pop(einfo)\n- node = self._call_graph.getNode(einfo)\n+ # clear funcmeta, func_args, codeblocks_by_funcva, update codeblocks, blockgraph, locations, etc...\n+ fva = einfo\n+ blocks = self.getFunctionBlocks(fva)\n+\n+ # not every codeblock identifying as this function is stored in funcmeta\n+ for cb in self.getCodeBlocks():\n+ if cb[CB_FUNCVA] == fva:\n+ self._handleDELCODEBLOCK(cb)\n+\n+ self.funcmeta.pop(fva)\n+ self.func_args.pop(fva, None)\n+ self.codeblocks_by_funcva.pop(fva)\n+ node = self._call_graph.getNode(fva)\nself._call_graph.delNode(node)\ndef _handleSETFUNCMETA(self, einfo):\n@@ -269,6 +278,7 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nself.codeblocks.append(einfo)\ndef _handleDELCODEBLOCK(self, cb):\n+ print \"DELCODEBLOCK: \", cb\nva,size,funcva = cb\nself.codeblocks.remove(cb)\nself.codeblocks_by_funcva.get(cb[CB_FUNCVA]).remove(cb)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
get rid of all codeblocks associated with a function...
|
718,770 |
30.11.2018 13:17:27
| 18,000 |
000251aae232b71b190b2ab80d926993e2710f22
|
included "vw.cfctx._funcs" in the deletion process
added GUI verification before a function is actually deleted.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -278,6 +278,14 @@ class CodeFlowContext(object):\n# Finally, notify the callback of a new function\nself._cb_function(va, {'CallsFrom':calls_from})\n+ def flushFunction(self, fva):\n+ '''\n+ Codeflow context maintains a list of identified functions, to avoid\n+ analyzing the same function twice. If a function is misidentified\n+ flushFunction() is used to clear that function from the tracked _funcs\n+ '''\n+ self._funcs[fva] = None\n+\ndef addDynamicBranchHandler(self, cb):\n'''\nAdd a callback handler for dynamic branches the code-flow resolver\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -263,6 +263,13 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nself.codeblocks_by_funcva.pop(fva)\nnode = self._call_graph.getNode(fva)\nself._call_graph.delNode(node)\n+ self.cfctx.flushFunction(fva)\n+\n+ # FIXME: do we want to now seek the function we *should* be in?\n+ # if xrefs_to, look for non-PROC code xrefs and take their function\n+ # if the previous instruction falls through, take its function\n+ # run codeblock analysis on that function to reassociate the blocks\n+ # with that function\ndef _handleSETFUNCMETA(self, einfo):\nfuncva, name, value = einfo\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/ctxmenu.py",
"new_path": "vivisect/qt/ctxmenu.py",
"diff": "@@ -152,7 +152,8 @@ def buildContextMenu(vw, va=None, expr=None, menu=None, parent=None, nav=None):\nfuncmenu.addAction('call graph', ACT(vw.getVivGui().showFuncCallGraph, fva))\nfuncmenu.addAction('re-analyze codeblocks', ACT(vagc.analyzeFunction, vw, fva))\nif fva == va:\n- funcmenu.addAction('delete function', ACT(vw.delFunction, va))\n+ #funcmenu.addAction('delete function', ACT(vw.delFunction, va))\n+ funcmenu.addAction('delete function', ACT(vw.getVivGui().delFunction, va))\nloc = vw.getLocation(va)\nif loc == None:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -202,6 +202,14 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nview = viv_q_views.VQVivVaSetView(self.vw, self, name)\nself.vqDockWidget(view)\n+ def delFunction(self, fva, parent=None):\n+ if parent == None:\n+ parent = self\n+\n+ yn, ok = QInputDialog.getItem(self, 'Delete Function', 'Confirm:', ('No', 'Yes'), 0, False)\n+ if ok and yn == 'Yes':\n+ self.vw.delFunction(fva)\n+\ndef vqInitDockWidgetClasses(self):\nexprloc = e_expr.MemoryExpressionLocals(self.vw, symobj=self.vw)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
included "vw.cfctx._funcs" in the deletion process
added GUI verification before a function is actually deleted.
|
718,765 |
04.12.2018 09:57:03
| 18,000 |
4a276cb36e1e8cc7f215ef57587187649a9e968d
|
Update README for running vivisect under recent python 2.7 versions
|
[
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -45,6 +45,47 @@ that aren't ) are directly accessible for use writing your own custom\nresearch tools... The interface should be nearly the same when dealing with\na real process ( via vdb/vtrace ) and dealing with an emulator / viv workspace.\n+## UI Dependencies\n+\n+In order to get the vivisect UI running, you'll first need to install the Qt4 and Qt4-Webkit libraries. On Ubuntu, you can do this via:\n+\n+> sudo apt-get install libqt4-dev libqtwebkit-dev\n+\n+If you're on an older version of python, you may be able to pip install PyQt4 and SIP like so:\n+\n+> pip install PyQt4 SIP\n+\n+However, on recent (tested on 2.7.15 December 2018) versions of pip, that pip install fails. To get around this, you'll need to download the sources for both PyQt4 and SIP from Riverbank.\n+* SIP can be found [here](https://sourceforge.net/projects/pyqt/files/sip/sip-4.19.13/sip-4.19.13.tar.gz)\n+* PyQt4 can be found [here](http://sourceforge.net/projects/pyqt/files/PyQt4/PyQt-4.12.3/PyQt4_gpl_x11-4.12.3.tar.gz)\n+\n+Untar them to their respective directories and cd in the directory for SIP:\n+\n+```\n+tar -xf sip-4.19.13.tar.gz\n+tar -xf PyQt4_gpl_x11-4.12.3.tar.gz\n+cd sip-4.19.13/\n+```\n+\n+Then build the SIP module. Due to the recent version of SIP we're using, we have to build it as a private module like so:\n+\n+```\n+python configure.py --sip-module PyQt4.sip\n+make\n+make install\n+```\n+\n+Now cd back to the PyQt4 module and build that one:\n+\n+```\n+cd ../PyQt4_gpl_x11-4.12.3/\n+python configure-ng.py\n+make -j4\n+make install\n+```\n+\n+And then you should be able to open up your vivisect workspace with the vivbin script.\n+\n## Build Status\n[](https://travis-ci.org/vivisect/vivisect)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Update README for running vivisect under recent python 2.7 versions
|
718,765 |
12.12.2018 11:31:41
| 18,000 |
6e3cc7020be82cef01c90f0c1c355785e1fdcddd
|
Add section about building/installing PyQt5
|
[
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -90,6 +90,22 @@ make install\nAnd then you should be able to open up your vivisect workspace with the vivbin script.\n+### PyQt5\n+\n+PyQt5 is unsupported on Python 2.x. So similar steps must be followed to install PyQt5 to get the UI working that way as well.\n+\n+Install qt5:\n+```\n+sudo apt-get install qt5-default libqtwebkit-dev\n+```\n+\n+Install the dependencies that PyQt5 needs:\n+```\n+pip install enum34\n+```\n+\n+The rest of the build/install steps are the same, save for changing out the version numbers from PyQt4 to PyQt5.\n+\n## Build Status\n[](https://travis-ci.org/vivisect/vivisect)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Add section about building/installing PyQt5
|
718,765 |
14.12.2018 12:00:27
| 18,000 |
b1a94d859fb4a8d1740c9848ce7161760ab7253b
|
Got QT5 showing a UI
|
[
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -96,7 +96,7 @@ PyQt5 is unsupported on Python 2.x. So similar steps must be followed to install\nInstall qt5:\n```\n-sudo apt-get install qt5-default libqtwebkit-dev\n+sudo apt-get install qt5-default libqt5webkit5-dev\n```\nInstall the dependencies that PyQt5 needs:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Got QT5 showing a UI
|
718,765 |
14.12.2018 12:02:04
| 18,000 |
e5357739954f2bc00d08d525fda7106777a9d529
|
Add blurd on a perm issue
|
[
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -88,6 +88,8 @@ make -j4\nmake install\n```\n+If you run into an `Error 2` status code on the `make install` line, replace that line with `sudo make install`, and things should work out fine.\n+\nAnd then you should be able to open up your vivisect workspace with the vivbin script.\n### PyQt5\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Add blurd on a perm issue
|
718,765 |
14.12.2018 12:15:00
| 18,000 |
30ae75a24b7a46c29b4a00e1089d653c5a07e94d
|
Change around wording as per atlas
|
[
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -47,7 +47,9 @@ a real process ( via vdb/vtrace ) and dealing with an emulator / viv workspace.\n## UI Dependencies\n-In order to get the vivisect UI running, you'll first need to install the Qt4 and Qt4-Webkit libraries. On Ubuntu, you can do this via:\n+The vivisect UI can be run under either PyQt4 and PyQt5\n+\n+For running via PyQt4, first you'll need to install Qt4 and Qt4-Webkit libraries. On Ubuntu, you can do this via:\n```\nsudo apt-get install libqt4-dev libqtwebkit-dev\n@@ -94,9 +96,9 @@ And then you should be able to open up your vivisect workspace with the vivbin s\n### PyQt5\n-PyQt5 is unsupported on Python 2.x. So similar steps must be followed to install PyQt5 to get the UI working that way as well.\n+Installing PyQt5 via pip is not supported in Python 2.x. So similar steps must be followed to install PyQt5 to get the UI working that way as well.\n-Install qt5:\n+Install qt5 and the webkit dependency:\n```\nsudo apt-get install qt5-default libqt5webkit5-dev\n```\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Change around wording as per atlas
|
718,770 |
14.12.2018 13:47:04
| 18,000 |
a4c6a0b021608e9f32bffe61e714da6ad5240433
|
Update vdbbin
configure the root logger for vdbbin
|
[
{
"change_type": "MODIFY",
"old_path": "vdbbin",
"new_path": "vdbbin",
"diff": "@@ -4,6 +4,7 @@ import argparse\nimport traceback\nimport logging\n+logging.basicConfig(format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nlogger = logging.getLogger()\nlogger.setLevel(logging.DEBUG) # any messages called during import will be printed\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Update vdbbin
configure the root logger for vdbbin
|
718,770 |
14.12.2018 13:49:25
| 18,000 |
90d67b2f70900cec965264a5626ce57d53508229
|
Update vdbbin
refixing vdbbin
|
[
{
"change_type": "MODIFY",
"old_path": "vdbbin",
"new_path": "vdbbin",
"diff": "@@ -4,9 +4,8 @@ import argparse\nimport traceback\nimport logging\n-logging.basicConfig(format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nlogger = logging.getLogger()\n-logger.setLevel(logging.DEBUG) # any messages called during import will be printed\n+logger.basicConfig(level=logging.DEBUG, format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nimport vdb\nimport vtrace\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Update vdbbin
refixing vdbbin
|
718,770 |
14.12.2018 14:02:09
| 18,000 |
dedcb98493221323f8cb13bf53ab675a54bcac9b
|
updates to thumb/thumb2/thumb16 naming...
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -31,7 +31,7 @@ def addAnalysisModules(vw):\nvw.addImpApi('windows','amd64')\nvw.addStructureModule('ntdll', 'vstruct.defs.windows.win_6_1_amd64.ntdll')\n- elif arch in ('arm', 'thumb', 'thumb2'):\n+ elif arch in ('arm', 'thumb', 'thumb16'):\nvw.addImpApi('windows','arm')\nvw.addConstModule('vstruct.constants.ntstatus')\n@@ -57,7 +57,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch in ('arm', 'thumb', 'thumb2'):\n+ elif arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n# See if we got lucky and got arg/local hints from symbols\n@@ -79,7 +79,7 @@ def addAnalysisModules(vw):\n# add va set for tracking thunk_bx function(s)\nvw.addVaSet('thunk_bx', ( ('fva', vivisect.VASET_ADDRESS), ) )\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.thunk_bx\")\n- elif arch in ('arm', 'thumb', 'thumb2'):\n+ elif arch in ('arm', 'thumb', 'thumb16'):\nvw.addVaSet('thunk_reg', ( ('fva', vivisect.VASET_ADDRESS), ('reg', vivisect.VASET_INTEGER), ))\nvw.addFuncAnalysisModule('vivisect.analysis.arm.thunk_reg')\nvw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\n@@ -100,7 +100,7 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch in ('arm', 'thumb', 'thumb2'):\n+ elif arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n# Find import thunks\n@@ -128,7 +128,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch in ('arm', 'thumb', 'thumb2'):\n+ elif arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n@@ -143,7 +143,7 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\n- if arch in ('arm', 'thumb', 'thumb2'):\n+ if arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.impapi\")\n@@ -156,7 +156,7 @@ def addAnalysisModules(vw):\n#vw.addAnalysisModule(\"vivisect.analysis.generic.pointertables\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.emucode\")\n- if arch in ('arm', 'thumb', 'thumb2'):\n+ if arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -11,6 +11,9 @@ import visgraph.pathcore as vg_path\nfrom vivisect.const import *\n+import logging\n+logger = logging.getLogger(__name__)\n+\n# Pre-initialize a default stack size\ninit_stack_size = 0x7fff\ninit_stack_map = b'\\xfe' * init_stack_size\n@@ -235,7 +238,7 @@ class WorkspaceEmulator:\nif len(blist) > 1:\nfor bva,bflags in blist:\nif bva == None:\n- print \"Unresolved branch even WITH an emulator?\"\n+ logger.warn(\"Unresolved branch even WITH an emulator?\")\ncontinue\nbpath = self.getBranchNode(self.curpath, bva)\n@@ -371,10 +374,10 @@ class WorkspaceEmulator:\nexcept envi.UnsupportedInstruction, e:\nif self.strictops:\n- print \"STRICTOPS: BREAK!\"\n+ logger.debug(\"STRICTOPS: BREAK!\")\nbreak\nelse:\n- print 'runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\n+ logger.debug('runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\nself.setProgramCounter(e.op.va+ e.op.size)\nexcept Exception, e:\n#traceback.print_exc()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/lookup.py",
"new_path": "vivisect/impemu/lookup.py",
"diff": "@@ -15,6 +15,6 @@ workspace_emus = {\n'amd64' :v_i_amd64.Amd64WorkspaceEmulator,\n'msp430' :v_i_msp430.Msp430WorkspaceEmulator,\n'thumb' :v_i_arm.ThumbWorkspaceEmulator,\n- 'thumb2' :v_i_arm.ThumbWorkspaceEmulator,\n+ 'thumb16' :v_i_arm.Thumb16WorkspaceEmulator,\n('windows','i386'):v_i_windows.Windowsi386Emulator,\n}\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -272,6 +272,16 @@ class ThumbWorkspaceEmulator(ArmWorkspaceEmulator):\ndef __init__(self, vw, logwrite=False, logread=False):\nArmWorkspaceEmulator.__init__(self, vw, logwrite, logread)\nself.setThumbMode()\n+ self.setMemArchitecture(envi.ARCH_THUMB)\n+\n+ def runFunction(self, funcva, stopva=None, maxhit=None, maxloop=None, tmode=None):\n+ return ArmWorkspaceEmulator.runFunction(self, funcva, stopva, maxhit, maxloop, tmode=1)\n+\n+class Thumb16WorkspaceEmulator(ArmWorkspaceEmulator):\n+ def __init__(self, vw, logwrite=False, logread=False):\n+ ArmWorkspaceEmulator.__init__(self, vw, logwrite, logread)\n+ self.setThumbMode()\n+ self.setMemArchitecture(envi.ARCH_THUMB16)\ndef runFunction(self, funcva, stopva=None, maxhit=None, maxloop=None, tmode=None):\nreturn ArmWorkspaceEmulator.runFunction(self, funcva, stopva, maxhit, maxloop, tmode=1)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -85,6 +85,8 @@ archcalls = {\n'amd64':'sysvamd64call',\n'arm':'armcall',\n'thumb':'armcall',\n+ 'thumb16':'armcall',\n+ 'aarch64':'a64call',\n}\ndef loadElfIntoWorkspace(vw, elf, filename=None):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updates to thumb/thumb2/thumb16 naming...
|
718,770 |
14.12.2018 14:23:54
| 18,000 |
ce1e9d0b8f9a4d86cdc11fb38025f6b3e2b7a85a
|
unify the ThumbModule.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/__init__.py",
"new_path": "envi/archs/thumb16/__init__.py",
"diff": "@@ -3,17 +3,8 @@ from envi.archs.arm import *\nimport disasm as th_disasm\n-class Thumb16Module(ArmModule):\n+class Thumb16Module(ThumbModule):\ndef __init__(self):\n- ArmModule.__init__(self, name='thumb16')\n- self._arch_dis = self._arch_thumb_dis\n-\n-\n-class ThumbModule(ArmModule):\n-\n- def __init__(self):\n- ArmModule.__init__(self, name='thumb')\n- self._arch_dis = self._arch_thumb_dis\n-\n+ ThumbModule.__init__(self, name='thumb16')\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
unify the ThumbModule.
|
718,770 |
16.12.2018 13:21:24
| 18,000 |
221d71c8240ccc78b5fb6407baca3eeff4044024
|
fixed (damn github editor :)
|
[
{
"change_type": "MODIFY",
"old_path": "vdbbin",
"new_path": "vdbbin",
"diff": "@@ -4,8 +4,8 @@ import argparse\nimport traceback\nimport logging\n+logging.basicConfig(level=logging.DEBUG, format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nlogger = logging.getLogger()\n-logger.basicConfig(level=logging.DEBUG, format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nimport vdb\nimport vtrace\n@@ -65,7 +65,7 @@ def main():\nparser.add_argument('-r', '--run', dest='dorunagain', default=False, action='store_true', help='Do not stop on attach')\nparser.add_argument('-s', '--snapshot', dest='snapshot', default=None, help='Load a vtrace snapshot file')\nparser.add_argument('-S', '--server', dest='doserver', default=False, action='store_true')\n- parser.add_argument('-v', '--verbose', dest='doverbose', default=False, action='count')\n+ parser.add_argument('-v', '--verbose', dest='verbose', default=False, action='count')\nparser.add_argument('-t', '--target', dest='target', default=None, help='Activate special vdb target ( -t ? for list )')\nparser.add_argument('--android', dest='doandroid', default=False, action='store_true', help='Debug Android with ADB!')\nparser.add_argument('-e', '--eventid', dest='eventid', default=None, type=int, help='Used for Windows JIT')\n"
},
{
"change_type": "MODIFY",
"old_path": "vivbin",
"new_path": "vivbin",
"diff": "@@ -10,8 +10,8 @@ import threading\nimport traceback\nimport logging\n+logging.basicConfig(level=logging.DEBUG, format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nlogger = logging.getLogger()\n-logger.basicConfig(level=logging.DEBUG, format='%(asctime)s:%(levelname)s:%(name)s: %(message)s')\nimport vivisect\nimport vivisect.cli as viv_cli\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fixed (damn github editor :)
|
718,770 |
24.12.2018 12:12:03
| 18,000 |
c6847ba3fdb2ff139b90f404daa5333e509df1f0
|
help message correction
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/cli.py",
"new_path": "vivisect/cli.py",
"diff": "@@ -226,7 +226,7 @@ class VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\n'''\nsearch opcodes/function for a pattern\n- search [-f <funcva>] [options] <pattern>\n+ searchopcodes [-f <funcva>] [options] <pattern>\n-f [fva] - focus on one function\n-c - search comments\n-o - search operands\n@@ -253,7 +253,7 @@ class VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\npattern = ' '.join(args)\nif len(pattern) == 0:\nself.vprint('you must specify a pattern')\n- return self.do_help('search')\n+ return self.do_help('searchopcodes')\nvw = self\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
help message correction
|
718,770 |
29.12.2018 23:09:28
| 18,000 |
6c4c25c652eb63934b41a2642bacfff5ece78c46
|
logging and cleanup
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -145,6 +145,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nself.addVaSet(\"Emulation Anomalies\", ((\"va\",VASET_ADDRESS),(\"Message\",VASET_STRING)))\nself.addVaSet(\"Bookmarks\", ((\"va\",VASET_ADDRESS),(\"Bookmark Name\", VASET_STRING)))\nself.addVaSet('DynamicBranches', (('va',VASET_ADDRESS),('opcode', VASET_STRING),('bflags',VASET_INTEGER)))\n+ self.addVaSet('SwitchCases', (('va', VASET_ADDRESS), ('setup_va',VASET_ADDRESS), ('Cases', VASET_INTEGER)) )\ndef verbprint(self, msg):\nif self.verbose:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -3,9 +3,12 @@ import envi\nimport vivisect\nimport vivisect.impemu.monitor as viv_monitor\n+import logging\n+\nfrom envi.archs.arm.regs import PSR_T_bit\nfrom vivisect import LOC_STRING, LOC_UNI, REF_DATA\n+logger = logging.getLogger(__name__)\nMAX_INIT_OPCODES = 30\ndef reprPointer(vw, va):\n@@ -49,11 +52,11 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\n# second operand has the register we're interested in for this function\ntgt = op.getOperValue(0, emu)\nif tgt == None:\n- emu.vw.vprint(\"0x%x: %s tgt == None!\" % (op.va, op))\n+ logger.warn(\"0x%x: %s tgt == None!\", op.va, op)\nreturn\nself.tracker[op.va] = tgt\n- #print(\"%x %s\" % (op.va, self.vw.reprVa(tgt)))\n+ #logger.debug(\"%x %s\", op.va, self.vw.reprVa(tgt))\ndef analyzeFunction(vw, fva):\n@@ -119,13 +122,13 @@ def analyzeFunction(vw, fva):\ntva += len(op)\nif op.isReturn():\n- #print \"thunk_reg: returning before finding PIE data\"\n+ logger.debug(\"thunk_reg: returning before finding PIE data\")\nbreak\nif not success:\nreturn\n- if vw.verbose: vw.vprint('funcva 0x%x using thunk_reg for PIE' % fva)\n+ logger.debug('funcva 0x%x using thunk_reg for PIE', fva)\n# now check through all the functions and track references\nemumon = AnalysisMonitor(vw, fva)\n@@ -133,7 +136,7 @@ def analyzeFunction(vw, fva):\ntry:\nemu.runFunction(fva, maxhit=1)\nexcept:\n- vw.vprint(\"Error emulating function 0x%x\\n\\t%s\" % (fva, repr(emumon.emuanom)))\n+ logger.warn(\"Error emulating function 0x%x\\n\\t%r\", fva, emumon.emuanom)\nif vw.verbose: sys.stderr.write('=')\n@@ -146,7 +149,7 @@ def analyzeFunction(vw, fva):\ntry:\nvw.followPointer(tgt)\nexcept envi.SegmentationViolation:\n- if vw.verbose: vw.vprint(\"SegV: %x (va:0x%x)\" % (tgt,va))\n+ logger.debug(\"SegV: %x (va:0x%x)\", tgt, va)\nemumon.emuanom.append(\"SegV: %x (va:0x%x)\" % (tgt,va))\ncontinue\n@@ -155,7 +158,7 @@ def analyzeFunction(vw, fva):\nif xto == tgt:\nnogo = True\nif not nogo:\n- #vw.vprint(\"PIE XREF: 0x%x -> 0x%x\" % (va, tgt))\n+ logger.debug(\"PIE XREF: 0x%x -> 0x%x\", va, tgt)\ntry:\nvw.addXref(va, tgt, REF_DATA, 0)\nexcept:\n@@ -171,9 +174,9 @@ def analyzeFunction(vw, fva):\ncmt = \"0x%x: %s ;\\n %s\" % (tgt, reprPointer(vw, tgt), curcmt)\nvw.setComment(va, cmt)\n- if vw.verbose: vw.vprint(\"PIE XREF: %x %s\" % (va, cmt))\n+ logger.debug(\"PIE XREF: %x %s\" % (va, cmt))\n- if vw.verbose: vw.vprint(\"ANOMS: \\n\", repr(emumon.emuanom))\n+ logger.debug(\"ANOMS: \\n\", repr(emumon.emuanom))\ndef analyze(vw):\n'''\n@@ -188,9 +191,9 @@ def analyze(vw):\nif globals().get('vw') != None:\nif len(argv) > 1:\nva = vw.parseExpression(argv[1])\n- vw.vprint(\"analyzing workspace function %x for thunk_reg\", va)\n+ logger.warn(\"analyzing workspace function %x for thunk_reg\", va)\nanalyzeFunction(vw, va)\nelse:\n- vw.vprint(\"analyzing workspace for thunk_reg\")\n+ logger.warn(\"analyzing workspace for thunk_reg\")\nanalyze(vw)\n- vw.vprint(\"done\")\n+ logger.warn(\"done\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -9,7 +9,7 @@ import vivisect.impemu.emulator as v_i_emulator\nimport visgraph.pathcore as vg_path\nfrom envi.archs.arm.regs import *\n-logger = logging.getLogger(\"__name__\")\n+logger = logging.getLogger(__name__)\nverbose = True\nclass ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
logging and cleanup
|
718,770 |
30.12.2018 23:18:06
| 18,000 |
24f95699b209dd1b9fb06112d7d4ee6a57e6c3e2
|
vw.parseExpression() now accurately uses vw names with the new evaluate()
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -13,9 +13,6 @@ class ExpressionFail(Exception):\nreturn self.__repr__()\ndef evaluate(pycode, locals):\n- try:\n- val = eval(pycode, {}, locals)\n- except NameError, e:\ntry:\n# check through the keys for anything we might want to replace\nkeys = locals.keys()\n@@ -26,7 +23,7 @@ def evaluate(pycode, locals):\n# replace the substrings with the string versions of the lookup value\nfor key in keys:\nif key in pycode:\n- pval = locals.get(key)\n+ pval = locals[key]\npycode = pycode.replace(key, str(pval))\nval = eval(pycode, {}, locals)\n@@ -49,9 +46,20 @@ class ExpressionLocals(dict):\ndef __getitem__(self, name):\nif self.symobj != None:\nret = self.symobj.getSymByName(name)\n- if ret != None: return ret\n+ if ret != None: return ret.value\nreturn dict.__getitem__(self, name)\n+ def __iter__(self):\n+ for va, name in self.symobj.getNames():\n+ yield name\n+\n+ dict.__iter__(self)\n+\n+ def keys(self):\n+ return [key for key in self]\n+\n+\n+\nclass MemoryExpressionLocals(ExpressionLocals):\ndef __init__(self, memobj, symobj=None):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
vw.parseExpression() now accurately uses vw names with the new evaluate()
|
718,770 |
30.12.2018 23:25:24
| 18,000 |
593c6f76cb60651b8601207784e2083658dbba85
|
return to trying the name as-is
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -13,6 +13,9 @@ class ExpressionFail(Exception):\nreturn self.__repr__()\ndef evaluate(pycode, locals):\n+ try:\n+ val = eval(pycode, {}, locals)\n+ except NameError, e:\ntry:\n# check through the keys for anything we might want to replace\nkeys = locals.keys()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
return to trying the name as-is
|
718,770 |
30.12.2018 23:45:12
| 18,000 |
72ccd477363cb22e3a36fd810aa13a18931ec3e7
|
envi unittests (with Vivisect mixins)
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": "envi/tests/test_expression.py",
"diff": "+import unittest\n+\n+import vivisect\n+import vivisect.cli\n+\n+class EnviExpressionTest(unittest.TestCase):\n+\n+ def test_viv_parseExpression(self):\n+ vw = vivisect.cli.VivCli()\n+ vw.makeName(0xfffffffe, 'foo(bar)')\n+\n+ self.assertEqual(vw.parseExpression('foo(bar) + 5'), 0x100000003L)\n+\n+ def test_envi_MemoryExpressionLocals(self):\n+ import envi.expression as e_expr\n+\n+ vw = vivisect.cli.VivCli()\n+ vw.makeName(0xfffffffe, 'foo(bar)')\n+\n+ mel = e_expr.MemoryExpressionLocals(vw, symobj=vw)\n+ self.assertEqual(mel.sym('foo(bar)'), 4294967294L)\n+\n+ def test_envi_expr_evaluate(self):\n+ import envi.expression as e_expr\n+ x={'foo(bar)': 0x40, 'foo':0x60}\n+\n+ self.assertEqual(e_expr.evaluate('foo(bar) + 1', x), 65)\n+ self.assertEqual(e_expr.evaluate('foo + 1', x), 97)\n+ self.assertEqual(e_expr.evaluate('32 + 1', x), 33)\n+\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
envi unittests (with Vivisect mixins)
|
718,770 |
08.01.2019 18:56:56
| 18,000 |
c8839090b27f2380f5604bb05b66336887af0b8e
|
* and : cause SyntaxError.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -15,7 +15,7 @@ class ExpressionFail(Exception):\ndef evaluate(pycode, locals):\ntry:\nval = eval(pycode, {}, locals)\n- except NameError, e:\n+ except (NameError, SyntaxError), e:\ntry:\n# check through the keys for anything we might want to replace\nkeys = locals.keys()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
* and : cause SyntaxError.
|
718,770 |
08.01.2019 19:09:14
| 18,000 |
86d050086819702bd26304407052f1fcdc3ba449
|
and more goodies.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -31,7 +31,7 @@ def evaluate(pycode, locals):\nval = eval(pycode, {}, locals)\n- except NameError, e:\n+ except (SyntaxError, NameError), e:\nraise ExpressionFail(pycode)\nreturn val\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
and more goodies.
|
718,770 |
08.01.2019 19:12:01
| 18,000 |
4ba935d71052c3ee4678dad28875fa0950cbbbec
|
"One that looks nice." - Knight of Ni
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -31,7 +31,7 @@ def evaluate(pycode, locals):\nval = eval(pycode, {}, locals)\n- except (SyntaxError, NameError), e:\n+ except (NameError, SyntaxError), e:\nraise ExpressionFail(pycode)\nreturn val\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
"One that looks nice." - Knight of Ni
|
718,770 |
10.01.2019 17:16:13
| 18,000 |
7021c3f97afa371d382ade9ee3aae303358bf028
|
bugfix: envi.expression throws AttributeError when "file.symbol" format is used. we may end up simply excepting all Exceptions instead of attempting to be selective.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "Unified expression helpers.\n\"\"\"\nclass ExpressionFail(Exception):\n- def __init__(self, pycode):\n+ def __init__(self, pycode, exception):\nException.__init__(self)\nself.pycode = pycode\n+ self.exception = exception\ndef __repr__(self):\n- return \"ExpressionFail: %r is not a valid expression in this context\" % self.pycode\n+ return \"ExpressionFail: %r is not a valid expression in this context (%r)\" % \\\n+ (self.pycode, self.exception)\ndef __str__(self):\nreturn self.__repr__()\n@@ -15,7 +17,7 @@ class ExpressionFail(Exception):\ndef evaluate(pycode, locals):\ntry:\nval = eval(pycode, {}, locals)\n- except (NameError, SyntaxError), e:\n+ except (NameError, SyntaxError, AttributeError), e:\ntry:\n# check through the keys for anything we might want to replace\nkeys = locals.keys()\n@@ -31,8 +33,8 @@ def evaluate(pycode, locals):\nval = eval(pycode, {}, locals)\n- except (NameError, SyntaxError), e:\n- raise ExpressionFail(pycode)\n+ except (NameError, SyntaxError, AttributeError), e:\n+ raise ExpressionFail(pycode, e)\nreturn val\n@@ -52,6 +54,8 @@ class ExpressionLocals(dict):\nif ret != None: return ret.value\nreturn dict.__getitem__(self, name)\n+ get = __getitem__\n+\ndef __iter__(self):\nfor va, name in self.symobj.getNames():\nyield name\n@@ -61,6 +65,10 @@ class ExpressionLocals(dict):\ndef keys(self):\nreturn [key for key in self]\n+ def has_key(self, key):\n+ return self.__getitem__(key) != None\n+\n+ __contains__ = has_key\nclass MemoryExpressionLocals(ExpressionLocals):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: envi.expression throws AttributeError when "file.symbol" format is used. we may end up simply excepting all Exceptions instead of attempting to be selective.
|
718,770 |
10.01.2019 17:21:39
| 18,000 |
cfb0329096b3acdbeb9c3c11add607180f38192f
|
ah fukit. broadening the net to try substitution regardless of the exception
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -17,7 +17,7 @@ class ExpressionFail(Exception):\ndef evaluate(pycode, locals):\ntry:\nval = eval(pycode, {}, locals)\n- except (NameError, SyntaxError, AttributeError), e:\n+ except Exception, e:\ntry:\n# check through the keys for anything we might want to replace\nkeys = locals.keys()\n@@ -33,7 +33,7 @@ def evaluate(pycode, locals):\nval = eval(pycode, {}, locals)\n- except (NameError, SyntaxError, AttributeError), e:\n+ except Exception, e:\nraise ExpressionFail(pycode, e)\nreturn val\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
ah fukit. broadening the net to try substitution regardless of the exception
|
718,770 |
10.01.2019 22:55:43
| 18,000 |
9efb8010ab00a8335dcfb21f143a2484b2448b6b
|
aesthetics ocd.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -65,10 +65,10 @@ class ExpressionLocals(dict):\ndef keys(self):\nreturn [key for key in self]\n- def has_key(self, key):\n+ def __contains__(self, key):\nreturn self.__getitem__(key) != None\n- __contains__ = has_key\n+ has_key = __contains__\nclass MemoryExpressionLocals(ExpressionLocals):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
aesthetics ocd.
|
718,770 |
04.02.2018 23:52:25
| 18,000 |
d3d53067a06cdd817b61236c62952e88906421d4
|
elf parsing, naming and name-demangling.
|
[
{
"change_type": "MODIFY",
"old_path": "Elf/__init__.py",
"new_path": "Elf/__init__.py",
"diff": "@@ -523,6 +523,7 @@ class Elf(vs_elf.Elf32, vs_elf.Elf64):\nif sec.sh_type != SHT_NOTE:\ncontinue\n+ try:\nnotebytes = self.readAtOffset(sec.sh_offset, sec.sh_size)\noffset = 0\nnotebyteslen = len(notebytes)\n@@ -534,6 +535,8 @@ class Elf(vs_elf.Elf32, vs_elf.Elf64):\noffset = note.vsParse(notebytes,offset=offset)\nyield note\n+ except Exception, e:\n+ print \"Elf.getNotes() Exception: %r\" % e\ndef getPlatform(self):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -23,24 +23,23 @@ def analyze(vw):\nsva += ltup[vivisect.L_SIZE]\ndef analyzeFunction(vw, funcva):\n-\nseg = vw.getSegment(funcva)\nif seg == None:\nreturn\nsegva, segsize, segname, segfname = seg\n- if segname != \".plt\":\n+ if segname not in (\".plt\", \".plt.got\"):\nreturn\n- #FIXME check for i386\nop = vw.parseOpcode(funcva)\n- if op.opcode != opcode86.INS_BRANCH:\n+ if op.iflags & envi.IF_BRANCH == 0:\nreturn\nloctup = None\noper0 = op.opers[0]\n-\n+ opval = oper0.getOperAddr(op)\n+ \"\"\"\nif isinstance(oper0, e_i386.i386ImmMemOper):\nloctup = vw.getLocation(oper0.getOperAddr(op))\n@@ -60,15 +59,19 @@ def analyzeFunction(vw, funcva):\nif got != None:\nloctup = vw.getLocation(got+oper0.disp)\n+ \"\"\"\n+\n+ loctup = vw.getLocation(opval)\nif loctup == None:\nreturn\n- if loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT:\n- return\n+ if loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT: # FIXME: Why are AMD64 IMPORTS showing up as POINTERs?\n+ print \"0x%x: \" % funcva, loctup[vivisect.L_LTYPE], ' != ', vivisect.LOC_IMPORT\n+ #return\n- tinfo = loctup[vivisect.L_TINFO]\n- lname,fname = tinfo.split(\".\")\n+ gotname = vw.getName(opval)\n+ tinfo = gotname\n#vw.makeName(funcva, \"plt_%s\" % fname, filelocal=True)\nvw.makeFunctionThunk(funcva, tinfo)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -86,18 +86,20 @@ archcalls = {\n'arm':'armcall',\n}\n-def loadElfIntoWorkspace(vw, elf, filename=None):\n+def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filefmt='elf'):\n+ if arch == None:\narch = arch_names.get(elf.e_machine)\nif arch == None:\nraise Exception(\"Unsupported Architecture: %d\\n\", elf.e_machine)\n+ if platform == None:\nplatform = elf.getPlatform()\n# setup needed platform/format\nvw.setMeta('Architecture', arch)\nvw.setMeta('Platform', platform)\n- vw.setMeta('Format', 'elf')\n+ vw.setMeta('Format', filefmt)\nvw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\n@@ -130,6 +132,8 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nfor pgm in pgms:\nif pgm.p_type == Elf.PT_LOAD:\n+ if pgm.p_memsz == 0:\n+ continue\nif vw.verbose: vw.vprint('Loading: %s' % (repr(pgm)))\nbytez = elf.readAtOffset(pgm.p_offset, pgm.p_filesz)\nbytez += \"\\x00\" * (pgm.p_memsz - pgm.p_filesz)\n@@ -222,10 +226,11 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nmakeRelocTable(vw, sva, sva+size, addbase, baseaddr)\nif sec.sh_flags & Elf.SHF_STRINGS:\n- print \"FIXME HANDLE SHF STRINGS\"\n+ makeStringTable(vw, sva, sva+size)\n# Let pyelf do all the stupid string parsing...\n- for r in elf.getRelocs():\n+ relocs = elf.getRelocs()\n+ for r in relocs:\nrtype = Elf.getRelocType(r.r_info)\nrlva = r.r_offset\nif addbase: rlva += baseaddr\n@@ -234,7 +239,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\n# resolved \"import\" entry, otherwise, just a regular reloc\nif arch in ('i386','amd64'):\n- name = r.getName()\n+ name = decode(r.getName())\nif name:\nif rtype == Elf.R_386_JMP_SLOT:\nvw.makeImport(rlva, \"*\", name)\n@@ -246,9 +251,13 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nelif rtype == Elf.R_386_32:\npass\n+ elif rtype == Elf.R_X86_64_GLOB_DAT:\n+ vw.makeImport(rlva, \"*\", name)\n+\nelse:\nvw.verbprint('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n+\nif arch == 'arm':\nname = r.getName()\nif name:\n@@ -270,9 +279,12 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif sva == 0:\ncontinue\n+ decodedname = decode(s.name)\n+ sname = pyfriendlyName(decodedname)\n+\nif stype == Elf.STT_FUNC or (stype == Elf.STT_GNU_IFUNC and arch in ('i386','amd64')): # HACK: linux is what we're really after.\ntry:\n- vw.addExport(sva, EXP_FUNCTION, s.name, fname)\n+ vw.addExport(sva, EXP_FUNCTION, sname, fname)\nvw.addEntryPoint(sva)\nexcept Exception, e:\nvw.vprint('addExport Failure: %s' % e)\n@@ -280,7 +292,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nelif stype == Elf.STT_OBJECT:\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_DATA, s.name, fname)\n+ vw.addExport(sva, EXP_DATA, sname, fname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -291,7 +303,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_FUNCTION, s.name, fname)\n+ vw.addExport(sva, EXP_FUNCTION, sname, fname)\nvw.addEntryPoint(sva)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -303,7 +315,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_DATA, s.name, fname)\n+ vw.addExport(sva, EXP_DATA, sname, fname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -323,18 +335,91 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nfor s in elf.getSymbols():\nsva = s.st_value\n+\n+ # if the symbol has a value of 0, it is likely a relocation point which gets updated\n+ sname = normName(s.name)\n+ if sva == 0:\n+ for reloc in relocs:\n+ rname = normName(reloc.name)\n+ if rname == sname:\n+ sva = reloc.r_offset\n+ break\n+\n+ decodedname = decode(sname)\n+ sname = pyfriendlyName(decodedname)\n+\nif addbase: sva += baseaddr\n- if vw.isValidPointer(sva) and len(s.name):\n+ vw.setComment(sva, decodedname)\n+ if vw.isValidPointer(sva) and len(sname):\ntry:\n- vw.makeName(sva, s.name, filelocal=True)\n+ vw.makeName(sva, \"%s_%x\" % (sname,sva), filelocal=True)\nexcept Exception, e:\nprint \"WARNING:\",e\n- if vw.isValidPointer(elf.e_entry):\n- vw.addExport(elf.e_entry, EXP_FUNCTION, '__entry', fname)\n- vw.addEntryPoint(elf.e_entry)\n+ if addbase:\n+ eentry = baseaddr + elf.e_entry\n+ else:\n+ eentry = elf.e_entry\n+\n+ if vw.isValidPointer(eentry):\n+ vw.addExport(eentry, EXP_FUNCTION, '__entry', fname)\n+ vw.addEntryPoint(eentry)\nif vw.isValidPointer(baseaddr):\nvw.makeStructure(baseaddr, \"elf.Elf32\")\nreturn fname\n+\n+def normName(name):\n+ atidx = name.find('@@')\n+ if atidx > -1:\n+ name = name[:atidx]\n+ return name\n+\n+import string\n+chars_ok = string.letters + string.digits + '_'# + ':'# + '~'\n+chars_cok = (\"%$#*<>~\")\n+\n+def pyfriendlyName(name):\n+ out = []\n+ normname = os.path.basename(name)\n+\n+ lastcok = False\n+ chars = list(normname)\n+\n+ for i in xrange(len(chars)):\n+ if chars[i] not in chars_ok:\n+ if chars[i] in chars_cok:\n+ x = \"%.2X\" % ord(chars[i])\n+ out.append(x)\n+ if not lastcok:\n+ # prepend on front\n+ out.insert(i, '_')\n+\n+ lastcok = True\n+\n+ else:\n+ out.append('_')\n+ lastcok = False\n+\n+ else:\n+ if lastcok:\n+ # if last was a 'cok' and this is just ok...\n+ out.append('_')\n+ out.append(chars[i])\n+\n+ lastcok = False\n+\n+ normname = ''.join(out)\n+ return normname\n+\n+def decode(name):\n+ name = normName(name)\n+\n+ try:\n+ import cxxfilt\n+ name = cxxfilt.demangle(name)\n+ except:\n+ pass\n+\n+ return name\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
elf parsing, naming and name-demangling.
|
718,770 |
11.04.2018 15:58:47
| 14,400 |
51503e42fc8a7940c83c567a0c2882a8a3e08677
|
print cleanup.
|
[
{
"change_type": "MODIFY",
"old_path": "Elf/__init__.py",
"new_path": "Elf/__init__.py",
"diff": "@@ -536,7 +536,7 @@ class Elf(vs_elf.Elf32, vs_elf.Elf64):\noffset = note.vsParse(notebytes,offset=offset)\nyield note\nexcept Exception, e:\n- print \"Elf.getNotes() Exception: %r\" % e\n+ print(\"Elf.getNotes() Exception: %r\" % e)\ndef getPlatform(self):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
print cleanup.
|
718,770 |
05.01.2019 23:40:06
| 18,000 |
706613da92174e653e8f27238bafbe6fdc40a71f
|
melding together the three naming branches. still to clean up the name-normalizing code...
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -14,8 +14,9 @@ def analyze(vw):\nDo simple linear disassembly of the .plt section if present.\n\"\"\"\nfor sva,ssize,sname,sfname in vw.getSegments():\n- if sname != \".plt\":\n+ if sname not in (\".plt\", \".plt.got\"):\ncontinue\n+\nnextva = sva + ssize\nwhile sva < nextva:\nvw.makeCode(sva)\n@@ -50,6 +51,6 @@ def analyzeFunction(vw, funcva):\ngotname = vw.getName(opval)\ntinfo = gotname\n- #vw.makeName(funcva, \"plt_%s\" % fname, filelocal=True)\n+ vw.makeName(funcva, \"plt_%s\" % fname, filelocal=True)\nvw.makeFunctionThunk(funcva, tinfo)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/blob.py",
"new_path": "vivisect/parsers/blob.py",
"diff": "@@ -8,6 +8,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef parseFd(vw, fd, filename=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -84,6 +84,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filefmt='elf'):\n@@ -286,6 +288,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\ntry:\nvw.addExport(sva, EXP_FUNCTION, sname, fname)\nvw.addEntryPoint(sva)\n+ if decodedname != sname: vw.setComment(sva, decodedname)\nexcept Exception, e:\nvw.vprint('addExport Failure: %s' % e)\n@@ -293,6 +296,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nif vw.isValidPointer(sva):\ntry:\nvw.addExport(sva, EXP_DATA, sname, fname)\n+ if decodedname != sname: vw.setComment(sva, decodedname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -305,6 +309,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\ntry:\nvw.addExport(sva, EXP_FUNCTION, sname, fname)\nvw.addEntryPoint(sva)\n+ if decodedname != sname: vw.setComment(sva, decodedname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -316,6 +321,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nif vw.isValidPointer(sva):\ntry:\nvw.addExport(sva, EXP_DATA, sname, fname)\n+ if decodedname != sname: vw.setComment(sva, decodedname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -345,14 +351,15 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nsva = reloc.r_offset\nbreak\n+ origname = sname\ndecodedname = decode(sname)\nsname = pyfriendlyName(decodedname)\nif addbase: sva += baseaddr\n- vw.setComment(sva, decodedname)\n+ if decodedname != sname: vw.setComment(sva, decodedname)\nif vw.isValidPointer(sva) and len(sname):\ntry:\n- vw.makeName(sva, \"%s_%x\" % (sname,sva), filelocal=True)\n+ vw.makeName(sva, sname, filelocal=True)\nexcept Exception, e:\nprint \"WARNING:\",e\n@@ -371,6 +378,9 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nreturn fname\ndef normName(name):\n+ '''\n+ Normalize symbol names. ie. drop the @@GOBBLEDEGOOK from the end\n+ '''\natidx = name.find('@@')\nif atidx > -1:\nname = name[:atidx]\n@@ -381,6 +391,10 @@ chars_ok = string.letters + string.digits + '_'# + ':'# + '~'\nchars_cok = (\"%$#*<>~\")\ndef pyfriendlyName(name):\n+ '''\n+ Convert a C++ name into a Python-Friendly name (ie. name could become a variable in the\n+ Python environment)\n+ '''\nout = []\nnormname = os.path.basename(name)\n@@ -414,6 +428,9 @@ def pyfriendlyName(name):\nreturn normname\ndef decode(name):\n+ '''\n+ Translate C++ mangled name back into the verbose C++ symbol name (with helpful type info)\n+ '''\nname = normName(name)\ntry:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/ihex.py",
"new_path": "vivisect/parsers/ihex.py",
"diff": "@@ -9,6 +9,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef parseFile(vw, filename):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/macho.py",
"new_path": "vivisect/parsers/macho.py",
"diff": "@@ -15,6 +15,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef _loadMacho(vw, filebytes, filename=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -54,6 +54,8 @@ defcalls = {\n'i386':'cdecl',\n'amd64':'msx64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\n# map PE relocation types to vivisect types where possible\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
melding together the three naming branches. still to clean up the name-normalizing code...
|
718,770 |
08.01.2019 16:07:47
| 18,000 |
6c08e15511d7f7f556b0bb06729e340d1bc5a3b8
|
improved duplicate naming
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -744,8 +744,9 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nAdd an already created export object.\n\"\"\"\nrname = \"%s.%s\" % (filename,name)\n- if self.vaByName(rname) != None:\n- raise Exception(\"Duplicate Name: %s\" % rname)\n+ curval = self.vaByName(rname)\n+ if curval != None:\n+ raise Exception(\"Duplicate Name: %s => 0x%x (cur: 0x%x)\" % (rname, va, curval))\nself._fireEvent(VWE_ADDEXPORT, (va,etype,name,filename))\ndef getExport(self, va):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
improved duplicate naming
|
718,770 |
10.01.2019 23:51:30
| 18,000 |
96abfe2f2f8a6439e5626326dd3f6257ab0e3335
|
naming enhancements, bug-fixes, and general make-it-work-rightness.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -739,14 +739,28 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n\"\"\"\nreturn list(self.exports)\n- def addExport(self, va, etype, name, filename):\n+ def addExport(self, va, etype, name, filename, makeuniq=False):\n\"\"\"\nAdd an already created export object.\n\"\"\"\nrname = \"%s.%s\" % (filename,name)\n+\n+ # check if it exists\ncurval = self.vaByName(rname)\nif curval != None:\n+ # if we don't force it to make a uniq name, bail\n+ if not makeuniq:\nraise Exception(\"Duplicate Name: %s => 0x%x (cur: 0x%x)\" % (rname, va, curval))\n+\n+ # otherwise, tack a number on the end\n+ index = 0\n+ newname = \"%s.%d\" % (rname, index)\n+ while self.vaByName(newname) != None:\n+ index += 1\n+ newname = \"%s.%d\" % (rname, index)\n+\n+ name = \"%s.%d\" % (name, index)\n+\nself._fireEvent(VWE_ADDEXPORT, (va,etype,name,filename))\ndef getExport(self, va):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -38,7 +38,7 @@ def analyzeFunction(vw, funcva):\nreturn\noper0 = op.opers[0]\n- opval = oper0.getOperAddr(op)\n+ opval = oper0.getOperAddr(op, None)\nloctup = vw.getLocation(opval)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -241,7 +241,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\n# resolved \"import\" entry, otherwise, just a regular reloc\nif arch in ('i386','amd64'):\n- name = decode(r.getName())\n+ name = demangle(r.getName())\nif name:\nif rtype == Elf.R_386_JMP_SLOT:\nvw.makeImport(rlva, \"*\", name)\n@@ -275,28 +275,26 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nfor s in elf.getDynSyms():\nstype = s.getInfoType()\nsva = s.st_value\n+\nif sva == 0:\ncontinue\nif addbase: sva += baseaddr\nif sva == 0:\ncontinue\n- decodedname = decode(s.name)\n- sname = pyfriendlyName(decodedname)\n+ demangledname = demangle(s.name)\nif stype == Elf.STT_FUNC or (stype == Elf.STT_GNU_IFUNC and arch in ('i386','amd64')): # HACK: linux is what we're really after.\ntry:\n- vw.addExport(sva, EXP_FUNCTION, sname, fname)\nvw.addEntryPoint(sva)\n- if decodedname != sname: vw.setComment(sva, decodedname)\n+ vw.addExport(sva, EXP_FUNCTION, demangledname, fname, makeuniq=True)\nexcept Exception, e:\n- vw.vprint('addExport Failure: %s' % e)\n+ vw.vprint('addExport Failure: (%s) %s' % (s.name, e))\nelif stype == Elf.STT_OBJECT:\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_DATA, sname, fname)\n- if decodedname != sname: vw.setComment(sva, decodedname)\n+ vw.addExport(sva, EXP_DATA, demangledname, fname, makeuniq=True)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -307,9 +305,8 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_FUNCTION, sname, fname)\nvw.addEntryPoint(sva)\n- if decodedname != sname: vw.setComment(sva, decodedname)\n+ vw.addExport(sva, EXP_FUNCTION, demangledname, fname, makeuniq=True)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -320,8 +317,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_DATA, sname, fname)\n- if decodedname != sname: vw.setComment(sva, decodedname)\n+ vw.addExport(sva, EXP_DATA, demangledname, fname, makeuniq=True)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -352,14 +348,12 @@ def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filef\nbreak\norigname = sname\n- decodedname = decode(sname)\n- sname = pyfriendlyName(decodedname)\n+ demangledname = demangle(sname)\nif addbase: sva += baseaddr\n- if decodedname != sname: vw.setComment(sva, decodedname)\n- if vw.isValidPointer(sva) and len(sname):\n+ if vw.isValidPointer(sva) and len(demangledname):\ntry:\n- vw.makeName(sva, sname, filelocal=True)\n+ vw.makeName(sva, demangledname, filelocal=True)\nexcept Exception, e:\nprint \"WARNING:\",e\n@@ -386,48 +380,7 @@ def normName(name):\nname = name[:atidx]\nreturn name\n-import string\n-chars_ok = string.letters + string.digits + '_'# + ':'# + '~'\n-chars_cok = (\"%$#*<>~\")\n-\n-def pyfriendlyName(name):\n- '''\n- Convert a C++ name into a Python-Friendly name (ie. name could become a variable in the\n- Python environment)\n- '''\n- out = []\n- normname = os.path.basename(name)\n-\n- lastcok = False\n- chars = list(normname)\n-\n- for i in xrange(len(chars)):\n- if chars[i] not in chars_ok:\n- if chars[i] in chars_cok:\n- x = \"%.2X\" % ord(chars[i])\n- out.append(x)\n- if not lastcok:\n- # prepend on front\n- out.insert(i, '_')\n-\n- lastcok = True\n-\n- else:\n- out.append('_')\n- lastcok = False\n-\n- else:\n- if lastcok:\n- # if last was a 'cok' and this is just ok...\n- out.append('_')\n- out.append(chars[i])\n-\n- lastcok = False\n-\n- normname = ''.join(out)\n- return normname\n-\n-def decode(name):\n+def demangle(name):\n'''\nTranslate C++ mangled name back into the verbose C++ symbol name (with helpful type info)\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
naming enhancements, bug-fixes, and general make-it-work-rightness.
|
718,770 |
11.01.2019 20:09:32
| 18,000 |
d2b397872676bbd3d5e795fef0d1221c1ae550dc
|
cleanup disasm.py
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -152,7 +152,7 @@ shifters = (\ndp_mnem = (\n(\"and\", INS_AND),\n(\"eor\", INS_EOR),\n- (\"sub\", INS_EOR),\n+ (\"sub\", INS_SUB),\n(\"rsb\", INS_RSB),\n(\"add\", INS_ADD),\n(\"adc\", INS_ADC),\n@@ -178,8 +178,8 @@ dp_shift_mnem = (\n)\n# THIS IS FUGLY but sadly it works\n-dp_noRn = (13,15)\n-dp_noRd = (8,9,10,11)\n+dp_noRn = (INS_MOV,INS_MVN)\n+dp_noRd = (INS_TST,INS_TEQ,INS_CMP,INS_CMN)\ndp_silS = dp_noRd\n# IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\n@@ -189,7 +189,7 @@ for x in dp_silS:\n# FIXME: dp_MOV was supposed to be a tuple of opcodes that could be converted to MOV's if offset from PC.\n# somehow this list has vanished into the ether. add seems like the right one here.\n-dp_ADR = (2, 4,)\n+dp_ADR = (INS_SUB, INS_ADD,)\n# FIXME: !!! Don't make SBZ and SBO's part of the list of opers !!!\n@@ -215,16 +215,16 @@ def p_dp_imm_shift(opval, va):\nRm = opval & 0xf\nshtype = (opval >> 5) & 0x3\nshval = (opval >> 7) & 0x1f # effectively, rot*2\n- if (shtype==3) & (shval ==0): # is it an rrx?\n- shtype = 4\n+ if (shtype==S_ROR) & (shval ==0): # is it an rrx?\n+ shtype = S_RRX\nmnem, opcode = dp_mnem[ocode]\niflags = 0\nif ocode in dp_noRn:\n#is it a mov? Only if shval is a 0, type is lsl, and ocode = 13\n- if (ocode == 13) and ((shval != 0) or (shtype != 0)):\n+ if (ocode == INS_MOV) and ((shval != 0) or (shtype != S_LSL)):\nmnem, opcode = dp_shift_mnem[shtype]\n- if shtype!= 4: #if not rrx\n+ if shtype!= S_RRX: #if not rrx\nolist = (\nArmRegOper(Rd, va=va),\nArmRegOper(Rm, va=va),\n@@ -1699,10 +1699,9 @@ pld_mnem = ((\"pldw\", INS_PLDW), (\"pld\", INS_PLD))\npl_opcode = (INS_PLI, INS_PLD)\ndef p_uncond(opval, va, psize = 4):\nif opval & 0x0f000000 == 0x0f000000:\n- # FIXME THIS IS HORKED?\n- opcode = INS_SVC\n+ opcode = INS_UNDEF\nimmval = opval & 0x00ffffff\n- return (opcode, 'svc', (ArmImmOper(immval),), 0, 0)\n+ return (opcode, 'undefined', (ArmImmOper(immval),), 0, 0)\noptop = ( opval >> 26 ) & 0x3\nif optop == 0:\n@@ -1722,11 +1721,8 @@ def p_uncond(opval, va, psize = 4):\nArmCPSFlagsOper(aif) # if mode is set...\n]\n- if imod & 1: # interrupt disable\n- iflags |= IF_ID\n-\n- else: # interrupt enable\n- iflags |= IF_IE\n+ # interrupt enable/disable (imod & 1)\n+ iflags |= (IF_IE, IF_ID, IF_IE, IF_ID)\nelse:\nolist = []\n@@ -1744,7 +1740,7 @@ def p_uncond(opval, va, psize = 4):\nreturn (opcode, mnem, olist, 0, 0)\nelif (opval & 0xfe000000 == 0xf2000000):\n- #print \"handing off to adv_simd_32\"\n+ # handing off to adv_simd_32\nreturn adv_simd_32(opval, va)\nelse:\n@@ -1895,6 +1891,7 @@ def p_uncond(opval, va, psize = 4):\nelif (opval & 0xff000010) == 0xfe000000:\n#coproc dp (cdp2)\nreturn p_coproc_dp(opval, va)\n+\nelif (opval & 0xff000010) == 0xfe000010:\n#mcr2/mrc2\nopcode1 = (opval>>21) & 0x7\n@@ -4068,9 +4065,8 @@ class ArmRegShiftRegOper(ArmOperand):\nmcanv.addNameText(arm_regs[self.shreg][0], typename='registers')\ndef repr(self, op):\n- rname = arm_regs[self.reg][0]+\", \"\n- rname+=shift_names[self.shtype] #Changed to remove extra spaces\n- rname+= arm_regs[self.shreg][0]\n+ rname = \"%s, %s %s\" % (arm_regs[self.reg][0], \\\n+ shift_names[self.shtype],arm_regs[self.shreg][0])\nreturn rname\nclass ArmRegShiftImmOper(ArmOperand):\n@@ -4285,7 +4281,6 @@ class ArmScaledOffsetOper(ArmOperand):\nif emu == None:\nreturn None\n- #base = emu.getRegister(self.base_reg)\nbase = self._getOperBase(emu)\npom = (-1, 1)[(self.pubwl>>3)&1]\n@@ -4719,12 +4714,7 @@ class ArmPgmStatRegOper(ArmOperand):\nnewpsr = psr & (~self.mask) | (val & self.mask)\nemu.setSPSR(mode, newpsr)\n- #elif self.psr == PSR_APSR: # APSR is an alias for CPSR\n- # psr = emu.getCPSR()\n- # newpsr = psr & (~self.mask) | (val & self.mask)\n- # emu.setCPSR(newpsr)\n-\n- else: # CPSR\n+ else: # CPSR (APSR is an alias for CPSR)\npsr = emu.getCPSR()\nnewpsr = psr & (~self.mask) | (val & self.mask)\nemu.setCPSR(newpsr)\n@@ -4804,7 +4794,6 @@ class ArmRegListOper(ArmOperand):\nreturn reglist\ndef repr(self, op):\n- #fixed register list. Should be {r1, r2, r3 ..} not { r1 r2 r3 ..}\ns = [ \"{\" ]\nregs = [arm_regs[l][0] for l in range(16) if (self.val & (1<<l))]\ns.append(', '.join(regs))\n@@ -4814,6 +4803,9 @@ class ArmRegListOper(ArmOperand):\nreturn \"\".join(s)\nclass ArmExtRegListOper(ArmOperand):\n+ '''\n+ extended register list: Vector/FP registers\n+ '''\ndef __init__(self, firstreg, count, size):\nself.firstreg = firstreg\nself.count = count\n@@ -4838,8 +4830,6 @@ class ArmExtRegListOper(ArmOperand):\nmcanv.addText('{')\ntop = self.count-1\nfor l in xrange(self.count):\n- #vreg = REGS_VECTOR_BASE_IDX + self.firstreg + l\n- #mcanv.addNameText(arm_regs[l][0], typename='registers')\nvreg = self.firstreg + l\nmcanv.addNameText(regbase % vreg, typename='registers')\nif l < top:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup disasm.py
|
718,770 |
11.01.2019 23:01:30
| 18,000 |
1675e89fd36609ecbd8d8085b1b5eeb8edb459ed
|
bugfix: bfi shifting issue
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1013,7 +1013,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nmask <<= lsb\nval = self.getOperValue(op, 0) & ~mask\n- val |= addit\n+ val |= (addit<<lsb)\n#print \"bfi: 2 \", bin(mask), bin(val)\nself.setOperValue(op, 0, val)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: bfi shifting issue
|
718,770 |
11.01.2019 23:01:49
| 18,000 |
f8ec3943f2504aefdd2b954ffd180e4f57bd5190
|
bfi unit test
|
[
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -889,7 +889,10 @@ instrs = [\n{'setup':(('r1',0xaaaaaaaa),),\n'tests':(('r1',0b10101010101010101000000000000000),) },\n)),\n- (REV_ALL_ARM, '1432cfe7', 0x4560, 'bfi r3, r4, #0x04, #0x0f', 0, ()),\n+ (REV_ALL_ARM, '1432cfe7', 0x4560, 'bfi r3, r4, #0x04, #0x0f', 0, (\n+ {'setup':(('r3', 0x55555555),('r4',0xabcdef),),\n+ 'tests':(('r3',0x5554def5),) },\n+ )),\n(REV_ALL_ARM, 'fff053f5', 0x4560, 'pld [r3, #-0xff]', 0, ()),\n(REV_ALL_ARM, 'fff0d3f5', 0x4560, 'pld [r3, #0xff]', 0, ()),\n(REV_ALL_ARM, 'fff013f5', 0x4560, 'pldw [r3, #-0xff]', 0, ()),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bfi unit test
|
718,770 |
14.01.2019 23:52:29
| 18,000 |
2f25c927036810c8bd074c822b1b56f07754a8a9
|
more cleanup, better exception handling.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/cli.py",
"new_path": "vivisect/cli.py",
"diff": "The vivisect CLI.\n\"\"\"\n+import sys\nimport shlex\nimport pprint\nimport socket\n@@ -278,9 +279,9 @@ class VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\nres = []\ncanv = e_canvas.StringMemoryCanvas(vw)\n- try:\ndefaultSearchAll = True\nfor va in valist:\n+ try:\naddthis = False\nop = vw.parseOpcode(va)\n@@ -344,9 +345,8 @@ class VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\n# only want one listing of each va, no matter how many times it matches\nif addthis:\nres.append(va)\n-\nexcept:\n- vw.vprint('\\n'.join(traceback.format_exception(*sys.exc_info())))\n+ vw.vprint(''.join(traceback.format_exception(*sys.exc_info())))\nif len(res) == 0:\nself.vprint('pattern not found: %s (%s)' % (pattern.encode('hex'), repr(pattern)))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
more cleanup, better exception handling.
|
718,770 |
15.01.2019 00:14:43
| 18,000 |
b8195f9e2948ec6c5b88587201c7b606f223f24a
|
cleanup (largely of print statements), and bugfix/better parsing/handling of UNDEFINED instructions.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -737,6 +737,7 @@ instrnames = [\n'RFE',\n'SRS',\n'HINT',\n+ 'UNDEF',\n]\nins_index = 0\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -240,7 +240,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# IT block handling\nif self.itcount:\nself.itcount -= 1\n- print \"untested IT functionality\"\n+\nif not (self.itmask & 1):\nskip = True\nself.itmask >>= 1\n@@ -484,7 +484,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# get the necessary flags here, *or* we can just do both a signed and\n# unsigned sub and use the results.\n-\nudst = e_bits.unsigned(src1, tsize)\nusrc = e_bits.unsigned(src2, tsize)\n@@ -535,17 +534,17 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef interrupt(self, val):\nif val >= len(self.int_handlers):\n- print(\"FIXME: Interrupt Handler %x is not handled\") % val\n+ logger.critical(\"FIXME: Interrupt Handler %x is not handled\", val)\nhandler = self.int_handlers[val]\nhandler(val)\ndef default_int_handler(self, val):\n- print(\"DEFAULT INTERRUPT HANDLER for Interrupt %d (called at 0x%x)\" % (val, self.getProgramCounter()))\n- print(\"Stack Dump:\")\n+ logger.warn(\"DEFAULT INTERRUPT HANDLER for Interrupt %d (called at 0x%x)\", val, self.getProgramCounter())\n+ logger.warn(\"Stack Dump:\")\nsp = self.getStackCounter()\nfor x in range(16):\n- print(\"\\t0x%x:\\t0x%x\" % (sp, self.readMemValue(sp, self.psize)))\n+ logger.warn(\"\\t0x%x:\\t0x%x\", sp, self.readMemValue(sp, self.psize))\nsp += self.psize\ndef i_and(self, op):\n@@ -575,7 +574,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nsrcreg = op.opers[0].reg\naddr = self.getOperValue(op,0)\nregvals = self.getOperValue(op, 1)\n- #regmask = op.opers[1].val\n+\nupdatereg = op.opers[0].oflags & OF_W\nflags = op.iflags\nelse:\n@@ -697,7 +696,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif isinstance(op.opers[1], ArmImmOper):\n# immediate version copies immediate into each element (Q=2 elements, D=1)\nsrcsz = op.opers[1].size\n- print \"0x%x vmov: immediate: %x (%d bytes)\" % (op.va, src, srcsz)\n+ logger.warn(\"0x%x vmov: immediate: %x (%d bytes)\", op.va, src, srcsz)\n# change src to fill all vectors with immediate\n# vreg to vreg: 1 to 1 copy\n@@ -741,7 +740,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nsrc1 = self.getOperValue(op, 0)\nsrc2 = self.getOperValue(op, 1)\nval = src2 - src1\n- #print \"vcmpe %r %r %r\" % (src1, src2, val)\n+ logger.debug(\"vcmpe %r %r %r\", src1, src2, val)\nfpsrc = self.getRegister(REG_FPSCR)\n# taken from VFCompare() from arch ref manual p80\n@@ -757,7 +756,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setFpFlag(PSR_C_bit, c)\nself.setFpFlag(PSR_V_bit, v)\nexcept Exception, e:\n- print(\"vcmp exception: %r\" % e)\n+ logger.warn(\"vcmp exception: %r\", e)\ndef i_vcmpe(self, op):\ntry:\n@@ -768,7 +767,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = src2 - src1\n- #print \"vcmpe %r %r %r %r\" % (op, src1, src2, val)\n+ logger.debug(\"vcmpe %r %r %r %r\", op, src1, src2, val)\nfpsrc = self.getRegister(REG_FPSCR)\n# taken from VFCompare() from arch ref manual p80\n@@ -784,15 +783,15 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setFpFlag(PSR_C_bit, c)\nself.setFpFlag(PSR_V_bit, v)\nexcept Exception, e:\n- print(\"vcmpe exception: %r\" % e)\n+ logger.warn(\"vcmpe exception: %r\" % e)\ndef i_vcvt(self, op):\n- print op, op.opers\n- print(\"complete implementing vcvt\")\n+ logger.warn('%r\\t%r', op, op.opers)\n+ logger.warn(\"complete implementing vcvt\")\nwidth = op.opers[0].getWidth()\nregcnt = width / 4\n-\n+ raise Exception(\"IMPLEMENT ME: i_vcvt\")\nif len(op.opers) == 3:\nfor reg in range(regcnt):\n#frac_bits = 64 - op.opers[2].val\n@@ -835,7 +834,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif len(op.opers) == 2:\nsrcreg = op.opers[0].reg\naddr = self.getOperValue(op,0)\n- #regmask = self.getOperValue(op,1)\nregmask = op.opers[1].val\nupdatereg = op.opers[0].oflags & OF_W\nflags = op.iflags\n@@ -941,14 +939,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setRegister(REG_FPSCR, val)\n- #def i_vmrs(self, op):\n- #val = self.getRegister(REG_FPSCR)\n- #\n- #if len(op.opers) == 1:\n- #self.setOperValue(op, 0, val)\n- #else:\n- #self.setOperValue(op, 1, val)\n-\ndef i_mrs(self, op):\nval = self.getAPSR()\nself.setOperValue(op, 0, val)\n@@ -966,18 +956,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_vldr = i_mov\n- ''' this one is not favored\n- def i_it(self, op):\n- if self.itcount:\n- raise Exception(\"IT block within an IT block!\")\n-\n- oper = op.opers[0]\n- self.itva = op.va\n- self.itcount = oper.getCondInstrCount()\n- self.itflags = oper.getFlags()\n- print \"IT flags need to be set such that each bit means YES or NO\"\n- '''\n-\n# TESTME: IT functionality\ndef i_it(self, op):\nif self.itcount:\n@@ -987,7 +965,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncondcheck = conditionals[self.ittype]\nself.itva = op.va\n-\ni_ite = i_it\ni_itt = i_it\ni_itee = i_it\n@@ -1009,12 +986,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nmask = e_bits.b_masks[width]\naddit = self.getOperValue(op, 1) & mask\n- #print \"bfi: \", lsb, width, bin(mask), bin(addit)\nmask <<= lsb\nval = self.getOperValue(op, 0) & ~mask\nval |= (addit<<lsb)\n- #print \"bfi: 2 \", bin(mask), bin(val)\nself.setOperValue(op, 0, val)\n@@ -1023,12 +998,9 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nwidth = self.getOperValue(op, 2)\nmask = e_bits.b_masks[width] << lsb\nmask ^= 0xffffffff\n- #print \"0x%x: %r %r: \" % (op.va, self.readMemory(op.va, 4).encode('hex'), op), lsb, width, bin(mask)\nval = self.getOperValue(op, 0)\n- #print \"bfc: 1.5: \", bin(val)\nval &= mask\n- #print \"bfc: 2 \", bin(mask), bin(val)\nself.setOperValue(op, 0, val)\n@@ -1153,7 +1125,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_svc(self, op):\nsvc = self.getOperValue(op, 0)\n- print(\"Service 0x%x called at 0x%x\" % (svc, op.va))\n+ logger.warn(\"Service 0x%x called at 0x%x\", svc, op.va)\ndef i_tst(self, op):\nsrc1 = self.getOperValue(op, 0)\n@@ -1179,7 +1151,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif isinstance(oper, ArmRegShiftImmOper):\nif oper.shimm == 0:\nreturn\n- print('FIXME: TEQ - do different shift types for Carry flag')\n+ logger.critical('FIXME: TEQ - do different shift types for Carry flag')\n# FIXME: make the operands handle a ThumbExpandImm_C (for immediate) or Shift_C (for RegShiftImm), etc...\nself.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, dsize))\n@@ -1632,38 +1604,37 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nbase = emu.getRegister(basereg)\nelse:\nbase = op.opers[0].va\n- print \"base = \", hex(base)\n+ logger.debug(\"TB base = 0%x\", base)\n#base = op.opers[0].getOperValue(op, emu)\n- print(\"base: 0x%x\" % base)\n+ logger.debug(\"base: 0x%x\" % base)\nval0 = emu.readMemValue(base, tsize)\nif val0 > 0x200 + base:\n- print \"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\"\n+ logger.warn(\"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\")\nva = base\nwhile va < base + val0:\nnexttgt = emu.readMemValue(va, tsize) * 2\n- print \"0x%x: -> 0x%x\" % (va, nexttgt + base)\n+ logger.debug(\"0x%x: -> 0x%x\", va, nexttgt + base)\nif nexttgt == 0:\n- print \"Terminating TB at 0-offset\"\n+ logger.warn(\"Terminating TB at 0-offset\")\nbreak\nif nexttgt > 0x500:\n- print \"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nexttgt\n+ logger.warn(\"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\", nexttgt)\nbreak\nloc = emu.vw.getLocation(va)\nif loc != None:\n- print \"Terminating TB at Location/Reference\"\n- print \"%x, %d, %x, %r\" % loc\n+ logger.warn(\"Terminating TB at Location/Reference\")\n+ logger.warn(\"%x, %d, %x, %r\", loc)\nbreak\ntbl.append(nexttgt)\nva += tsize\n- #sys.stderr.write('.')\n- print \"%s: \\n\\t\"%op.mnem + '\\n\\t'.join([hex(x+base) for x in tbl])\n+ logger.debug(\"%s: \\n\\t\"%op.mnem + '\\n\\t'.join([hex(x+base) for x in tbl]))\n###\n# for workspace emulation analysis, let's check the index register for sanity.\n@@ -1675,7 +1646,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\njmptblbase = op.opers[0]._getOperBase(emu)\njmptblval = emu.getOperAddr(op, 0)\njmptbltgt = (emu.getOperValue(op, 0) * 2) + base\n- print \"0x%x: 0x%r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\" % (op.va, op, jmptblbase, jmptblval, jmptbltgt)\n+ logger.debug(\"0x%x: 0x%r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\", op.va, op, jmptblbase, jmptblval, jmptbltgt)\n#raw_input(\"PRESS ENTER TO CONTINUE\")\nreturn jmptbltgt\n@@ -1693,15 +1664,15 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_umull(self, op):\n- print(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ logger.warn(\"FIXME: 0x%x: %s - in emu\", op.va, op)\ndef i_umlal(self, op):\n- print(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ logger.warn(\"FIXME: 0x%x: %s - in emu\", op.va, op)\ndef i_smull(self, op):\n- print(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ logger.warn(\"FIXME: 0x%x: %s - in emu\", op.va, op)\ndef i_umull(self, op):\n- print(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ logger.warn(\"FIXME: 0x%x: %s - in emu\", op.va, op)\ndef i_umull(self, op):\n- print(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ logger.warn(\"FIXME: 0x%x: %s - in emu\", op.va, op)\ndef i_mla(self, op):\nsrc1 = self.getOperValue(op, 1)\n@@ -1722,10 +1693,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_cps(self, op):\n- print(\"CPS: 0x%x %r\" % (op.va, op))\n+ logger.warn(\"CPS: 0x%x %r\" % (op.va, op))\ndef i_pld2(self, op):\n- print(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ logger.warn(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\ndef _getCoProc(self, cpnum):\nif cpnum > 15:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup (largely of print statements), and bugfix/better parsing/handling of UNDEFINED instructions.
|
718,770 |
15.01.2019 00:33:41
| 18,000 |
a091ba6c63c85c10aeb47cb2a873333aa467a972
|
bugfix: thumb T1 shifter decoding, if imm5==0: it's 0x20
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -537,6 +537,9 @@ def imm5_rm_rd(va, value):\nstype = value >> 11\n+ if imm5 == 0:\n+ imm5 = 0x20\n+\noper0 = ArmRegOper(rd, va)\noper1 = ArmRegOper(rm, va)\noper2 = ArmImmOper(imm5)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: thumb T1 shifter decoding, if imm5==0: it's 0x20
|
718,770 |
16.01.2019 12:49:14
| 18,000 |
fe1bd390bbd37192879ab5aafca545bd65f5e0ee
|
thumb arch default calling conventions.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/blob.py",
"new_path": "vivisect/parsers/blob.py",
"diff": "@@ -8,6 +8,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef parseFd(vw, fd, filename=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/ihex.py",
"new_path": "vivisect/parsers/ihex.py",
"diff": "@@ -9,6 +9,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef parseFile(vw, filename):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/macho.py",
"new_path": "vivisect/parsers/macho.py",
"diff": "@@ -15,6 +15,8 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\ndef _loadMacho(vw, filebytes, filename=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -54,6 +54,8 @@ defcalls = {\n'i386':'cdecl',\n'amd64':'msx64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n+ 'thumb16':'armcall',\n}\n# map PE relocation types to vivisect types where possible\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
thumb arch default calling conventions.
|
718,770 |
16.01.2019 12:53:38
| 18,000 |
8db9440254e6ce7309b873c98222b88cc649f0d8
|
backout merge clutter.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -84,24 +84,20 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n- 'thumb':'armcall',\n- 'thumb16':'armcall',\n}\n-def loadElfIntoWorkspace(vw, elf, filename=None, arch=None, platform=None, filefmt='elf'):\n+def loadElfIntoWorkspace(vw, elf, filename=None):\n- if arch == None:\narch = arch_names.get(elf.e_machine)\nif arch == None:\nraise Exception(\"Unsupported Architecture: %d\\n\", elf.e_machine)\n- if platform == None:\nplatform = elf.getPlatform()\n# setup needed platform/format\nvw.setMeta('Architecture', arch)\nvw.setMeta('Platform', platform)\n- vw.setMeta('Format', filefmt)\n+ vw.setMeta('Format', 'elf')\nvw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/ihex.py",
"new_path": "vivisect/parsers/ihex.py",
"diff": "@@ -9,8 +9,6 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n- 'thumb':'armcall',\n- 'thumb16':'armcall',\n}\ndef parseFile(vw, filename):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/macho.py",
"new_path": "vivisect/parsers/macho.py",
"diff": "@@ -15,8 +15,6 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n- 'thumb':'armcall',\n- 'thumb16':'armcall',\n}\ndef _loadMacho(vw, filebytes, filename=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -54,8 +54,6 @@ defcalls = {\n'i386':'cdecl',\n'amd64':'msx64call',\n'arm':'armcall',\n- 'thumb':'armcall',\n- 'thumb16':'armcall',\n}\n# map PE relocation types to vivisect types where possible\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
backout merge clutter.
|
718,770 |
19.01.2019 23:16:10
| 18,000 |
6242deb36ade0ba6612719b829bf9ce32236ef4f
|
expell the evil.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "import os\nimport struct\n+import logging\nimport Elf\nimport vivisect\n@@ -9,6 +10,8 @@ from vivisect.const import *\nfrom cStringIO import StringIO\n+logger = logging.getLogger(__name__)\n+\ndef parseFile(vw, filename):\nfd = file(filename, 'rb')\nelf = Elf.Elf(fd)\n@@ -385,7 +388,7 @@ def demangle(name):\ntry:\nimport cxxfilt\nname = cxxfilt.demangle(name)\n- except:\n- pass\n+ except Exception, e:\n+ logger.debug('failed to demangle name (%r): %r', name, e)\nreturn name\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
expell the evil.
|
718,770 |
19.01.2019 23:18:10
| 18,000 |
f8018a84b69160a78d1f2a378e083546f8ec83cb
|
vprint please.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -651,7 +651,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nexcept Exception, e:\nif self.verbose:\ntraceback.print_exc()\n- self.verbprint(\"Extended Analysis Exception %s: %s\" % (mod.__name__,e))\n+ self.vprint(\"Extended Analysis Exception %s: %s\" % (mod.__name__,e))\nendtime = time.time()\nif self.verbose:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
vprint please.
|
718,770 |
20.01.2019 00:00:44
| 18,000 |
f4a676e10ea2154a87778c9dc2c0e9f0ffc63e15
|
update README.md
i'd gladly add this to setup.py, but i don't seem to have one.
|
[
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -110,6 +110,18 @@ pip install enum34\nThe rest of the build/install steps are the same, save for changing out the version numbers from PyQt4 to PyQt5.\n+### Dependencies:\n+To enable proper networking:\n+\n+```\n+pip install msgpack\n+```\n+\n+To enable Posix C++ demangling:\n+\n+```\n+pip install cxxfilter\n+```\n## Build Status\n[](https://travis-ci.org/vivisect/vivisect)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
update README.md
i'd gladly add this to setup.py, but i don't seem to have one.
|
718,770 |
20.01.2019 00:10:33
| 18,000 |
680f035557220f52216b501baec2267d84c0306c
|
bugfix: imod&1 / IE/ID
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1721,8 +1721,8 @@ def p_uncond(opval, va, psize = 4):\nArmCPSFlagsOper(aif) # if mode is set...\n]\n- # interrupt enable/disable (imod & 1)\n- iflags |= (IF_IE, IF_ID, IF_IE, IF_ID)\n+ # interrupt enable/disable (imod & 1 == Disable)\n+ iflags |= (IF_IE, IF_ID,)[imod&1]\nelse:\nolist = []\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: imod&1 / IE/ID
|
718,770 |
22.01.2019 10:46:30
| 18,000 |
f194fd21d7f65a437f416e91e4eca8b75c06b5fd
|
cleanup unused IFS_* (warning, all indexes get moved up two numbers, if that matters). also, initial implementation of Exclusive LDR/STR in emu.py. may need some changes in the future.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -99,8 +99,6 @@ IFS_SYS_MODE = 1<<8 # instruction is encoded to be executed in SYSTEM mode,\nIFS = [\nNone,\n- '.f32',\n- '.f64',\n'.f32.s32',\n'.f64.s32',\n'.f32.u32',\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -5,6 +5,7 @@ The initial arm module.\nimport sys\nimport struct\nimport logging\n+import threading\nimport envi\nimport envi.bits as e_bits\n@@ -144,6 +145,9 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.itflags = None\nself.itcount = None\n+ # for memory exclusive access:\n+ self.mem_access_lock = threading.Lock()\n+\n# FIXME: this should be None's, and added in for each real coproc... but this will work for now.\nself.coprocs = [CoProcEmulator(x) for x in xrange(16)]\nself.int_handlers = [self.default_int_handler for x in range(100)]\n@@ -901,6 +905,20 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_ldrsb = i_ldr\ni_ldrt = i_ldr\n+ def i_ldrex(self, op):\n+ try:\n+ self.mem_access_lock.acquire()\n+ return self.i_ldr(op)\n+ finally:\n+ self.mem_access_lock.release()\n+\n+ def i_strex(self, op):\n+ try:\n+ self.mem_access_lock.acquire()\n+ return self.i_str(op)\n+ finally:\n+ self.mem_access_lock.release()\n+\ndef i_mov(self, op):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup unused IFS_* (warning, all indexes get moved up two numbers, if that matters). also, initial implementation of Exclusive LDR/STR in emu.py. may need some changes in the future.
|
718,770 |
22.01.2019 13:48:03
| 18,000 |
c007695ba94d148a0bc6a25a3874fec7aa590c7f
|
extending the logging phenom
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -56,7 +56,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\n# parse out an opcode\ntmode = self.getFlag(PSR_T_bit)\n- #print(\"tmode: %x\" % tmode)\n+ #logger.debug(\"tmode: %x\", tmode)\nop = self.parseOpcode(starteip | tmode)\nif self.emumon:\nself.emumon.prehook(self, op, starteip)\n@@ -77,13 +77,13 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif tmode != None:\n# we're forcing thumb or arm mode... update the flag\nself.setFlag(PSR_T_bit, tmode)\n- if verbose: print(\"funcva thumb==%d (forced): 0x%x\" % (tmode, funcva))\n+ logger.debug(\"funcva thumb==%d (forced): 0x%x\", (tmode, funcva))\nelif funcva & 3:\n# if the va isn't 4-byte aligned, it's gotta be thumb\nself.setFlag(PSR_T_bit, 1)\nfuncva &= -2\n- if verbose: print(\"funcva is THUMB(addr): 0x%x\" % funcva)\n+ logger.debug(\"funcva is THUMB(addr): 0x%x\", funcva)\nelse:\nloc = self.vw.getLocation(funcva)\n@@ -92,8 +92,8 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nlva, lsz, lt, lti = loc\nif (lti & envi.ARCH_MASK) == envi.ARCH_THUMB:\nself.setFlag(PSR_T_bit, 1)\n- if verbose: print(\"funcva is THUMB(loc): 0x%x\" % funcva)\n- elif verbose: print(\"funcva is ARM(loc): 0x%x\" % funcva)\n+ logger.debug(\"funcva is THUMB(loc): 0x%x\", funcva)\n+ ellogger.debug(\"funcva is ARM(loc): 0x%x\", funcva)\nelse:\n# otherwise, let's use some heuristics to guess.\n@@ -131,9 +131,9 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nelif armthumb < 0:\nself.setFlag(PSR_T_bit, 1)\n- if verbose: print(\"ArmWorkspaceEmulator: Heuristically Determined funcva is THUMB: 0x%x\" % funcva)\n+ logger.debug(\"ArmWorkspaceEmulator: Heuristically Determined funcva is THUMB: 0x%x\", funcva)\nelse:\n- if verbose: print(\"ArmWorkspaceEmulator: Heuristically Determined funcva is ARM: 0x%x\" % funcva)\n+ logger.debug(\"ArmWorkspaceEmulator: Heuristically Determined funcva is ARM: 0x%x\", funcva)\nself.funcva = funcva\n@@ -145,7 +145,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nwill emulate, but only inside the given function. You may specify a stopva\nto return once that location is hit.\n\"\"\"\n- logger.debug('%s === emu.runFunction(0x%x, stopva=%r, maxhit=%r, maxloop=%r, tmode=%r)' % (__name__, funcva, stopva, maxhit, maxloop, tmode))\n+ logger.debug('%s === emu.runFunction(0x%x, stopva=%r, maxhit=%r, maxloop=%r, tmode=%r)', __name__, funcva, stopva, maxhit, maxloop, tmode)\nself._prep(funcva, tmode)\n# Let the current (should be base also) path know where we are starting\n@@ -252,17 +252,17 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nexcept envi.UnsupportedInstruction, e:\nif self.strictops:\n- if verbose: print('runFunction breaking after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\n+ logger.debug('runFunction breaking after unsupported instruction: 0x%08x %s', e.op.va, e.op.mnem)\nraise e\nelse:\n- if verbose: print('runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\n+ logger.debug('runFunction continuing after unsupported instruction: 0x%08x %s', e.op.va, e.op.mnem)\nself.setProgramCounter(e.op.va+ e.op.size)\nexcept Exception, e:\n#traceback.print_exc()\nif self.emumon != None:\nself.emumon.logAnomaly(self, starteip, str(e))\n- if verbose: print('runFunction breaking after exception (fva: 0x%x): %s' % (funcva, e))\n+ logger.debug('runFunction breaking after exception (fva: 0x%x): %s', funcva, e)\nif verbose: sys.excepthook(*sys.exc_info())\nbreak # If we exc during execution, this branch is dead.\n#except:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
extending the logging phenom
|
718,770 |
22.01.2019 18:16:27
| 18,000 |
84d057a2eced969bb898e733ce3b64cfca05dc42
|
renaming thumb function names: take 2.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -35,6 +35,7 @@ def addAnalysisModules(vw):\nelif arch in ('arm', 'thumb', 'thumb16'):\nvw.addImpApi('windows','arm')\n+ vw.addFuncAnalysisModule('vivisect.analysis.arm.naming')\nvw.addConstModule('vstruct.constants.ntstatus')\n@@ -85,6 +86,7 @@ def addAnalysisModules(vw):\nvw.addVaSet('thunk_reg', ( ('fva', vivisect.VASET_ADDRESS), ('reg', vivisect.VASET_INTEGER), ))\nvw.addFuncAnalysisModule('vivisect.analysis.arm.thunk_reg')\nvw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\n+ vw.addFuncAnalysisModule('vivisect.analysis.arm.naming')\nvw.addAnalysisModule(\"vivisect.analysis.generic.funcentries\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.relocations\")\n@@ -132,6 +134,7 @@ def addAnalysisModules(vw):\nelif arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n+ vw.addFuncAnalysisModule('vivisect.analysis.arm.naming')\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.pointers\")\n@@ -147,6 +150,7 @@ def addAnalysisModules(vw):\nif arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n+ vw.addFuncAnalysisModule('vivisect.analysis.arm.naming')\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.impapi\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n@@ -160,6 +164,7 @@ def addAnalysisModules(vw):\nif arch in ('arm', 'thumb', 'thumb16'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n+ vw.addFuncAnalysisModule('vivisect.analysis.arm.naming')\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.impapi\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/renaming.py",
"new_path": "vivisect/analysis/arm/renaming.py",
"diff": "import envi\nimport vivisect\n-def analyze(vw):\n- for nva, name in vw.getNames():\n- if nva & 1 == 0: continue\n-\n- mmap = vw.getMemoryMap(nva)\n- if mmap == None: continue\n- mva, msz, mperms, mname = mmap\n-\n- loctup = vw.getLocation(nva)\n- if loctup == None:\n- print \"DEBUG: name where loctup == None: %x: %s\" % (nva, name)\n+#def analyze(vw):\n+# for nva, name in vw.getNames():\n+# if nva & 1 == 0: continue\n+#\n+# mmap = vw.getMemoryMap(nva)\n+# if mmap == None: continue\n+# mva, msz, mperms, mname = mmap\n+#\n+# loctup = vw.getLocation(nva)\n+# if loctup == None:\n+# print \"DEBUG: name where loctup == None: %x: %s\" % (nva, name)\n+#\n+# lva, lsz, ltype, ltinfo = loctup\n+# if ltype != vivisect.LOC_OP: continue\n+#\n+# vw.makeName(nva, None)\n+# vw.makeName(lva, name + \"_thumb\")\n- lva, lsz, ltype, ltinfo = loctup\n- if ltype != vivisect.LOC_OP: continue\n-\n- vw.makeName(nva, None)\n- vw.makeName(lva, name + \"_thumb\")\n+def analyze(vw):\n+ for fva in vw.getFunctions():\n+ analyzeFunction(vw, fva)\n+def analyzeFunction(vw, fva):\n+ fakename = vw.getName(fva+1)\n+ if fakename != None:\n+ vw.makeName(fva+1, None)\n+ vw.makeName(fva, fakename)\n#if globals().get('argv') != None:\nif globals().get('vw') != None:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
renaming thumb function names: take 2.
|
718,770 |
22.01.2019 18:17:36
| 18,000 |
30f7aa6bfd2d3047061864e5a2a925751354685d
|
fix: missing BLX encoding space in thumb mode! (specifically in the '1111*' bit space, where data processing instructions don't live.)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -2122,18 +2122,22 @@ thumb2_extension = [\n('11111110', (IENC_COPROC_SIMD,'coproc simd', coproc_simd_32, IF_THUMB32)),\n('11111111', (IENC_ADVSIMD,'adv simd', adv_simd_32, IF_THUMB32)),\n- # data-processing (modified immediate)\n+ # data-processing (modified immediate) (branches mostly redirected from dp_mod_imm_32)\n('11110000000', (INS_AND, 'and', dp_mod_imm_32, IF_THUMB32)), # tst if rd=1111 and s=1\n('11110000001', (INS_BIC, 'bic', dp_mod_imm_32, IF_THUMB32)),\n('11110000010', (INS_ORR, 'orr', dp_mod_imm_32, IF_THUMB32)),\n('11110000011', (INS_ORN, 'orn', dp_mod_imm_32, IF_THUMB32)), # mvn if rn=1111\n- ('11110000110', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('11110000100', (INS_EOR, 'eor', dp_mod_imm_32, IF_THUMB32)), # teq if rd=1111 and s=1\n+ ('11110000110', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('11110001000', (INS_ADD, 'add', dp_mod_imm_32, IF_THUMB32)), # cmn if rd=1111 and s=1\n+ ('11110001001', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('11110001010', (INS_ADC, 'adc', dp_mod_imm_32, IF_THUMB32)),\n('11110001011', (INS_SBC, 'sbc', dp_mod_imm_32, IF_THUMB32)),\n+ ('11110001100', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('11110001101', (INS_SUB, 'sub', dp_mod_imm_32, IF_THUMB32)), # cmp if rd=1111 and s=1\n('11110001110', (INS_RSB, 'rsb', dp_mod_imm_32, IF_THUMB32)),\n+ ('11110001111', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n+ ('1111001', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('11110100000', (INS_AND, 'and', dp_mod_imm_32, IF_THUMB32)), # tst if rd=1111 and s=1\n('11110100001', (INS_BIC, 'bic', dp_mod_imm_32, IF_THUMB32)),\n('11110100010', (INS_ORR, 'orr', dp_mod_imm_32, IF_THUMB32)),\n@@ -2158,6 +2162,7 @@ thumb2_extension = [\n('111100111010', (INS_USAT, 'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n('111100111011', (INS_USAT, 'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n('1111001111', (INS_UBFX, 'ubfx', ubfx_32, IF_THUMB32)),\n+ ('1111010', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('1111011000', (INS_ADD, 'add', dp_bin_imm_32, IF_THUMB32)), # adr if rn=1111\n('1111011001', (INS_MOVW, 'movw', dp_bin_imm_32, IF_THUMB32)),\n('1111011010', (INS_SUB, 'sub', dp_bin_imm_32, IF_THUMB32)), # adr if rn=1111\n@@ -2178,16 +2183,24 @@ thumb2_extension = [\n('111110000011', (INS_LDR, 'ldr', ldr_puw_32, IF_H | IF_THUMB32)),\n('111110000100', (INS_STR, 'str', ldr_puw_32, IF_THUMB32)), # T4 encoding\n('111110000101', (INS_LDR, 'ldr', ldr_puw_32, IF_THUMB32)), # T4 encoding\n- #('111110001001', (INS_LDRB, 'ldrb', ldr_32, IF_THUMB32)),\n+ ('11111000011', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n+ ('111110001000', (INS_STR, 'str', ldr_32, IF_B | IF_THUMB32)),\n('111110001001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n('111110001010', (INS_STR, 'str', ldr_32, IF_H | IF_THUMB32)),\n('111110001011', (INS_LDR, 'ldr', ldr_32, IF_H | IF_THUMB32)),\n('111110001100', (INS_STR, 'str', ldr_32, IF_THUMB32)),\n('111110001101', (INS_LDR, 'ldr', ldr_32, IF_THUMB32)), # T3\n- ('111110001000', (INS_STR, 'str', ldr_32, IF_B | IF_THUMB32)),\n+ ('111110001110', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n+ ('111110001111', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n+ ('111110010000', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('111110010001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n+ ('11111001001', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n+ ('1111100101', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n+ ('111110011000', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('111110011001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n+ ('111110011010', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('111110011011', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n+ ('1111100111', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n# data-processing (register)\n('111110100', (None, 'shift_or_extend', shift_or_ext_32, IF_THUMB32)),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fix: missing BLX encoding space in thumb mode! (specifically in the '1111*' bit space, where data processing instructions don't live.)
|
718,770 |
23.01.2019 00:25:42
| 18,000 |
fbe85f037bc556430a6bca743590838609be55c5
|
revamping branch_misc() parser in thumb disasm.py
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -273,8 +273,8 @@ def branch_misc(va, val, val2): # bl and misc control\nmesg=\"branch_misc subsection 2\",\nbytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va-4)\n- else:\nif imm8 == 0 and op == 0b0111101:\n+ # original imm8 was imm4!\nimm8 = val2 & 0xff\nif imm8:\nopers = (\n@@ -285,25 +285,21 @@ def branch_misc(va, val, val2): # bl and misc control\nreturn COND_AL, None, 'sub', opers, IF_PSR_S, 0\nreturn COND_AL, None, 'eret', tuple(), envi.IF_RET | envi.IF_NOFALL, 0\n- print(\"TEST ME: branch_misc subsection 3\")\n-##### FIXME! THIS NEEDS TO ALSO HIT MSR BELOW....\n- #raise InvalidInstruction(\n- # mesg=\"branch_misc subsection 3\",\n- # bytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va-4)\n# xx0xxxxx and others\n- if op == 0b0111000:\n+ if op & 0b1111110 == 0b0111000:\ntmp = op2 & 3\nRn = val & 0xf\nmask = (val2>>8) & 0xf\n- if tmp == 0:\n+ if not (op & 1) and tmp == 0:\n+ # MSR(register) p A8-498\nR = PSR_APSR\n- #raise Exception(\"FIXME: MSR(register) p A8-498\")\n- else:\n+ else: # op==0111000 and op2==01/10/11 or op==0111001\n+ # MSR(register) p B9-1968\nR = (val >> 4) & 1\n- #raise Exception(\"FIXME: MSR(register) p B9-1968\")\n+ # System Level Only...\nopers = (\nArmPgmStatRegOper(R, mask),\n@@ -311,12 +307,6 @@ def branch_misc(va, val, val2): # bl and misc control\n)\nreturn COND_AL, None, 'msr', opers, None, 0\n-\n- elif op == 0b0111001:\n- # coalesce with previous\n- raise Exception(\"FIXME: MSR(register) p B9-1968\")\n-\n-\nelif op == 0b0111010:\nflags = 0\n@@ -359,26 +349,26 @@ def branch_misc(va, val, val2): # bl and misc control\nreturn COND_AL, opcode, mnem, opers, flags, 0\n- elif op == 0b0111011:\n- raise Exception(\"FIXME: Misc control instrs p A6-235\")\n+ #elif op == 0b0111011:\n+ # raise Exception(\"FIXME: Misc control instrs p A6-235\") should be covered by \"op & 0b111 == 0b011\"\nelif op == 0b0111100:\nraise Exception(\"FIXME: BXJ p A8-352\")\n- elif op == 0b0111101: # subs PC, LR, #imm (see special case ERET above)\n- imm8 = val2 & 0xff\n- opers = (\n- ArmRegOper(REG_PC),\n- ArmRegOper(REG_LR),\n- ArmImmOper(imm8),\n- )\n- return COND_AL, None, 'sub', opers, IF_PSR_S, 0\n+ #elif op == 0b0111101: # subs PC, LR, #imm (see special case ERET above)... unnecessary?\n+ # imm8 = val2 & 0xff\n+ # opers = (\n+ # ArmRegOper(REG_PC),\n+ # ArmRegOper(REG_LR),\n+ # ArmImmOper(imm8),\n+ # )\n+ # return COND_AL, None, 'sub', opers, IF_PSR_S, 0\nelif op == 0b0111110:\nRd = (val2 >> 8) & 0xf\nopers = (\nArmRegOper(Rd),\n- ArmRegOper(REG_OFFSET_CPSR),\n+ ArmPgmStatRegOper(PSR_CPSR),\n)\nreturn COND_AL, None, 'mrs', opers, None, 0\n@@ -387,10 +377,9 @@ def branch_misc(va, val, val2): # bl and misc control\nR = (val >> 4) & 1\nopers = (\nArmRegOper(Rd),\n- ArmRegOper(REG_OFFSET_CPSR),\n+ ArmPgmStatRegOper(R),\n)\n- raise Exception(\"FIXME: MRS(register) p B9-1962 - how is R used?\")\nreturn COND_AL, None, 'mrs', opers, None, 0\nelif op == 0b1111110:\n@@ -415,6 +404,10 @@ def branch_misc(va, val, val2): # bl and misc control\nmesg=\"branch_misc subsection 1\",\nbytez=struct.pack(\"<HH\", val, val2), va=va-4)\n+ raise InvalidInstruction(\n+ mesg=\"branch_misc subsection 3\",\n+ bytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va-4)\n+\nelif op1 & 0b101 == 1: # T4 encoding\n@@ -439,7 +432,13 @@ def branch_misc(va, val, val2): # bl and misc control\nelif op1 == 0b010:\nif op == 0b1111111:\n- raise Exception(\"FIXME: UDF (permanently undefined) p B9-1972\")\n+ flags = 0\n+ imm4 = val & 0xf\n+ imm12 = val2 & 0xfff\n+ immval = (imm4<<12) | imm12\n+ oper0 = ArmImmOper(immval)\n+ return COND_AL, INS_UDF, 'udf', (oper0, ), flags, 0\n+\nraise InvalidInstruction(\nmesg=\"branch_misc subsection 6\",\nbytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va-4)\n@@ -473,9 +472,6 @@ def branch_misc(va, val, val2): # bl and misc control\nreturn COND_AL, opcode, mnem, (oper0, ), flags, 0\n-\n-\n-\nraise InvalidInstruction(\nmesg=\"branch_misc Branches and Miscellaneous Control: Failed to match\",\nbytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va-4)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
revamping branch_misc() parser in thumb disasm.py
|
718,770 |
23.01.2019 11:05:54
| 18,000 |
61694aa7b2d5d42effdfbd84dcfea4fc3e50aa05
|
bugfix: logger.debug
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -77,7 +77,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif tmode != None:\n# we're forcing thumb or arm mode... update the flag\nself.setFlag(PSR_T_bit, tmode)\n- logger.debug(\"funcva thumb==%d (forced): 0x%x\", (tmode, funcva))\n+ logger.debug(\"funcva thumb==%d (forced): 0x%x\", tmode, funcva)\nelif funcva & 3:\n# if the va isn't 4-byte aligned, it's gotta be thumb\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: logger.debug
|
718,770 |
23.01.2019 11:12:45
| 18,000 |
c90211746ac1a6398f704a2725614ac220b074b5
|
more logger refinement
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -174,9 +174,9 @@ def analyzeFunction(vw, fva):\ncmt = \"0x%x: %s ;\\n %s\" % (tgt, reprPointer(vw, tgt), curcmt)\nvw.setComment(va, cmt)\n- logger.debug(\"PIE XREF: %x %s\" % (va, cmt))\n+ logger.debug(\"PIE XREF: %x %s\", va, cmt)\n- logger.debug(\"ANOMS: \\n\", repr(emumon.emuanom))\n+ logger.debug(\"ANOMS: \\n%r\", emumon.emuanom)\ndef analyze(vw):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -146,7 +146,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nwill emulate, but only inside the given function. You may specify a stopva\nto return once that location is hit.\n\"\"\"\n- logger.debug('%s === emu.runFunction(0x%x, stopva=%r, maxhit=%r, maxloop=%r, tmode=%r)', __name__, funcva, stopva, maxhit, maxloop, tmode)\n+ logger.debug('=== emu.runFunction(0x%x, stopva=%r, maxhit=%r, maxloop=%r, tmode=%r)', funcva, stopva, maxhit, maxloop, tmode)\nself._prep(funcva, tmode)\n# Let the current (should be base also) path know where we are starting\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
more logger refinement
|
718,770 |
24.01.2019 12:18:41
| 18,000 |
dcd49b5ecee5d75cea9c42d33cc5ce2c8c0a7d48
|
moving "makeuniq" into makeName() instead of addExport.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -750,18 +750,8 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif curval != None and curval != va:\n# if we don't force it to make a uniq name, bail\n- if not makeuniq:\nraise Exception(\"Duplicate Name: %s => 0x%x (cur: 0x%x)\" % (rname, va, curval))\n- # otherwise, tack a number on the end\n- index = 0\n- newname = \"%s.%d\" % (rname, index)\n- while self.vaByName(newname) != None:\n- index += 1\n- newname = \"%s.%d\" % (rname, index)\n-\n- name = \"%s.%d\" % (name, index)\n-\nself._fireEvent(VWE_ADDEXPORT, (va,etype,name,filename))\ndef getExport(self, va):\n@@ -2046,7 +2036,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nname = \"%s%s%s\" % (basename, pom, hex(delta))\nreturn name\n- def makeName(self, va, name, filelocal=False):\n+ def makeName(self, va, name, filelocal=False, makeuniq=False):\n\"\"\"\nSet a readable name for the given location by va. There\n*must* be a Location defined for the VA before you may name\n@@ -2067,8 +2057,19 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nreturn\nif oldva != None:\n+ if not makeuniq:\nraise DuplicateName(oldva, va, name)\n+ else:\n+ # tack a number on the end\n+ index = 0\n+ newname = \"%s_%d\" % (name, index)\n+ while self.vaByName(newname) not in (None, newname):\n+ index += 1\n+ newname = \"%s_%d\" % (name, index)\n+\n+ name = newname\n+\nself._fireEvent(VWE_SETNAME, (va,name))\ndef saveWorkspace(self, fullsave=True):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "import Queue\n+import logging\nimport traceback\nimport threading\nimport collections\n@@ -22,6 +23,8 @@ from envi.threads import firethread\nfrom vivisect.exc import *\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n\"\"\"\nMostly this is a place to scuttle away some of the inner workings\nof a workspace, so the outer facing API is a little cleaner.\n@@ -320,9 +323,11 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nif name == None:\noldname = self.name_by_va.pop(va, None)\nself.va_by_name.pop(oldname, None)\n+\nelse:\ncurname = self.name_by_va.get(va)\nif curname != None:\n+ logger.debug( 'replacing 0x%x: %r -> %r', va, curname, name)\nself.va_by_name.pop(curname)\nself.va_by_name[name] = va\n@@ -349,7 +354,7 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nself.exports.append(einfo)\nself.exports_by_va[va] = einfo\nfullname = \"%s.%s\" % (filename,name)\n- self.makeName(va, fullname)\n+ self.makeName(va, fullname, makeuniq=True)\ndef _handleSETMETA(self, einfo):\nname,value = einfo\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -238,12 +238,14 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\ntry:\n# If it has a name, it's an externally\n# resolved \"import\" entry, otherwise, just a regular reloc\n+ name = r.getName()\n+ dmglname = demangle(name)\n+ logger.debug('relocs: 0x%x: %r', rlva, name)\nif arch in ('i386','amd64'):\n-\n- name = demangle(r.getName())\nif name:\nif rtype == Elf.R_386_JMP_SLOT:\nvw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\n# FIXME elf has conflicting names for 2 relocs?\n#elif rtype == Elf.R_386_GLOB_DAT:\n@@ -254,16 +256,24 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nelif rtype == Elf.R_X86_64_GLOB_DAT:\nvw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\nelse:\nvw.verbprint('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\nif arch == 'arm':\n- name = r.getName()\nif name:\nif rtype == Elf.R_ARM_JUMP_SLOT:\n+ vw.makeImport(rlva, \"*\", dmglname)\n+\n+ elif rtype == Elf.R_ARM_ABS32: # Direct 32 bit */\nvw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\n+\n+ elif rtype == Elf.R_ARM_GLOB_DAT: # Create GOT entry */\n+ vw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\nelse:\nvw.verbprint('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n@@ -281,19 +291,20 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif sva == 0:\ncontinue\n- demangledname = demangle(s.name)\n+ dmglname = demangle(s.name)\n+ logger.debug('dynsyms: 0x%x: %r', sva, dmglname)\nif stype == Elf.STT_FUNC or (stype == Elf.STT_GNU_IFUNC and arch in ('i386','amd64')): # HACK: linux is what we're really after.\ntry:\nvw.addEntryPoint(sva)\n- vw.addExport(sva, EXP_FUNCTION, demangledname, fname, makeuniq=True)\n+ vw.addExport(sva, EXP_FUNCTION, s.name, fname)\nexcept Exception, e:\nvw.vprint('addExport Failure: (%s) %s' % (s.name, e))\nelif stype == Elf.STT_OBJECT:\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_DATA, demangledname, fname, makeuniq=True)\n+ vw.addExport(sva, EXP_DATA, s.name, fname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -305,7 +316,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif vw.isValidPointer(sva):\ntry:\nvw.addEntryPoint(sva)\n- vw.addExport(sva, EXP_FUNCTION, demangledname, fname, makeuniq=True)\n+ vw.addExport(sva, EXP_FUNCTION, dmglname, fname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -316,7 +327,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\ntry:\n- vw.addExport(sva, EXP_DATA, demangledname, fname, makeuniq=True)\n+ vw.addExport(sva, EXP_DATA, dmglname, fname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\n@@ -333,9 +344,31 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\npass\n#print \"DYNAMIC DYNAMIC DYNAMIC\",d\n+ vw.addVaSet(\"FileSymbols\", ((\"Name\",VASET_STRING),(\"va\",VASET_ADDRESS)))\n+ vw.addVaSet(\"WeakSymbols\", ((\"Name\",VASET_STRING),(\"va\",VASET_ADDRESS)))\n+ # apply symbols to workspace (if any)\n+ impvas = [va for va,x,y,z in vw.getImports()]\n+ expvas = [va for va,x,y,z in vw.getExports()]\nfor s in elf.getSymbols():\nsva = s.st_value\n+ logger.debug('symbol val: 0x%x\\ttype: %r\\tbind: %r\\t name: %r',\n+ sva,\n+ Elf.st_info_type.get(s.st_info, s.st_info),\n+ Elf.st_info_bind.get(s.st_other, s.st_other),\n+ s.name)\n+\n+ if s.st_info == Elf.STT_FILE:\n+ vw.setVaSetRow('FileSymbols', (s.name, sva))\n+ continue\n+\n+ if s.st_info == Elf.STT_NOTYPE:\n+ logger.info('skipping NOTYPE symbol: 0x%x: %r',sva, s.name)\n+ continue\n+\n+ if sva in impvas or sva in expvas:\n+ logginer.debug('skipping Symbol naming for existing Import/Export: 0x%x (%r)', sva, s.name)\n+ continue\n# if the symbol has a value of 0, it is likely a relocation point which gets updated\nsname = normName(s.name)\n@@ -344,18 +377,26 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nrname = normName(reloc.name)\nif rname == sname:\nsva = reloc.r_offset\n+ logger.info('sva==0, using relocation name: %x: %r', sva, rname)\nbreak\n- origname = sname\n- demangledname = demangle(sname)\n+ dmglname = demangle(sname)\nif addbase: sva += baseaddr\n- if vw.isValidPointer(sva) and len(demangledname):\n+ if vw.isValidPointer(sva) and len(dmglname):\ntry:\n- vw.makeName(sva, demangledname, filelocal=True)\n+ if s.st_other == Elf.STB_WEAK:\n+ logger.info('WEAK symbol: 0x%x: %r', sva, sname)\n+ vw.setVaSetRow('WeakSymbols', (sname, sva))\n+ dmglname = '__weak_' + dmglname\n+\n+ vw.makeName(sva, dmglname, filelocal=True, makeuniq=True)\nexcept Exception, e:\nprint \"WARNING:\",e\n+ if s.st_info == Elf.STT_FUNC:\n+ vw.addEntryPoint(sva)\n+\nif addbase:\neentry = baseaddr + elf.e_entry\nelse:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
moving "makeuniq" into makeName() instead of addExport.
|
718,770 |
23.01.2019 15:46:57
| 18,000 |
2c3c59786416786f5010a738a8754f19063f7b50
|
handle .init_array and .fini_array
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -199,10 +199,38 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nvw.makeName(sva, \"init_function\", filelocal=True)\nvw.addEntryPoint(sva)\n+ elif sname == \".init_array\":\n+ # handle pseudo-fixups first: these pointers require base-addresses\n+ psize = vw.getPointerSize()\n+ secbytes = elf.readAtRva(sec.sh_addr, size)\n+ ptr_count = 0\n+ for off in range(0, size, psize):\n+ addr = struct.unpack_from(fmt, secbytes, off)\n+ if addbase: addr += baseaddr\n+\n+ vw.makeName(addr, \"init_function_%d\" % ptr_count, filelocal=True)\n+ vw.addXref(sec.sh_addr + off, addr, REF_PTR)\n+ vw.addEntryPoint(addr)\n+ ptr_count += 1\n+\nelif sname == \".fini\":\nvw.makeName(sva, \"fini_function\", filelocal=True)\nvw.addEntryPoint(sva)\n+ elif sname == \".fini_array\":\n+ # handle pseudo-fixups first: these pointers require base-addresses\n+ psize = vw.getPointerSize()\n+ secbytes = elf.readAtRva(sec.sh_addr, size)\n+ ptr_count = 0\n+ for off in range(0, size, psize):\n+ addr = struct.unpack_from(fmt, secbytes, off)\n+ if addbase: addr += baseaddr\n+\n+ vw.makeName(addr, \"fini_function_%d\" % ptr_count, filelocal=True)\n+ vw.addXref(sec.sh_addr + off, addr, REF_PTR)\n+ vw.addEntryPoint(addr)\n+ ptr_count += 1\n+\nelif sname == \".dynamic\": # Imports\nmakeDynamicTable(vw, sva, sva+size)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
handle .init_array and .fini_array
|
718,770 |
24.01.2019 20:05:00
| 18,000 |
81846d3035507b8a2d03af125963ec7ec62739c9
|
stash fail. fixing a tuple of problems
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -5,6 +5,7 @@ import logging\nimport Elf\nimport vivisect\nimport vivisect.parsers as v_parsers\n+import envi.bits as e_bits\nfrom vivisect.const import *\n@@ -135,14 +136,14 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nif pgm.p_type == Elf.PT_LOAD:\nif pgm.p_memsz == 0:\ncontinue\n- if vw.verbose: vw.vprint('Loading: %s' % (repr(pgm)))\n+ logger.info('Loading: %s', repr(pgm))\nbytez = elf.readAtOffset(pgm.p_offset, pgm.p_filesz)\nbytez += \"\\x00\" * (pgm.p_memsz - pgm.p_filesz)\npva = pgm.p_vaddr\nif addbase: pva += baseaddr\nvw.addMemoryMap(pva, pgm.p_flags & 0x7, fname, bytez) #FIXME perms\nelse:\n- if vw.verbose: vw.vprint('Skipping: %s' % repr(pgm))\n+ logger.info('Skipping: %s', repr(pgm))\nif len(pgms) == 0:\n# fall back to loading sections as best we can...\n@@ -202,10 +203,11 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nelif sname == \".init_array\":\n# handle pseudo-fixups first: these pointers require base-addresses\npsize = vw.getPointerSize()\n+ pfmt = e_bits.le_fmt_chars[psize] #FIXME: make Endian-aware (needs plumbing through ELF)\nsecbytes = elf.readAtRva(sec.sh_addr, size)\nptr_count = 0\nfor off in range(0, size, psize):\n- addr = struct.unpack_from(fmt, secbytes, off)\n+ addr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\nvw.makeName(addr, \"init_function_%d\" % ptr_count, filelocal=True)\n@@ -220,10 +222,11 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nelif sname == \".fini_array\":\n# handle pseudo-fixups first: these pointers require base-addresses\npsize = vw.getPointerSize()\n+ pfmt = e_bits.le_fmt_chars[psize] #FIXME: make Endian-aware (needs plumbing through ELF)\nsecbytes = elf.readAtRva(sec.sh_addr, size)\nptr_count = 0\nfor off in range(0, size, psize):\n- addr = struct.unpack_from(fmt, secbytes, off)\n+ addr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\nvw.makeName(addr, \"fini_function_%d\" % ptr_count, filelocal=True)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
stash fail. fixing a tuple of problems
|
718,770 |
24.01.2019 20:08:23
| 18,000 |
35fc67ecb9a44e081be212b7918b3b51e80b0281
|
make the init- and fini-array's pointers
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -207,6 +207,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nsecbytes = elf.readAtRva(sec.sh_addr, size)\nptr_count = 0\nfor off in range(0, size, psize):\n+ vw.makePointer(sec.sh_addr + off)\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n@@ -226,6 +227,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nsecbytes = elf.readAtRva(sec.sh_addr, size)\nptr_count = 0\nfor off in range(0, size, psize):\n+ vw.makePointer(sec.sh_addr + off)\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
make the init- and fini-array's pointers
|
718,770 |
24.01.2019 20:20:13
| 18,000 |
ba01a7cbd5fd9f43b4607d527bec7b29f2d9c86d
|
makePointers needs baseaddr-offset to be correct.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -205,14 +205,17 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\npsize = vw.getPointerSize()\npfmt = e_bits.le_fmt_chars[psize] #FIXME: make Endian-aware (needs plumbing through ELF)\nsecbytes = elf.readAtRva(sec.sh_addr, size)\n+ sh_addr = sec.sh_addr\n+ if addbase: sh_addr += baseaddr\n+\nptr_count = 0\nfor off in range(0, size, psize):\n- vw.makePointer(sec.sh_addr + off)\n+ vw.makePointer(sh_addr + off)\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\nvw.makeName(addr, \"init_function_%d\" % ptr_count, filelocal=True)\n- vw.addXref(sec.sh_addr + off, addr, REF_PTR)\n+ vw.addXref(sh_addr + off, addr, REF_PTR)\nvw.addEntryPoint(addr)\nptr_count += 1\n@@ -225,9 +228,12 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\npsize = vw.getPointerSize()\npfmt = e_bits.le_fmt_chars[psize] #FIXME: make Endian-aware (needs plumbing through ELF)\nsecbytes = elf.readAtRva(sec.sh_addr, size)\n+ sh_addr = sec.sh_addr\n+ if addbase: sh_addr += baseaddr\n+\nptr_count = 0\nfor off in range(0, size, psize):\n- vw.makePointer(sec.sh_addr + off)\n+ vw.makePointer(sh_addr + off)\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
makePointers needs baseaddr-offset to be correct.
|
718,770 |
24.01.2019 21:04:01
| 18,000 |
9592825738d048af179ae397c90cddf40f270265
|
improved pointer following for init_array and fini_array
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -210,10 +210,10 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nptr_count = 0\nfor off in range(0, size, psize):\n- vw.makePointer(sh_addr + off)\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n+ vw.makePointer(sh_addr + off, addr)\nvw.makeName(addr, \"init_function_%d\" % ptr_count, filelocal=True)\nvw.addXref(sh_addr + off, addr, REF_PTR)\nvw.addEntryPoint(addr)\n@@ -233,10 +233,10 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\nptr_count = 0\nfor off in range(0, size, psize):\n- vw.makePointer(sh_addr + off)\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n+ vw.makePointer(sh_addr + off, addr)\nvw.makeName(addr, \"fini_function_%d\" % ptr_count, filelocal=True)\nvw.addXref(sec.sh_addr + off, addr, REF_PTR)\nvw.addEntryPoint(addr)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
improved pointer following for init_array and fini_array
|
718,770 |
25.01.2019 07:51:37
| 18,000 |
dc07e983bb121b28835d0bac3b9fbe01c1b24d43
|
cleanup original (now unused) makeuniq arg to addExport
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -739,7 +739,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n\"\"\"\nreturn list(self.exports)\n- def addExport(self, va, etype, name, filename, makeuniq=False):\n+ def addExport(self, va, etype, name, filename):\n\"\"\"\nAdd an already created export object.\n\"\"\"\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup original (now unused) makeuniq arg to addExport
|
718,770 |
30.01.2019 18:27:12
| 18,000 |
8588506e532151c3eb4db3cdf8cd8160e5d27958
|
a few ldr/str tsize bugfixes. need to go through thumb and normalize the b/h/d/s stuff. visi's original thumb16 code doesn't line up with mine.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1138,12 +1138,15 @@ def strex_32(va, val1, val2):\nreturn COND_AL, None, None, opers, flags, 0\ndef ldr_32(va, val1, val2):\n+ bitsbits = (val1>>4) & 0x7\n+ tsize = (1, 0, 2, 2, 4, 4, 0, 0)[bitsbits]\n+\nrn = val1 & 0xf\nrt = (val2 >> 12) & 0xf\nimm12 = val2 & 0xfff\noper0 = ArmRegOper(rt, va=va)\n- oper1 = ArmImmOffsetOper(rn, imm12, va=va)\n+ oper1 = ArmImmOffsetOper(rn, imm12, va=va, tsize=tsize)\nopers = (oper0, oper1)\nreturn COND_AL, None, None, opers, None, 0\n@@ -1183,7 +1186,7 @@ def ldrb_memhints_32(va, val1, val2):\nimm12 = val2 & 0xfff\nopers = (\nArmRegOper(rt),\n- ArmPcOffsetOper(imm12, va),\n+ ArmPcOffsetOper(imm12, va, tsize=1),\n)\nreturn COND_AL, opcode, mnem, opers, flags, 0\n@@ -1228,7 +1231,7 @@ def ldrb_memhints_32(va, val1, val2):\nimm2 = (val2>>4) & 3\nopers = (\nArmRegOper(rt),\n- ArmScaledOffsetOper(rn, rm, S_LSL, imm2, va),\n+ ArmScaledOffsetOper(rn, rm, S_LSL, imm2, va, tsize=1),\n)\nreturn COND_AL, opcode, mnem, opers, flags, 0\n@@ -1243,6 +1246,8 @@ def ldr_shift_32(va, val1, val2):\n#b11 = (val2>>11) & 1\n#if not b11:\n# raise Exception(\"ldr_shift_32 parsing non-ldrb\")\n+ bitsbits = (val1>>4) & 0x7\n+ tsize = (1, 0, 2, 2, 4, 4, 0, 0)[bitsbits]\nrn = val1 & 0xf\nrm = val2 & 0xf\n@@ -1250,7 +1255,7 @@ def ldr_shift_32(va, val1, val2):\nimm2 = (val2 >> 4) & 3\noper0 = ArmRegOper(rt, va=va)\n- oper1 = ArmScaledOffsetOper(rn, rm, S_LSL, imm2, va=va)\n+ oper1 = ArmScaledOffsetOper(rn, rm, S_LSL, imm2, va=va, tsize=tsize)\nopers = (oper0, oper1)\nreturn COND_AL, None, None, opers, None, 0\n@@ -1261,7 +1266,7 @@ def ldrex_32(va, val1, val2):\nimm8 = val2 & 0xff\noper0 = ArmRegOper(rt, va=va)\n- oper1 = ArmImmOffsetOper(rn, imm8<<2, va=va)\n+ oper1 = ArmImmOffsetOper(rn, imm8<<2, va=va, tsize=4)\nopers = (oper0, oper1)\nflags = 0\n@@ -1402,11 +1407,13 @@ def tb_ldrex_32(va, val1, val2):\nif op3 & 4: # ldrex#\nmnem = 'ldrex'\nopcode = INS_LDREX\n- flags | (IF_B, IF_H, 0, IF_D)[op3&3]\n+ flags |= (IF_B, IF_H, 0, IF_D)[op3&3]\n+ tsize = [1, 2, 0, 8][op3&3]\noper0 = ArmRegOper(rt, va=va)\n- oper1 = ArmRegOper(rn, va=va)\n+ oper1 = ArmRegOffsetOper(rn, va=va, tsize=tsize)\nopers = (oper0, oper1)\n+\nelse: # tbb/tbh\nisH = op3 & 1\nmnem, opcode, tsize = (('tbb', INS_TBB, 1), ('tbh', INS_TBH, 2))[isH]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
a few ldr/str tsize bugfixes. need to go through thumb and normalize the b/h/d/s stuff. visi's original thumb16 code doesn't line up with mine.
|
718,770 |
11.02.2019 15:37:27
| 18,000 |
752e1d946e299109d28b9c366ae2087258a69230
|
tweak to come in line with readMemValue() and use envi.bits.buildbytes()
|
[
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -204,9 +204,8 @@ class IMemory:\n'''\nWrite a number from memory of the given size.\n'''\n- efmt = e_bits.fmt_chars[self.getEndian()]\n- fmt = efmt[size]\n- return self.writeMemoryFormat(addr, fmt, val)\n+ bytez = e_bits.buildbytes(val, size, self.getEndian())\n+ return self.writeMemory(addr, bytez)\ndef writeMemoryPtr(self, va, val):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
tweak to come in line with readMemValue() and use envi.bits.buildbytes()
|
718,770 |
11.02.2019 16:25:57
| 18,000 |
b526d594b2d9a08e2057dca56fa0e8154ef33ac9
|
basic change to allow new files to be easily added to a workspace with a specified baseaddr. no linking is currently done.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -2081,7 +2081,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n- def loadFromFd(self, fd, fmtname=None):\n+ def loadFromFd(self, fd, fmtname=None, baseaddr=None):\n\"\"\"\nRead the first bytes of the file descriptor and see if we can identify the type.\nIf so, load up the parser for that file type, otherwise raise an exception.\n@@ -2100,7 +2100,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nfd.seek(0)\nfilename = hashlib.md5( fd.read() ).hexdigest()\n- fname = mod.parseFd(self, fd, filename)\n+ fname = mod.parseFd(self, fd, filename, baseaddr=baseaddr)\nself.initMeta(\"StorageName\", filename+\".viv\")\n@@ -2146,7 +2146,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nself.vprint('Saving Symbol Cache: %s (%d syms)' % (symhash,len(symtups)))\nsymcache.setCacheSyms( symhash, symtups )\n- def loadFromFile(self, filename, fmtname=None):\n+ def loadFromFile(self, filename, fmtname=None, baseaddr=None):\n\"\"\"\nRead the first bytes of the file and see if we can identify the type.\nIf so, load up the parser for that file type, otherwise raise an exception.\n@@ -2159,7 +2159,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nfmtname = viv_parsers.guessFormatFilename(filename)\nmod = viv_parsers.getParserModule(fmtname)\n- fname = mod.parseFile(self, filename)\n+ fname = mod.parseFile(self, filename, baseaddr=baseaddr)\nself.initMeta(\"StorageName\", filename+\".viv\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "import os\nimport struct\n+import logging\nimport Elf\nimport vivisect\nimport vivisect.parsers as v_parsers\n+import envi.bits as e_bits\nfrom vivisect.const import *\nfrom cStringIO import StringIO\n-def parseFile(vw, filename):\n+logger = logging.getLogger(__name__)\n+\n+def parseFile(vw, filename, baseaddr=None):\nfd = file(filename, 'rb')\nelf = Elf.Elf(fd)\n- return loadElfIntoWorkspace(vw, elf, filename=filename)\n+ return loadElfIntoWorkspace(vw, elf, filename=filename, baseaddr=baseaddr)\n-def parseBytes(vw, bytes):\n+def parseBytes(vw, bytes, baseaddr=None):\nfd = StringIO(bytes)\nelf = Elf.Elf(fd)\n- return loadElfIntoWorkspace(vw, elf)\n+ return loadElfIntoWorkspace(vw, elf, baseaddr=baseaddr)\n-def parseFd(vw, fd, filename=None):\n+def parseFd(vw, fd, filename=None, baseaddr=None):\nfd.seek(0)\nelf = Elf.Elf(fd)\n- return loadElfIntoWorkspace(vw, elf, filename=filename)\n+ return loadElfIntoWorkspace(vw, elf, filename=filename, baseaddr=baseaddr)\ndef parseMemory(vw, memobj, baseaddr):\nraise Exception('FIXME implement parseMemory for elf!')\n@@ -86,7 +90,7 @@ archcalls = {\n'arm':'armcall',\n}\n-def loadElfIntoWorkspace(vw, elf, filename=None):\n+def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\narch = arch_names.get(elf.e_machine)\nif arch == None:\n@@ -108,6 +112,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None):\naddbase = False\nif not elf.isPreLinked() and elf.isSharedObject():\naddbase = True\n+ if baseaddr == None:\nbaseaddr = elf.getBaseAddress()\n#FIXME make filename come from dynamic's if present for shared object\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
basic change to allow new files to be easily added to a workspace with a specified baseaddr. no linking is currently done.
|
718,770 |
11.02.2019 17:06:11
| 18,000 |
2c25dc5f2f58c8f286208f702fa3b26e8e62f048
|
commit fail. need all the parsers committed...
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/blob.py",
"new_path": "vivisect/parsers/blob.py",
"diff": "@@ -10,10 +10,11 @@ archcalls = {\n'arm':'armcall',\n}\n-def parseFd(vw, fd, filename=None):\n+def parseFd(vw, fd, filename=None, baseaddr=None):\nfd.seek(0)\narch = vw.config.viv.parsers.blob.arch\nbigend = vw.config.viv.parsers.blob.bigend\n+ if baseaddr == None:\nbaseaddr = vw.config.viv.parsers.blob.baseaddr\ntry:\nenvi.getArchModule(arch)\n@@ -31,10 +32,11 @@ def parseFd(vw, fd, filename=None):\nvw.addMemoryMap(baseaddr, 7, filename, bytez)\nvw.addSegment( baseaddr, len(bytez), '%.8x' % baseaddr, 'blob' )\n-def parseFile(vw, filename):\n+def parseFile(vw, filename, baseaddr=None):\narch = vw.config.viv.parsers.blob.arch\nbigend = vw.config.viv.parsers.blob.bigend\n+ if baseaddr == None:\nbaseaddr = vw.config.viv.parsers.blob.baseaddr\ntry:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/ihex.py",
"new_path": "vivisect/parsers/ihex.py",
"diff": "@@ -11,7 +11,7 @@ archcalls = {\n'arm':'armcall',\n}\n-def parseFile(vw, filename):\n+def parseFile(vw, filename, baseaddr=None):\narch = vw.config.viv.parsers.ihex.arch\nif not arch:\n@@ -25,6 +25,7 @@ def parseFile(vw, filename):\nvw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\n+ # might we make use of baseaddr, even though it's an IHEX? for now, no.\nfname = vw.addFile(filename, 0, v_parsers.md5File(filename))\nihex = v_ihex.IHexFile()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/macho.py",
"new_path": "vivisect/parsers/macho.py",
"diff": "@@ -4,12 +4,12 @@ import vivisect.parsers as viv_parsers\nimport vstruct.defs.macho as vs_macho\nimport vivisect.analysis.i386 as viv_a_i386\n-def parseFile(vw, filename):\n+def parseFile(vw, filename, baseaddr=None):\nfbytes = file(filename, 'rb').read()\n- return _loadMacho(vw, fbytes, filename=filename)\n+ return _loadMacho(vw, fbytes, filename=filename, baseaddr=baseaddr)\n-def parseBytes(vw, filebytes):\n- return _loadMacho(vw, filebytes)\n+def parseBytes(vw, filebytes, baseaddr=None):\n+ return _loadMacho(vw, filebytes, baseaddr=baseaddr)\narchcalls = {\n'i386':'cdecl',\n@@ -17,9 +17,10 @@ archcalls = {\n'arm':'armcall',\n}\n-def _loadMacho(vw, filebytes, filename=None):\n+def _loadMacho(vw, filebytes, filename=None, baseaddr=None):\n# We fake them to *much* higher than norm so pointer tests do better...\n+ if baseaddr == None:\nbaseaddr = vw.config.viv.parsers.macho.baseaddr\nif filename == None:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -24,15 +24,15 @@ from vivisect.const import *\n#0x166 MIPS R4000\n#0x183 DEC Alpha AXP\n-def parseFile(vw, filename):\n+def parseFile(vw, filename, baseaddr=None):\npe = PE.PE(file(filename,\"rb\"))\n- return loadPeIntoWorkspace(vw, pe, filename)\n+ return loadPeIntoWorkspace(vw, pe, filename, baseaddr=baseaddr)\n-def parseBytes(vw, bytes):\n+def parseBytes(vw, bytes, baseaddr=None):\nfd = StringIO.StringIO(bytes)\nfd.seek(0)\npe = PE.PE(fd)\n- return loadPeIntoWorkspace(vw, pe, filename=filename)\n+ return loadPeIntoWorkspace(vw, pe, filename=filename, baseaddr=baseaddr)\ndef parseMemory(vw, memobj, base):\npe = PE.peFromMemoryObject(memobj, base)\n@@ -40,10 +40,10 @@ def parseMemory(vw, memobj, base):\n#FIXME does the PE's load address get fixedup on rebase?\nreturn loadPeIntoWorkspace(vw, pe, fname)\n-def parseFd(vw, fd, filename=None):\n+def parseFd(vw, fd, filename=None, baseaddr=None):\nfd.seek(0)\npe = PE.PE(fd)\n- return loadPeIntoWorkspace(vw, pe, filename=filename)\n+ return loadPeIntoWorkspace(vw, pe, filename=filename, baseaddr=baseaddr)\narch_names = {\nPE.IMAGE_FILE_MACHINE_I386:'i386',\n@@ -61,7 +61,7 @@ relmap = {\nPE.IMAGE_REL_BASED_HIGHLOW:vivisect.RTYPE_BASERELOC,\n}\n-def loadPeIntoWorkspace(vw, pe, filename=None):\n+def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nmach = pe.IMAGE_NT_HEADERS.FileHeader.Machine\n@@ -83,8 +83,9 @@ def loadPeIntoWorkspace(vw, pe, filename=None):\nvw.setMeta('DefaultCall', defcalls.get(arch,'unknown'))\n- # Set ourselvs up for extended windows binary analysis\n+ # Set ourselves up for extended windows binary analysis\n+ if baseaddr == None:\nbaseaddr = pe.IMAGE_NT_HEADERS.OptionalHeader.ImageBase\nentry = pe.IMAGE_NT_HEADERS.OptionalHeader.AddressOfEntryPoint + baseaddr\nentryrva = entry - baseaddr\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
commit fail. need all the parsers committed...
|
718,770 |
13.02.2019 15:45:20
| 18,000 |
f46f11a3f9e32b794940c6c18828cb5adc2baac4
|
enable a "supervisor" mode where memory map permissions are ignored. useful for RELOCATIONs
|
[
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -405,6 +405,7 @@ class MemoryObject(IMemory):\n\"\"\"\nIMemory.__init__(self, arch=arch)\nself._map_defs = []\n+ self._supervisor = False\n#FIXME MemoryObject: def allocateMemory(self, size, perms=MM_RWX, suggestaddr=0):\n@@ -462,7 +463,7 @@ class MemoryObject(IMemory):\nmva, mmaxva, mmap, mbytes = mapdef\nif va >= mva and va < mmaxva:\nmva, msize, mperms, mfname = mmap\n- if not mperms & MM_WRITE:\n+ if not (mperms & MM_WRITE or self._supervisor):\nraise envi.SegmentationViolation(va)\noffset = va - mva\nmapdef[3] = mbytes[:offset] + bytes + mbytes[offset+len(bytes):]\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -229,7 +229,9 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nif ptr != (ptr & e_bits.u_maxes[self.psize]):\nlogger.warn('RTYPE_BASERELOC calculated a bad pointer: 0x%x (imgbase: 0x%x)', ptr, imgbase)\n+ self._supervisor = True\nself.writeMemoryPtr(rva, ptr)\n+ self._supervisor = False\nlogger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
enable a "supervisor" mode where memory map permissions are ignored. useful for RELOCATIONs
|
718,770 |
14.02.2019 09:24:54
| 18,000 |
f07928c0f89c8f5837931cedab8da4940e4e6a6e
|
added: RTYPE_BASEOFF, to store offsets from 'imagebase'
fixed: supervisor mode to use "with"
fixed: windows relocation points to use RTPE_BASEOFF
updated: vivisect.analysis.generic.relocations updated to use the new storage format.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -303,11 +303,17 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n'''\nreturn self.comments.items()\n- def addRelocation(self, va, rtype):\n+ def addRelocation(self, va, rtype, data=None):\n\"\"\"\nAdd a relocation entry for tracking.\n+ Expects data to have whatever is necessary for the reloc type. eg. addend\n\"\"\"\n- self._fireEvent(VWE_ADDRELOC, (va, rtype))\n+ # split \"current\" va into fname and offset. future relocations will want to base all va's from an image base\n+ mmva, mmsz, mmperm, fname = self.getMemoryMap(va) # FIXME: getFileByVa does not obey file defs\n+ imgbase = self.getFileMeta(fname, 'imagebase')\n+ offset = va - imgbase\n+\n+ self._fireEvent(VWE_ADDRELOC, (fname, offset, rtype, data))\ndef getRelocations(self):\n\"\"\"\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/relocations.py",
"new_path": "vivisect/analysis/generic/relocations.py",
"diff": "@@ -6,6 +6,12 @@ point to valid locations.\nimport vivisect\ndef analyze(vw):\n- for va, rtype in vw.getRelocations():\n+ for fname, vaoff, rtype, data in vw.getRelocations():\nif rtype == vivisect.RTYPE_BASERELOC and not vw.isLocation(va):\nvw.makePointer(va, follow=True)\n+\n+ elif rtype == vivisect.RTYPE_BASEOFF:\n+ imgbase = vw.getFileMeta(fname, 'imagebase')\n+ va = imgbase + vaoff\n+ if not vw.isLocation(va):\n+ vw.makePointer(va, follow=True)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -216,25 +216,44 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nself.segments.append(einfo)\ndef _handleADDRELOC(self, einfo):\n+ if len(einfo) == 2: # FIXME: legacy: remove after 02/13/2020\nrva,rtype = einfo\n+ mmva, mmsz, mmperm, fname = self.getMemoryMap(rva) # FIXME: getFileByVa does not obey file defs\n+ imgbase = self.getFileMeta(fname, 'imagebase')\n+ data = None\n+ einfo = fname, rva-imgbase, rtype, data\n+ else:\n+ fname, ptroff, rtype, data = einfo\n+ imgbase = self.getFileMeta(fname, 'imagebase')\n+ rva = imgbase + ptroff\n+\nself.reloc_by_va[rva] = rtype\nself.relocations.append(einfo)\nif rtype == RTYPE_BASERELOC:\n- fnm = self.getFileByVa(rva)\n- imgbase = self.getFileMeta(fnm, 'imagebase')\n-\n+ # FIXME: we can't rebase something and expect the pointer in memory to be just the offset...\n+ # consider deprecating this reloc type in favor of BASEOFF\nptr = self.readMemoryPtr(rva)\nptr += imgbase\nif ptr != (ptr & e_bits.u_maxes[self.psize]):\nlogger.warn('RTYPE_BASERELOC calculated a bad pointer: 0x%x (imgbase: 0x%x)', ptr, imgbase)\n- self._supervisor = True\n+ with SupervisorMode(self):\nself.writeMemoryPtr(rva, ptr)\n- self._supervisor = False\nlogger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n+ if rtype == RTYPE_BASEOFF:\n+ # add imgbase and offset to pointer in memory\n+ # 'data' arg must be 'offset' number\n+ ptr = imgbase + data\n+ if ptr != (ptr & e_bits.u_maxes[self.psize]):\n+ logger.warn('RTYPE_BASEOFF calculated a bad pointer: 0x%x (imgbase: 0x%x)', ptr, imgbase)\n+\n+ with SupervisorMode(self):\n+ self.writeMemoryPtr(rva, ptr)\n+\n+ logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\ndef _handleADDMODULE(self, einfo):\nprint('DEPRICATED (ADDMODULE) ignored: %s' % einfo)\n@@ -640,6 +659,13 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nfva,spdelta,symtype,syminfo = locsym\nself.localsyms[fva][spdelta] = locsym\n+class SupervisorMode:\n+ def __init__(self, vw):\n+ self.vw = vw\n+ def __enter__(self):\n+ self.vw._supervisor = 1\n+ def __exit__(self, type, value, traceback):\n+ self.vw._supervisor = 0\ndef trackDynBranches(cfctx, op, vw, bflags, branches):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/const.py",
"new_path": "vivisect/const.py",
"diff": "@@ -165,6 +165,7 @@ EXP_DATA = 1\n# Relocation types\nRTYPE_BASERELOC = 0 # VA contains a pointer to a va (and is assumed fixed up by parser)\n+RTYPE_BASEOFF = 1 # Add Base and Offset to a pointer at a memory location\n# Function Local Symbol Types\nLSYM_NAME = 0 # syminfo is a (typestr,name) tuple\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "import os\nimport PE\n+import logging\nimport vstruct\nimport vivisect\nimport PE.carve as pe_carve\n@@ -17,6 +18,8 @@ import envi.symstore.symcache as e_symcache\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n# PE Machine field values\n#0x14d Intel i860\n#0x14c Intel I386 (same ID used for 486 and 586)\n@@ -58,7 +61,7 @@ defcalls = {\n# map PE relocation types to vivisect types where possible\nrelmap = {\n- PE.IMAGE_REL_BASED_HIGHLOW:vivisect.RTYPE_BASERELOC,\n+ PE.IMAGE_REL_BASED_HIGHLOW:vivisect.RTYPE_BASEOFF,\n}\ndef loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\n@@ -311,9 +314,11 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\n# map PE reloc to VIV reloc ( or dont... )\nvtype = relmap.get(rtype)\nif vtype is None:\n+ logger.info('Skipping PE Relocation type: %d (no handler)', rtype)\ncontinue\n- vw.addRelocation(rva+baseaddr, vtype)\n+ mapoffset = vw.readMemoryPtr(rva+baseaddr) - baseaddr\n+ vw.addRelocation(rva+baseaddr, vtype, mapoffset)\nfor rva, lname, iname in pe.getImports():\nif vw.probeMemory(rva+baseaddr, 4, e_mem.MM_READ):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
added: RTYPE_BASEOFF, to store offsets from 'imagebase'
fixed: supervisor mode to use "with"
fixed: windows relocation points to use RTPE_BASEOFF
updated: vivisect.analysis.generic.relocations updated to use the new storage format.
|
718,770 |
14.02.2019 10:02:18
| 18,000 |
0f2c34c602563315bb59ddf70263f342d1de3090
|
updated: reduction in overhead if memory is already accurate
updated: using contextlib instead of home-grown class for "with" context.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -2,6 +2,7 @@ import Queue\nimport logging\nimport traceback\nimport threading\n+import contextlib\nimport collections\nimport envi\n@@ -230,18 +231,7 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nself.reloc_by_va[rva] = rtype\nself.relocations.append(einfo)\n- if rtype == RTYPE_BASERELOC:\n- # FIXME: we can't rebase something and expect the pointer in memory to be just the offset...\n- # consider deprecating this reloc type in favor of BASEOFF\n- ptr = self.readMemoryPtr(rva)\n- ptr += imgbase\n- if ptr != (ptr & e_bits.u_maxes[self.psize]):\n- logger.warn('RTYPE_BASERELOC calculated a bad pointer: 0x%x (imgbase: 0x%x)', ptr, imgbase)\n-\n- with SupervisorMode(self):\n- self.writeMemoryPtr(rva, ptr)\n-\n- logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n+ # RTYPE_BASERELOC assumes the memory is already accurate (eg. PE's unless rebased)\nif rtype == RTYPE_BASEOFF:\n# add imgbase and offset to pointer in memory\n@@ -250,10 +240,20 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nif ptr != (ptr & e_bits.u_maxes[self.psize]):\nlogger.warn('RTYPE_BASEOFF calculated a bad pointer: 0x%x (imgbase: 0x%x)', ptr, imgbase)\n- with SupervisorMode(self):\n+ # writes are costly, especially on larger binaries\n+ if ptr == self.readMemoryPtr(rva):\n+ return\n+\n+ with self.getAdminRights():\nself.writeMemoryPtr(rva, ptr)\n- logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n+ #logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n+\n+ @contextlib.contextmanager\n+ def getAdminRights(self):\n+ self._supervisor = True\n+ yield\n+ self._supervisor = False\ndef _handleADDMODULE(self, einfo):\nprint('DEPRICATED (ADDMODULE) ignored: %s' % einfo)\n@@ -659,14 +659,6 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nfva,spdelta,symtype,syminfo = locsym\nself.localsyms[fva][spdelta] = locsym\n-class SupervisorMode:\n- def __init__(self, vw):\n- self.vw = vw\n- def __enter__(self):\n- self.vw._supervisor = 1\n- def __exit__(self, type, value, traceback):\n- self.vw._supervisor = 0\n-\ndef trackDynBranches(cfctx, op, vw, bflags, branches):\n'''\ntrack dynamic branches\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updated: reduction in overhead if memory is already accurate
updated: using contextlib instead of home-grown class for "with" context.
|
718,770 |
14.02.2019 10:03:48
| 18,000 |
e6549564335f27e7c4bb7be31c42dfc8e94a055c
|
better placement for getAdminRights()
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -196,6 +196,12 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\n'''\nself._event_saved = len(self._event_list)\n+ @contextlib.contextmanager\n+ def getAdminRights(self):\n+ self._supervisor = True\n+ yield\n+ self._supervisor = False\n+\ndef _handleADDLOCATION(self, loc):\nlva, lsize, ltype, linfo = loc\nself.locmap.setMapLookup(lva, lsize, loc)\n@@ -249,12 +255,6 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\n#logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n- @contextlib.contextmanager\n- def getAdminRights(self):\n- self._supervisor = True\n- yield\n- self._supervisor = False\n-\ndef _handleADDMODULE(self, einfo):\nprint('DEPRICATED (ADDMODULE) ignored: %s' % einfo)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
better placement for getAdminRights()
|
718,770 |
22.02.2019 02:28:54
| 18,000 |
2de47ad24f071bf343083a333193de1bd7c2df2d
|
massive cleanup of arm regs...
test cases
bug-fixes in decoding and emulation.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -4850,7 +4850,7 @@ class ArmExtRegListOper(ArmOperand):\nreturn None\nreglist = []\nfor regidx in xrange(self.firstreg, self.firstreg + self.count):\n- reg = emu.getRegister(REGS_VECTOR_BASE_IDX + regidx)\n+ reg = emu.getRegister(REGS_VECTOR_TABLE_IDX + regidx)\nreglist.append(reg)\nreturn reglist\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -56,8 +56,9 @@ class CoProcEmulator: # useful for prototyping, but should be subclassed\ndef _getRegIdx(idx, mode):\n- if idx >= MAX_REGS:\n- return idx\n+ if idx >= REGS_VECTOR_TABLE_IDX:\n+ return reg_table[idx]\n+\nridx = idx + (mode*REGS_PER_MODE) # account for different banks of registers\nridx = reg_table[ridx] # magic pointers allowing overlapping banks of registers\nreturn ridx\n@@ -336,7 +337,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nset the SPSR for the given ARM processor mode\n'''\nridx = _getRegIdx(REG_OFFSET_CPSR, mode)\n- psr = self._rctx_vals[REG_CPSR] & (~mask) | (psr & mask)\n+ psr = self._rctx_vals[ridx] & (~mask) | (psr & mask)\nself._rctx_vals[ridx] = psr\ndef setProcMode(self, mode):\n@@ -384,7 +385,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself._rctx_dirty = True\n+ # the raw index (in case index is a metaregister)\nidx = (index & 0xffff)\n+\n+ # we only keep separate register banks per mode for general registers, not vectors\n+ if idx >= REGS_VECTOR_TABLE_IDX:\n+ ridx = idx\n+ else:\nridx = _getRegIdx(idx, mode)\nif idx == index: # not a metaregister\n@@ -396,8 +403,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\noffset = (index >> 24) & 0xff\nwidth = (index >> 16) & 0xff\n- #FIXME is it faster to generate or look thses up?\n- mask = (2**width)-1\n+ mask = e_bits.b_masks[width]\nmask = mask << offset\n# NOTE: basewidth is in *bits*\n@@ -460,13 +466,19 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nsdst = e_bits.signed(src1, tsize)\nssrc = e_bits.signed(src2, tsize)\n- ures = e_bits.unsigned(udst + usrc + carry, tsize)\n- sres = e_bits.signed(sdst + ssrc + carry, tsize)\n- result = ures & 0x7fffffff\n+ #ures = e_bits.unsigned(udst + usrc + carry, tsize)\n+ #sres = e_bits.signed(sdst + ssrc + carry, tsize)\n+ ures = udst + usrc + carry\n+ sres = sdst + ssrc + carry\n+ result = ures & 0xffffffff\nnewcarry = (ures != result)\n- #newcarry = (udst >= usrc)\n- overflow = (sres != result)\n+ overflow = (e_bits.unsigned(sres, 4) != result)\n+\n+ #print \"=====================\"\n+ #print hex(udst), hex(usrc), hex(ures), hex(result)\n+ #print hex(sdst), hex(ssrc), hex(sres)\n+ #print e_bits.is_signed(result, tsize), not result, newcarry, overflow\nif Sflag:\ncurmode = self.getProcMode()\n@@ -712,7 +724,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nelif len(op.opers) == 3:\n# 2 core reg to double\n# move between two ARM Core regs and one dblword extension reg\n- if op.opers[0].reg < REGS_VECTOR_BASE_IDX:\n+ if op.opers[0].reg < REGS_VECTOR_TABLE_IDX:\n# dest is core regs\nsrc = self.getOperValue(op, 2)\nself.setOperValue(op, 0, (src & 0xffffffff))\n@@ -875,7 +887,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nnewpc = self.getRegister(REG_PC) # check whether pc has changed\nif pc != newpc:\nself.setThumbMode(newpc & 1)\n- return newpc\n+ return newpc & -2\ni_ldmia = i_ldm\ni_pop = i_ldmia\n@@ -1127,7 +1139,9 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn self.getOperValue(op, 0)\ndef i_bl(self, op):\n- self.setRegister(REG_LR, self.getRegister(REG_PC) + len(op))\n+ tmode = self.getFlag(PSR_T_bit)\n+ retva = (self.getRegister(REG_PC) + len(op)) | tmode\n+ self.setRegister(REG_LR, retva)\nreturn self.getOperValue(op, 0)\ndef i_bx(self, op):\n@@ -1136,7 +1150,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn target & -2\ndef i_blx(self, op):\n- self.setRegister(REG_LR, self.getRegister(REG_PC) + len(op))\n+ tmode = self.getFlag(PSR_T_bit)\n+ retva = (self.getRegister(REG_PC) + len(op)) | tmode\n+ self.setRegister(REG_LR, retva)\n+\ntarget = self.getOperValue(op, 0)\nself.setFlag(PSR_T_bit, target & 1)\nreturn target & -2\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/regs.py",
"new_path": "envi/archs/arm/regs.py",
"diff": "@@ -30,8 +30,6 @@ arm_regs = [\n('nil', 32), # place holder\n# FIXME: need to deal with ELR_hyp\n]\n-MAX_REGS = 17\n-#arm_regs.extend([('q%d' % x, 128) for x in range(VFP_QWORD_REG_COUNT)])\n# force them into a tuple for faster run-time access\narm_regs = tuple(arm_regs)\n@@ -50,7 +48,11 @@ modes.sort()\nreg_table = [ x for x in range(17 * REGS_PER_MODE) ]\nreg_data = [ (reg, sz) for reg,sz in arm_regs ]\n+reg_table_data = [ (None, 32) for x in range(17 * REGS_PER_MODE) ]\n+for idx,data in enumerate(reg_data):\n+ reg_table_data[idx] = data\n+# banked registers for different processor modes\nfor modenum in modes[1:]: # skip first since we're already done\n(mname, msname, desc, offset, mode_reg_count, PSR_offset, priv_level) = proc_modes.get(modenum)\n# shared regs\n@@ -58,20 +60,31 @@ for modenum in modes[1:]: # skip first since we're already done\n# don't create new entries for this register, use the usr-mode reg\nreg_table[ridx+offset] = ridx\n- # mode-regs (including PC)\n+ rnm, rsz = arm_regs[ridx]\n+ reg_table_data[ridx+offset] = ('%s_%s' % (rnm, msname), rsz)\n+\n+ # mode-regs (not including PC)\nfor ridx in range(mode_reg_count, 15):\nidx = len(reg_data)\n- reg_data.append((arm_regs[ridx][0]+\"_\"+msname, 32))\n+ rnm, rsz = arm_regs[ridx]\n+ regname = rnm+\"_\"+msname\n+ reg_data.append((regname, 32))\nreg_table[ridx+offset] = idx\n+ reg_table_data[ridx+offset] = (regname, rsz)\n+\n# PC\nreg_table[PSR_offset-3] = 15\n+ reg_table_data[PSR_offset-3] = ('pc_%s' % (msname), 32)\n# CPSR\nreg_table[PSR_offset-2] = 16 # SPSR....??\n+ reg_table_data[PSR_offset-2] = ('CPSR_%s' % (msname), 32)\n# NIL\nreg_table[PSR_offset-1] = 17\n+ reg_table_data[PSR_offset-1] = ('NIL_%s' % (msname), 32)\n# PSR\nreg_table[PSR_offset] = len(reg_data)\n+ reg_table_data[PSR_offset] = ('SPSR_%s' % (msname), 32)\nreg_data.append((\"SPSR_\"+msname, 32))\n# done with banked register translation table\n@@ -87,12 +100,17 @@ for modenum in modes[1:]: # skip first since we're already done\n# we implement VFPv4-D32 since it should be backwards-compatible with all others\n# the largest accessor of this extended register bank is 128bits so we'll go with that.\n-REGS_VECTOR_BASE_IDX = len(reg_data)\n+REGS_VECTOR_TABLE_IDX = len(reg_table)\n+REGS_VECTOR_DATA_IDX = len(reg_data)\n+REGS_VECTOR_DELTA = REGS_VECTOR_TABLE_IDX - REGS_VECTOR_DATA_IDX\n+\nfor simdreg in range(VFP_QWORD_REG_COUNT):\n- simd_idx = REGS_VECTOR_BASE_IDX + simdreg\n+ simd_idx = REGS_VECTOR_TABLE_IDX + simdreg\nd = simdreg * 2\ns = d * 2\n+ reg_table.append(len(reg_data))\nreg_data.append((\"q%d\" % simdreg, 128))\n+ reg_table_data.append((\"q%d\" % simdreg, 128))\nif simdreg < 8: # VFPv4 only allows S# indexing up to S31\narm_metas.append((\"s%d\" % (s), simd_idx, 0, 32))\narm_metas.append((\"s%d\" % (s+1), simd_idx, 32, 32))\n@@ -101,9 +119,13 @@ for simdreg in range(VFP_QWORD_REG_COUNT):\narm_metas.append((\"d%d\" % (d), simd_idx, 0, 64))\narm_metas.append((\"d%d\" % (d+1), simd_idx, 32, 64))\n-REG_FPSCR = len(reg_data)\n+REG_FPSCR = len(reg_table)\n+reg_table.append(len(reg_data))\nreg_data.append(('fpscr', 32))\n+\n+MAX_TABLE_SIZE = len(reg_table_data)\n+\nl = locals()\ne_reg.addLocalEnums(l, arm_regs)\n@@ -192,11 +214,14 @@ arm_status_metas = [\ne_reg.addLocalStatusMetas(l, arm_metas, arm_status_metas, \"CPSR\")\ne_reg.addLocalMetas(l, arm_metas)\n+def getRegDataIdx(idx):\n+ ridx = reg_table[idx] # magic pointers allowing overlapping banks of registers\n+ return ridx\nclass ArmRegisterContext(e_reg.RegisterContext):\ndef __init__(self):\ne_reg.RegisterContext.__init__(self)\n- self.loadRegDef(reg_data)\n+ self.loadRegDef(reg_table_data)\nself.loadRegMetas(arm_metas, statmetas=arm_status_metas)\nself.setRegisterIndexes(REG_PC, REG_SP)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -16,8 +16,8 @@ from envi.archs.arm.disasm import *\nfrom envi.tests.armthumb_tests import advsimdtests\n-GOOD_TESTS = 5612\n-GOOD_EMU_TESTS = 840\n+GOOD_TESTS = 5615\n+GOOD_EMU_TESTS = 839\n'''\nThis dictionary will contain all instructions supported by ARM to test\nFields will contain following information:\n@@ -33,6 +33,56 @@ GOOD_EMU_TESTS = 840\n#HB, HBL, HBLP, HBP - thumbee instructions see A9.1125-1127\n#IT - thumb\n+\n+'''\n+CMP verification (Raspberry Pi 2, hijacking /bin/chown's startup process in ARM mode):\n+\n+(gdb) set *(int*)$pc = 0xe1500002\n+(gdb) set *(int*)($pc+4) = 0x3a000031\n+\n+(gdb) x/2i $pc\n+=> 0x11380 <__libc_start_main@plt>: cmp r0, r2\n+ 0x11384 <__libc_start_main@plt+4>: bcc 0x11450 <fscanf@plt+8>\n+\n+(gdb) stepi\n+0x00011384 in __libc_start_main@plt ()\n+1: x/i $pc\n+=> 0x11384 <__libc_start_main@plt+4>: bcc 0x11450 <fscanf@plt+8>\n+\n+(gdb) info reg r0 r2 cpsr\n+r0 0x11599 71065\n+r2 0x7efff6e4 2130704100\n+cpsr 0x800e0010 -2146566128\n+\n+(gdb) stepi\n+0x00011450 in fscanf@plt ()\n+1: x/i $pc\n+=> 0x11450 <fscanf@plt+8>: ldr pc, [r12, #3208]! ; 0xc88\n+\n+so since r0 is less than r2, cpsr's \"Negative\" flag should be set and \"bcc\" branch should be taken.\n+\n+\n+also:\n+(gdb) set *(int*)$pc = 0xe3530cff\n+(gdb) x/i $pc\n+=> 0x11450 <fscanf@plt+8>: cmp r3, #65280 ; 0xff00\n+\n+(gdb) info reg r3 cpsr\n+r3 0x17341 95041\n+cpsr 0x800e0010 -2146566128\n+\n+(gdb) stepi\n+0x00011454 in __printf_chk@plt ()\n+1: x/i $pc\n+=> 0x11454 <__printf_chk@plt>: add r12, pc, #0, 12\n+\n+(gdb) info reg r3 cpsr\n+r3 0x17341 95041\n+cpsr 0x200e0010 537788432\n+\n+in this case, since r3 was greater than 0xff00, the\n+\n+'''\ninstrs = [\n(REV_ALL_ARM, '08309fe5', 0xbfb00000, 'ldr r3, [#0xbfb00010]', 0, ()),\n(REV_ALL_ARM, '0830bbe5', 0xbfb00000, 'ldr r3, [r11, #0x8]!', 0, ()),\n@@ -511,7 +561,14 @@ instrs = [\n(REV_ALL_ARM, '273764ee', 0x4560, 'cdp p7, 6, cr3, cr4, cr7, 1', 0, ()),\n(REV_ALL_ARM, '473b34ee', 0x4560, 'vsub.f64 d3, d4, d7', 0, ()),\n(REV_ALL_ARM, 'ff0c74e3', 0x4560, 'cmn r4, #0xff00', 0, ()),\n- (REV_ALL_ARM, 'ff0c54e3', 0x4560, 'cmp r4, #0xff00', 0, ()),\n+ (REV_ALL_ARM, 'ff0c54e3', 0x4560, 'cmp r4, #0xff00', 0, (\n+ {'setup':(('r4',0x17341), ('cpsr',0)),\n+ 'tests':(('cpsr',0b00100000000000000000000000000000),) },\n+ )),\n+ (REV_ALL_ARM, '020050e1', 0x4560, 'cmp r0, r2', 0, (\n+ {'setup':(('r0',0x11599),('r2',0x7efff6e4), ('cpsr',0)),\n+ 'tests':(('cpsr',0b10000000000000000000000000000000),) },\n+ )),\n(REV_ALL_ARM, 'ff4c23e2', 0x4560, 'eor r4, r3, #0xff00', 0, ()),\n(REV_ALL_ARM, 'ff4c33e2', 0x4560, 'eors r4, r3, #0xff00', 0, ()),\n(REV_ALL_ARM, '073894ed', 0x4560, 'ldc p8, cr3, [r4, #0x1c]', 0, ()),\n@@ -1692,7 +1749,7 @@ class ArmInstructionSet(unittest.TestCase):\nop = vw.arch.archParseOpcode(bytez.decode('hex'), 0, va)\n#print repr(op)\nredoprepr = repr(op).replace(' ','').lower()\n- redgoodop = reprOp.replace(' ','')\n+ redgoodop = reprOp.replace(' ','').lower()\nif redoprepr != redgoodop:\nprint bytez,redgoodop\nprint bytez,redoprepr\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
massive cleanup of arm regs...
test cases
bug-fixes in decoding and emulation.
|
718,770 |
23.02.2019 17:27:27
| 18,000 |
e6b0e5b7b680fa2892c0b2a95ba2c7f7adb30b98
|
arm unit test enhancements (more coming...)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -9,6 +9,9 @@ import envi.archs.arm as arm\nimport vivisect\nimport platform\nimport unittest\n+\n+import test_arch_arm_cmp_flags\n+\nfrom envi import IF_RET, IF_NOFALL, IF_BRANCH, IF_CALL, IF_COND\nfrom envi.archs.arm.regs import *\nfrom envi.archs.arm.const import *\n@@ -16,8 +19,8 @@ from envi.archs.arm.disasm import *\nfrom envi.tests.armthumb_tests import advsimdtests\n-GOOD_TESTS = 5615\n-GOOD_EMU_TESTS = 839\n+GOOD_TESTS = 5618\n+GOOD_EMU_TESTS = 850\n'''\nThis dictionary will contain all instructions supported by ARM to test\nFields will contain following information:\n@@ -82,6 +85,27 @@ cpsr 0x200e0010 537788432\nin this case, since r3 was greater than 0xff00, the\n+\n+\n+in another bin, chosen for it's deps on libstdc++:\n+(gdb) set *(int*)($pc)=0xe1510003\n+(gdb) set *(int*)($pc+4)=0x31a04003\n+(gdb) set $r1=9\n+(gdb) set $r3=0\n+(gdb) x/8i $pc\n+=> 0x54aab8cc <_Z10InitLocalev@plt>: cmp r1, r3\n+ 0x54aab8d0 <_Z10InitLocalev@plt+4>: movcc r4, r3\n+(gdb) si\n+0x54aab8d0 in InitLocale()@plt ()\n+1: x/i $pc\n+=> 0x54aab8d0 <_Z10InitLocalev@plt+4>: movcc r4, r3\n+(gdb) si\n+... <snip>\n+(gdb)info reg r4 r3 cpsr\n+r4 0x54aac14d 1420476749\n+r3 0x0 0\n+cpsr 0x200d0010 537722896\n+\n'''\ninstrs = [\n(REV_ALL_ARM, '08309fe5', 0xbfb00000, 'ldr r3, [#0xbfb00010]', 0, ()),\n@@ -452,6 +476,10 @@ instrs = [\n(REV_ALL_ARM, '3746f3e0', 0x4560, 'rscs r4, r3, r7, lsr r6', 0, ()),\n(REV_ALL_ARM, '374613e1', 0x4560, 'tst r3, r7, lsr r6', 0, ()),\n(REV_ALL_ARM, '374623e1', 0x4560, 'blx r7', 0, ()),\n+ (REV_ALL_ARM, '0340a031', 0x4560, 'movcc r4, r3', 0, (\n+ {'setup':(('r3',0xaa),('r4',0x1a),('cpsr',0b00100000000000000000000000000000)),\n+ 'tests':(('r3',0xaa),('r4',0x1a)), },\n+ )),\n(REV_ALL_ARM, '374633e1', 0x4560, 'teq r3, r7, lsr r6', 0, ()),\n(REV_ALL_ARM, '374653e1', 0x4560, 'cmp r3, r7, lsr r6', 0, ()),\n(REV_ALL_ARM, '374673e1', 0x4560, 'cmn r3, r7, lsr r6', 0, ()),\n@@ -565,9 +593,14 @@ instrs = [\n{'setup':(('r4',0x17341), ('cpsr',0)),\n'tests':(('cpsr',0b00100000000000000000000000000000),) },\n)),\n+ (REV_ALL_ARM, '024050e0', 0x4560, 'subs r4, r0, r2', 0, (\n+ test_arch_arm_cmp_flags.cmp_tests\n+ )),\n(REV_ALL_ARM, '020050e1', 0x4560, 'cmp r0, r2', 0, (\n- {'setup':(('r0',0x11599),('r2',0x7efff6e4), ('cpsr',0)),\n- 'tests':(('cpsr',0b10000000000000000000000000000000),) },\n+ test_arch_arm_cmp_flags.cmp_tests\n+ )),\n+ (REV_ALL_ARM, '070073e1', 0x4560, 'cmn r3, r7', 0, (\n+ test_arch_arm_cmp_flags.cmn_tests\n)),\n(REV_ALL_ARM, 'ff4c23e2', 0x4560, 'eor r4, r3, #0xff00', 0, ()),\n(REV_ALL_ARM, 'ff4c33e2', 0x4560, 'eors r4, r3, #0xff00', 0, ()),\n@@ -1787,15 +1820,16 @@ class ArmInstructionSet(unittest.TestCase):\nbademu += 1\nelse:\n# if we have a special test lets run it\n- for sCase in emutests:\n+ for tidx, sCase in enumerate(emutests):\n#allows us to just have a result to check if no setup needed\nif 'tests' in sCase:\nsetters = ()\nif 'setup' in sCase:\nsetters = sCase['setup']\ntests = sCase['tests']\n- if not self.validateEmulation(emu, op, (setters), (tests)):\n+ if not self.validateEmulation(emu, op, (setters), (tests), tidx):\ngoodcount += 1\n+ goodemu += 1\nelse:\nbademu += 1\nraise Exception( \"FAILED emulation (special case): %.8x %s - %s\" % (va, bytez, op) )\n@@ -1823,7 +1857,7 @@ class ArmInstructionSet(unittest.TestCase):\ndef test_envi_arm_thumb_switches(self):\npass\n- def validateEmulation(self, emu, op, setters, tests):\n+ def validateEmulation(self, emu, op, setters, tests, tidx=0):\n# first set any environment stuff necessary\n## defaults\nemu.setRegister(REG_R3, 0x414141)\n@@ -1848,7 +1882,7 @@ class ArmInstructionSet(unittest.TestCase):\n#For this couldn't we set a temp value equal to endian and write that? Assuming byte order is issue with this one\nemu.writeMemValue(tgt, val, 1) # limited to 1-byte writes currently\nelse:\n- raise Exception( \"Funkt up Setting: %s = 0x%x\" % (tgt, val) )\n+ raise Exception( \"Funkt up Setting: (%r test#%d) %s = 0x%x\" % (op, tidx, tgt, val) )\nemu.executeOpcode(op)\nif not len(tests):\nsuccess = 0\n@@ -1862,7 +1896,7 @@ class ArmInstructionSet(unittest.TestCase):\n#print(\"SUCCESS(reg): %s == 0x%x\" % (tgt, val))\nsuccess = 0\nelse: # should be an else\n- raise Exception(\"FAILED(reg): %s != 0x%x (observed: 0x%x)\" % (tgt, val, testval))\n+ raise Exception(\"FAILED(reg): (%r test#%d) %s != 0x%x (observed: 0x%x) \\n\\t(setters: %r)\\n\\t(test: %r)\" % (op, tidx, tgt, val, testval, setters, tests))\nexcept e_reg.InvalidRegisterName, e:\n# it's not a register\nif type(tgt) == str and tgt.startswith(\"PSR_\"):\n@@ -1872,17 +1906,19 @@ class ArmInstructionSet(unittest.TestCase):\n#print(\"SUCCESS(flag): %s == 0x%x\" % (tgt, val))\nsuccess = 0\nelse:\n- raise Exception(\"FAILED(flag): %s != 0x%x (observed: 0x%x)\" % (tgt, val, testval))\n+ raise Exception(\"FAILED(flag): (%r test#%d) %s != 0x%x (observed: 0x%x) \\n\\t(setters: %r)\\n\\t(test: %r)\" % (op, tidx, tgt, val, testval, setters, tests))\n+ #raise Exception(\"FAILED(flag): (%r test#%d) %s != 0x%x (observed: 0x%x)\" % (op, tidx, tgt, val, testval))\nelif type(tgt) in (long, int):\n# it's an address\ntestval = emu.readMemValue(tgt, 1)\nif testval == val:\n#print(\"SUCCESS(addr): 0x%x == 0x%x\" % (tgt, val))\nsuccess = 0\n- raise Exception(\"FAILED(mem): 0x%x != 0x%x (observed: 0x%x)\" % (tgt, val, testval))\n+ #raise Exception(\"FAILED(mem): (%r test#%d) 0x%x != 0x%x (observed: 0x%x)\" % (op, tidx, tgt, val, testval))\n+ raise Exception(\"FAILED(mem): (%r test#%d) 0x%x != 0x%x (observed: 0x%x) \\n\\t(setters: %r)\\n\\t(test: %r)\" % (op, tidx, tgt, val, testval, setters, tests))\nelse:\n- raise Exception( \"Funkt up test: %s == %s\" % (tgt, val) )\n+ raise Exception( \"Funkt up test (%r test#%d) : %s == %s\" % (op, tidx, tgt, val) )\n# NOTE: Not sure how to test this to see if working\n# do some read/write tracking/testing\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "envi/tests/test_arch_arm_cmp_flags.py",
"diff": "+cmp_tests = ( \\\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },)\n+\n+cmn_tests = ( \\\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fff),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8001),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x0), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7ffffff),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000000),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x8000001),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x7fff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x7ffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x8000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x90000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x7fffffff),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x60000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x80000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x70000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000000),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x30000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x7fffffff), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x60000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x80000000), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x30000000), ), },\n+{ \"setup\" : ( (\"r3\",0x80000001),(\"r7\",0x80000001), (\"cpsr\",0), (\"r5\",0)),\n+ \"tests\" : ( (\"cpsr\", 0x30000000), ), },)\n+\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm unit test enhancements (more coming...)
|
718,765 |
25.02.2019 16:05:14
| 18,000 |
e8ab15e051715783b31cd1dcc53a71ce26d10214
|
it runs at least
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/h8/emu.py",
"new_path": "envi/archs/h8/emu.py",
"diff": "@@ -7,8 +7,10 @@ import logging\nimport envi\nimport envi.bits as e_bits\n+import envi.const as e_const\n+import envi.archs.h8.regs as h8_regs\n+import envi.archs.h8.const as h8_const\nfrom envi.archs.h8 import H8Module\n-from envi.archs.h8.regs import *\nfrom operands import H8RegDirOper\n@@ -80,28 +82,32 @@ class H8CallAdv(envi.CallingConvention):\nreference: C_H8_User_Manual.pdf\n\"\"\"\n- arg_def = [(CC_REG, REG_ER0), (CC_REG, REG_ER1), (CC_REG, REG_ER2), (CC_STACK_INF, 4),]\n- retaddr_def = (CC_STACK_INF, 0)\n- retval_def = (CC_REG, REG_ER0), (CC_STACK_INF, 0) #FIXME\n- flags = CC_CALLEE_CLEANUP\n+ arg_def = [(e_const.CC_REG, h8_regs.REG_ER0),\n+ (e_const.CC_REG, h8_regs.REG_ER1),\n+ (e_const.CC_REG, h8_regs.REG_ER2),\n+ (e_const.CC_STACK_INF, 4)]\n+ retaddr_def = (e_const.CC_STACK_INF, 0)\n+ retval_def = (e_const.CC_REG, h8_regs.REG_ER0), (e_const.CC_STACK_INF, 0) # FIXME\n+ flags = e_const.CC_CALLEE_CLEANUP\nalign = 2\npad = 0\n- def execCallReturn(self, emu, value, ccinfo=None):\n- sp = emu.getRegister(REG_SP)\n+ def execCallReturn(self, emu, value, argc=None):\n+ sp = emu.getRegister(h8_regs.REG_SP)\npc = struct.unpack('>H', emu.readMemory(sp, 2))[0]\nsp += 2 # For the saved pc\nsp += (2 * argc) # Cleanup saved args\n- emu.setRegister(REG_SP, sp)\n- emu.setRegister(REG_R0, value)\n+ emu.setRegister(h8_regs.REG_SP, sp)\n+ emu.setRegister(h8_regs.REG_R0, value)\nemu.setProgramCounter(pc)\ndef getCallArgs(self, emu, count):\n- return emu.getRegister(0xf) # r0-r3 are used to hand in parameters. additional ph8s are stored and pointed to by r0\n+ # r0-r3 are used to hand in parameters. additional ph8s are stored and pointed to by r0\n+ return emu.getRegister(0xf)\n-h8call = H8CallAdv()\n+h8call = H8CallAdv()\nCPUSTATE_RESET = 0\nCPUSTATE_EXC = 1\n@@ -111,18 +117,19 @@ CPUSTATE_SLEEP = 4\nCPUSTATE_SWSTDBY = 5\nCPUSTATE_HWSTDBY = 6\n-class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\n+\n+class H8Emulator(H8Module, h8_regs.H8RegisterContext, envi.Emulator):\nIVT_RESET = 0\ndef __init__(self, advanced=True):\nH8Module.__init__(self)\nenvi.Emulator.__init__(self, self)\n- H8RegisterContext.__init__(self)\n+ h8_regs.H8RegisterContext.__init__(self)\nself.state = CPUSTATE_RESET\nself.ptrsz = 0\n- seglist = [ (0,0xffffffff) for x in xrange(6) ]\n+ # seglist = [(0,0xffffffff) for x in xrange(6)]\nself.setAdvanced(advanced)\nself.addCallingConvention(\"H8 Arch Procedure Call\", h8call)\n@@ -150,7 +157,7 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nFrom outside the emulator, cause an interrupt to be handled.\nFIXME: wants to pause the run()/runFunction() thread, if any active\n'''\n- va = emuProcessInterrupt_2140(intval)\n+ va = self.emuProcessInterrupt_2140(intval)\nself.setProgramCounter(va)\ndef emuProcessInterrupt_2140(self, intval=0):\n@@ -226,19 +233,19 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nA flag setting operation has resulted in un-defined value. Set\nthe flags to un-defined as well.\n\"\"\"\n- self.setRegister(REG_FLAGS, None)\n+ self.setRegister(h8_const.REG_FLAGS, None)\ndef setFlag(self, which, state):\n- flags = self.getRegister(REG_FLAGS)\n+ flags = self.getRegister(h8_const.REG_FLAGS)\nif state:\nflags |= which\nelse:\nflags &= ~which\n- self.setRegister(REG_FLAGS, flags)\n+ self.setRegister(h8_const.REG_FLAGS, flags)\ndef getFlag(self, which):\n- flags = self.getRegister(REG_FLAGS)\n- if flags == None:\n+ flags = self.getRegister(h8_const.REG_FLAGS)\n+ if flags is None:\nraise envi.PDEUndefinedFlag(self)\nreturn bool(flags & which)\n@@ -247,23 +254,23 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\n# other than None, that is the new pc\nx = None\nmeth = self.op_methods.get(op.mnem, None)\n- if meth == None:\n+ if meth is None:\nraise envi.UnsupportedInstruction(self, op)\nx = meth(op)\n- if x == None:\n+ if x is None:\npc = self.getProgramCounter()\nx = pc+op.size\nself.setProgramCounter(x)\n- def doPush(self, val, inc=2, reg=REG_SP):\n+ def doPush(self, val, inc=2, reg=h8_const.REG_SP):\nsp = self.getRegister(reg)\nsp -= inc\nself.writeMemValue(sp, val, inc)\nself.setRegister(reg, sp)\n- def doPop(self, inc=2, reg=REG_SP):\n+ def doPop(self, inc=2, reg=h8_const.REG_SP):\nsp = self.getRegister(reg)\nval = self.readMemValue(sp, inc)\nself.setRegister(reg, sp+inc)\n@@ -274,23 +281,23 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nres = self.logicalAnd(op)\nself.setOperValue(op, 1, res)\n- self.setFlag(CCR_Z, not res)\n- self.setFlag(CCR_N, e_bits.is_signed(res, dsize))\n- self.setFlag(CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_Z, not res)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(res, dsize))\n+ self.setFlag(h8_regs.CCR_V, 0)\ndef i_andc(self, op):\nres = self.logicalAnd(op)\nself.setOperValue(op, 1, res)\ndef i_band(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\nval = self.getOperValue(op, 1)\nval >>= bit\nval &= C\n- self.setFlag(CCR_C, val)\n+ self.setFlag(h8_regs.CCR_C, val)\ndef i_bra(self, op):\nnextva = self.getOperValue(op, 0)\n@@ -300,85 +307,85 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\npass\ndef i_bhi(self, op):\n- if not (self.getFlag(CCR_C) == 0 or self.getFlag(CCR_Z) == 0):\n+ if not (self.getFlag(h8_regs.CCR_C) == 0 or self.getFlag(h8_regs.CCR_Z) == 0):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bls(self, op):\n- if not (self.getFlag(CCR_C) or self.getFlag(CCR_Z)):\n+ if not (self.getFlag(h8_regs.CCR_C) or self.getFlag(h8_regs.CCR_Z)):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bhs(self, op):\n- if self.getFlag(CCR_C):\n+ if self.getFlag(h8_regs.CCR_C):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_blo(self, op):\n- if not self.getFlag(CCR_C):\n+ if not self.getFlag(h8_regs.CCR_C):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bne(self, op):\n- if self.getFlag(CCR_Z):\n+ if self.getFlag(h8_regs.CCR_Z):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_beq(self, op):\n- if not self.getFlag(CCR_Z):\n+ if not self.getFlag(h8_regs.CCR_Z):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bvc(self, op):\n- if self.getFlag(CCR_V):\n+ if self.getFlag(h8_regs.CCR_V):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bvs(self, op):\n- if not self.getFlag(CCR_V):\n+ if not self.getFlag(h8_regs.CCR_V):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bpl(self, op):\n- if self.getFlag(CCR_N):\n+ if self.getFlag(h8_regs.CCR_N):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bmi(self, op):\n- if not self.getFlag(CCR_N):\n+ if not self.getFlag(h8_regs.CCR_N):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bge(self, op): # FIXME: TEST. these last 4 seem mixed up.\n- if self.getFlag(CCR_V) != self.getFlag(CCR_N):\n+ if self.getFlag(h8_regs.CCR_V) != self.getFlag(h8_regs.CCR_N):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_blt(self, op): # FIXME: TEST. these last 4 seem mixed up.\n- if self.getFlag(CCR_V) == self.getFlag(CCR_N):\n+ if self.getFlag(h8_regs.CCR_V) == self.getFlag(h8_regs.CCR_N):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_bgt(self, op): # FIXME: TEST. these last 4 seem mixed up.\n- if (self.getFlag(CCR_V) != self.getFlag(CCR_N)) or self.getFlag(CCR_Z):\n+ if (self.getFlag(h8_regs.CCR_V) != self.getFlag(h8_regs.CCR_N)) or self.getFlag(h8_regs.CCR_Z):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\ndef i_ble(self, op): # FIXME: TEST. these last 4 seem mixed up.\n- if not ((self.getFlag(CCR_V) != self.getFlag(CCR_N)) and self.getFlag(CCR_Z)):\n+ if not ((self.getFlag(h8_regs.CCR_V) != self.getFlag(h8_regs.CCR_N)) and self.getFlag(h8_regs.CCR_Z)):\nreturn\nnextva = self.getOperValue(op, 0)\nreturn nextva\n@@ -388,7 +395,6 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ni_bcc = i_bhs\ni_bcs = i_blo\n-\ndef i_bclr(self, op):\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\n@@ -397,30 +403,30 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, tgt)\ndef i_biand(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC &= ~(tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_bild(self, op):\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC = ~(tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_bior(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC |= ~(tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_bist(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\n@@ -429,19 +435,19 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, tgt)\ndef i_bixor(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC ^= ~(tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_bld(self, op):\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC = (tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_bnot(self, op):\nbit = self.getOperValue(op, 0)\n@@ -451,12 +457,12 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, tgt)\ndef i_bor(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC |= (tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_bset(self, op):\nbit = self.getOperValue(op, 0)\n@@ -466,7 +472,7 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, tgt)\ndef i_bst(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\n@@ -479,15 +485,15 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ntgt = self.getOperValue(op, 1)\nZ = ((tgt >> bit) & 1) ^ 1\n- self.setFlag(CCR_Z, Z)\n+ self.setFlag(h8_regs.CCR_Z, Z)\ndef i_bxor(self, op):\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nbit = self.getOperValue(op, 0)\ntgt = self.getOperValue(op, 1)\nC ^= (tgt >> bit) & 1\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_cmp(self, op):\nflagtup = self.integerSubtraction(op)\n@@ -534,11 +540,11 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nval = self.getOperValue(op, 0)\nself.setOperValue(op, 1, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, ssize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, ssize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n- if isinstance(op.opers[1], H8RegDirOper) and op.opers[1].reg == REG_PC:\n+ if isinstance(op.opers[1], H8RegDirOper) and op.opers[1].reg == h8_const.REG_PC:\nreturn val\ndef i_add(self, op):\n@@ -547,11 +553,11 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, ures)\n# FIXME: test and validate\n- self.setFlag(CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))\n- self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))\n+ self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))\n+ self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))\ndef i_adds(self, op):\n(ssize, dsize, sres, ures, sdst, udst) = self.integerAddition(op)\n@@ -561,28 +567,28 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndef i_addx(self, op):\n(ssize, dsize, sres, ures, sdst, udst) = self.integerAddition(op)\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nsres += C\nures += C\nself.setOperValue(op, 1, ures)\n# FIXME: test and validate (same as i_add)\n- self.setFlag(CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))\n- self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))\n+ self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))\n+ self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))\ndef i_daa(self, op):\noper = self.getOperValue(op, 0)\nupop = oper >> 4 & 0xf\nloop = oper & 0xf\n- C = self.getFlag(CCR_C)\n- H = self.getFlag(CCR_H)\n+ C = self.getFlag(h8_regs.CCR_C)\n+ H = self.getFlag(h8_regs.CCR_H)\naddtup = bcd_add.get((C, H, upop, loop))\n- if addtup == None:\n+ if addtup is None:\nlogger.debug(\"DAA: %x %x %x %x - addtup is None\" % (C, H, upop, loop))\nreturn # FIXME: raise exception once figured out\naddval, resC = addtup\n@@ -590,19 +596,19 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 0, ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, 1))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_C, resC)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, 1))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_C, resC)\ndef i_das(self, op):\noper = self.getOperValue(op, 0)\nupop = oper >> 4 & 0xf\nloop = oper & 0xf\n- C = self.getFlag(CCR_C)\n- H = self.getFlag(CCR_H)\n+ C = self.getFlag(h8_regs.CCR_C)\n+ H = self.getFlag(h8_regs.CCR_H)\naddtup = bcd_sub.get((C, H, upop, loop))\n- if addtup == None:\n+ if addtup is None:\nlogger.debug(\"DAS: %x %x %x %x - addtup is None\" % (C, H, upop, loop))\nreturn # FIXME: raise exception once figured out\naddval, resC = addtup\n@@ -610,9 +616,9 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 0, ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, 1))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_C, resC) # this should always be what it was coming in\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, 1))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_C, resC) # this should always be what it was coming in\ndef i_inc(self, op):\ndstidx = len(op.opers) - 1\n@@ -623,7 +629,8 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndst = self.getOperValue(op, 1)\nudst = e_bits.unsigned(dst, dsize)\n- sdst = e_bits.signed(dst, dsize)\n+ # TODO: What is sdst and why does it exist?\n+ # sdst = e_bits.signed(dst, dsize)\nusrc = e_bits.unsigned(src, ssize)\nssrc = e_bits.signed(src, ssize)\n@@ -632,15 +639,15 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndst = self.getOperValue(op, 0)\nudst = e_bits.unsigned(dst, dsize)\n- sdst = e_bits.signed(dst, dsize)\n+ # sdst = e_bits.signed(dst, dsize)\nssrc = usrc = 1\nures = usrc + udst\nsres = ssrc + udst\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))\n# V must be set if previous value was 0x7f (per docs, page 78 of H8/300)\nself.setOperValue(op, dstidx, ures)\n@@ -669,9 +676,9 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nures = udst - usrc\nsres = sdst - ssrc\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))\n# V must be set if previous value was 0x80 (per docs, page 73 of H8/300)\nself.setOperValue(op, dstidx, ures)\n@@ -689,20 +696,21 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndef doFlags(self, flagtup):\n(ssize, dsize, sres, ures, sdst, udst) = flagtup\n- self.setFlag(CCR_H, e_bits.is_signed_half_carry(ures, dsize, udst))\n- self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))\n+ self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(ures, dsize, udst))\n+ self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))\ndef i_subs(self, op):\n# Src op gets sign extended to dst\nssize = op.opers[0].tsize\n- dsize = op.opers[1].tsize\n+ # TODO: Why?\n+ # dsize = op.opers[1].tsize\nsrc = e_bits.sign_extend(self.getOperValue(op, 0), ssize, self.ptrsz)\ndst = e_bits.sign_extend(self.getOperValue(op, 1), ssize, self.ptrsz)\n- if src == None or dst == None:\n+ if src is None or dst is None:\nself.undefFlags()\nreturn None\n@@ -715,9 +723,9 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndsize = op.opers[1].tsize\nsrc = e_bits.sign_extend(self.getOperValue(op, 0), ssize, self.ptrsz)\ndst = e_bits.sign_extend(self.getOperValue(op, 1), dsize, self.ptrsz)\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\n- if src == None or dst == None:\n+ if src is None or dst is None:\nself.undefFlags()\nreturn None\n@@ -729,7 +737,7 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nsrc2 = self.getOperValue(op, 1)\n# FIXME PDE and flags\n- if src1 == None or src2 == None:\n+ if src1 is None or src2 is None:\nself.undefFlags()\nself.setOperValue(op, 1, None)\nreturn\n@@ -741,23 +749,24 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, ures)\n- self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, 4))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, 4))\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(ures, 4))\n+ self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, 4))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, 4))\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(ures, 4))\ndef i_xorc(self, op):\nsrc = self.getOperValue(op, 0)\ndst = self.getStatusRegister()\n# FIXME PDE and flags\n- if src == None:\n+ if src is None:\nself.undefFlags()\nself.setOperValue(op, 1, None)\nreturn\n- ssize = op.opers[0].tsize\n- dsize = op.opers[1].tsize\n+ # TODO: WHY?\n+ # ssize = op.opers[0].tsize\n+ # dsize = op.opers[1].tsize\nures = src ^ dst\n@@ -777,8 +786,8 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, rdval)\n- self.setFlag(CCR_Z, not quotient)\n- self.setFlag(CCR_N, e_bits.is_signed(quotient, 4))\n+ self.setFlag(h8_regs.CCR_Z, not quotient)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(quotient, 4))\ndef i_divxs(self, op):\nssize = op.opers[0].tsize\n@@ -797,19 +806,19 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, 1, rdval)\n- self.setFlag(CCR_Z, not quotient)\n- self.setFlag(CCR_N, e_bits.is_signed(quotient, 4))\n+ self.setFlag(h8_regs.CCR_Z, not quotient)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(quotient, 4))\ndef i_eepmov(self, op):\n- if op.iflags & IF_W:\n+ if op.iflags & h8_const.IF_W:\ndelta = 2\ncount = self.getRegisterByName('r4')\n- elif op.iflags & IF_B:\n+ elif op.iflags & h8_const.IF_B:\ndelta = 1\ncount = self.getRegisterByName('r4l')\n- src = self.getRegister(REG_ER5)\n- dst = self.getRegister(REG_ER6)\n+ src = self.getRegister(h8_regs.REG_ER5)\n+ dst = self.getRegister(h8_regs.REG_ER6)\nlogger.info(\"WARNING: EEPMOV instruction executed... 0x%x -> 0x%x (count=0x%x)\" % (\nsrc, dst, count * delta))\n@@ -885,11 +894,11 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\noper = -oper\nself.setOperValue(op, 0, oper)\n- self.setFlag(CCR_H, e_bits.is_signed_half_carry(oper, dsize, oper))\n- self.setFlag(CCR_N, e_bits.is_signed(oper, dsize))\n- self.setFlag(CCR_Z, not oper)\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(oper, dsize))\n- self.setFlag(CCR_C, e_bits.is_unsigned_carry(oper, dsize))\n+ self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(oper, dsize, oper))\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(oper, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not oper)\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(oper, dsize))\n+ self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(oper, dsize))\ndef i_not(self, op):\ndsize = op.opers[0].tsize\n@@ -898,42 +907,44 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\noper = e_bits.u_maxes[dsize] - oper\nself.setOperValue(op, 0, oper)\n- self.setFlag(CCR_N, e_bits.is_signed(oper, dsize))\n- self.setFlag(CCR_Z, not oper)\n- self.setFlag(CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(oper, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not oper)\n+ self.setFlag(h8_regs.CCR_V, 0)\ndef i_or(self, op):\nsrc = self.getOperValue(op, 0)\ndst = self.getOperValue(op, 1)\n# FIXME PDE and flags\n- if src == None:\n+ if src is None:\nself.undefFlags()\nself.setOperValue(op, 0, None)\nreturn\n- ssize = op.opers[0].tsize\n+ # TODO: WHY?\n+ # ssize = op.opers[0].tsize\ndsize = op.opers[1].tsize\nures = src | dst\nself.setOperValue(op, 1, ures)\n- self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))\n- self.setFlag(CCR_Z, not ures)\n- self.setFlag(CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not ures)\n+ self.setFlag(h8_regs.CCR_V, 0)\ndef i_orc(self, op):\nsrc = self.getOperValue(op, 0)\ndst = self.getStatusRegister()\n# FIXME PDE and flags\n- if src == None:\n+ if src is None:\nself.undefFlags()\nself.setOperValue(op, 0, None)\nreturn\n- ssize = op.opers[0].tsize\n- dsize = op.opers[1].tsize\n+ # TODO: WHY?\n+ # ssize = op.opers[0].tsize\n+ # dsize = op.opers[1].tsize\nures = src | dst\n@@ -944,18 +955,18 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nval = self.doPop()\nself.setOperValue(op, 0, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\ndef i_push(self, op):\ndsize = op.opers[0].tsize\nval = self.getOperValue(op, 0)\nself.doPush(val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\ndef i_rotl(self, op):\ndstidx = len(op.opers) - 1\n@@ -976,10 +987,10 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_rotr(self, op):\ndstidx = len(op.opers) - 1\n@@ -994,16 +1005,16 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nbits = (dsize * 8)\nC = (val >> (shbits - 1)) & 1\n- val |= (val<<(bits))\n+ val |= (val << bits)\nval >>= shbits\nval &= e_bits.u_maxes[dsize]\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_rotxl(self, op):\n'''\n@@ -1021,7 +1032,7 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nbits = (dsize * 8) - 1\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nnewC = (val >> (bits+1-shbits)) & 1\nval <<= shbits\nval |= (val >> (bits + 2))\n@@ -1030,10 +1041,10 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, newC)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, newC)\ndef i_rotxr(self, op):\ndstidx = len(op.opers) - 1\n@@ -1047,7 +1058,7 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndsize = op.opers[0].tsize\nbits = (dsize * 8)\n- C = self.getFlag(CCR_C)\n+ C = self.getFlag(h8_regs.CCR_C)\nnewC = (val >> (shbits-1)) & 1\nval |= (val << (bits + 1))\nval |= (C << bits)\n@@ -1056,10 +1067,10 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, newC)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, newC)\ndef i_rte(self, op):\n'''\n@@ -1112,10 +1123,10 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, e_bits.is_signed_overflow(rawval, dsize))\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(rawval, dsize))\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_shar(self, op):\ndstidx = len(op.opers) - 1\n@@ -1141,10 +1152,10 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_shll(self, op):\n'''\n@@ -1168,10 +1179,10 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_shlr(self, op):\n'''\n@@ -1187,17 +1198,17 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\nval = self.getOperValue(op, 0)\ndsize = op.opers[0].tsize\n- bits = (dsize * 8) - 1\n+ # bits = (dsize * 8) - 1\nC = (val >> (shbits-1)) & 1\nval >>= shbits\nself.setOperValue(op, dstidx, val)\n- self.setFlag(CCR_N, e_bits.is_signed(val, dsize))\n- self.setFlag(CCR_Z, not val)\n- self.setFlag(CCR_V, 0)\n- self.setFlag(CCR_C, C)\n+ self.setFlag(h8_regs.CCR_N, e_bits.is_signed(val, dsize))\n+ self.setFlag(h8_regs.CCR_Z, not val)\n+ self.setFlag(h8_regs.CCR_V, 0)\n+ self.setFlag(h8_regs.CCR_C, C)\ndef i_sleep(self, op):\nlogger.info(\"Entering Sleep Mode... waiting for an External Interrupt\")\n@@ -1223,4 +1234,3 @@ class H8Emulator(H8Module, H8RegisterContext, envi.Emulator):\ndef i_trapa(self, op):\nlogger.info(\"SW EXCEPTION: %s\" % op)\n# FIXME: processInterrupt()\n-\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/h8.py",
"new_path": "vivisect/impemu/platarch/h8.py",
"diff": "import envi.archs.h8 as e_h8\nimport envi.archs.h8.emu as h8_emu\n+import envi.archs.h8.regs as h8_regs\nimport vivisect.impemu.emulator as v_i_emulator\nclass H8WorkspaceEmulator(v_i_emulator.WorkspaceEmulator, h8_emu.H8Emulator):\n- taintregs = [e_h8.REG_ER0, e_h8.REG_ER1, e_h8.REG_ER2]\n+ taintregs = [h8_regs.REG_ER0, h8_regs.REG_ER1, h8_regs.REG_ER2]\ndef __init__(self, vw, logwrite=False, logread=False):\ne_h8.H8Emulator.__init__(self)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
it runs at least
|
718,770 |
27.02.2019 08:54:24
| 18,000 |
7a4633baec5c949f356a45fa15b6d94a400f9adf
|
bugfix: lsls/mov thumb decoding
otherwise, mostly cosmetic logging improvements
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -681,7 +681,7 @@ def p_dp_reg_shift(opval, va):\niflags = 0\nreturn (opcode, mnem, olist, iflags, 0)\n-multfail = (None, None, None,)\n+multfail = (None, None, None, None)\niencmul_r15_codes = {\n# Basic multiplication opcodes\n@@ -1176,7 +1176,7 @@ def p_media_pack_sat_rev_extend(opval, va):\nmnem, opcode = xtnd_mnem[idx]\nelse:\nraise envi.InvalidInstruction(\n- mesg=\"p_media_extend: invalid instruction\"+opc1+\".\"+opc2,\n+ mesg=\"p_media_extend: invalid instruction %r.%r\" % (opc1, opc2),\nbytez=struct.pack(\"<I\", opval), va=va)\nreturn (opcode, mnem, olist, 0, 0)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -794,7 +794,7 @@ sxt_mnem_2 = (\ndef shift_or_ext_32(va, val1, val2):\nif (val2 & 0xf000) != 0xf000:\n- raise InvalidInstruction(mesg=\"shift_or_ext_32 needs to hand off for val2 & 0xf000 != 0xf000 at va 0x%x: val1:%.4x val2:%.4x\" % (va, val1, val2), va=va)\n+ raise InvalidInstruction(mesg=\"UNDEFINED: shift_or_ext_32: val2 & 0xf000 != 0xf000 at va 0x%x: val1:%.4x val2:%.4x\" % (va, val1, val2), va=va)\nop1 = (val1>>4) & 0xf\n@@ -1290,8 +1290,8 @@ def ldrd_imm_32(va, val1, val2):\ndef strexn_32(va, val1, val2):\nop3 = (val1 >> 4) & 0xf\nif (op3 & 0xc != 0x10):\n- bytez = struct.pack(\"<HH\", val1, val2)\n- raise InvalidInstruction(bytez=bytez, va=va)\n+ raise InvalidInstruction(mesg=\"strexn_32 failure\",\n+ bytez=struct.pack(\"<HH\", val, val2), va=va-4)\ntsize = op3 & 4\nmnem = ('strexb', 'strexh', None, 'strexd')[tsize]\n@@ -1380,13 +1380,13 @@ def smull_32(va, val1, val2):\nif secondary == None:\nraise envi.InvalidInstruction( #FIXME!!!!\nmesg=\"smull invalid decode: op1\",\n- bytez=bytez[offset:offset+4], va=va)\n+ bytez=struct.pack(\"<HH\", val, val2), va=va-4)\nsecout = secondary.get(op2)\nif secout == None:\nraise envi.InvalidInstruction( #FIXME!!!!\nmesg=\"smull invalid decode: op2\",\n- bytez=bytez[offset:offset+4], va=va)\n+ bytez=struct.pack(\"<HH\", val, val2), va=va-4)\nopers = (\nArmRegOper(rdhi, va=va),\n@@ -1575,7 +1575,7 @@ def coproc_simd_32(va, val1, val2):\nbytez = struct.pack(\"<HH\", val1, val2)\nraise envi.InvalidInstruction(\nmesg=\"CoprocSIMD: UNDEFINED instructions\",\n- bytez=bytez, va=va)\n+ bytez=struct.pack(\"<HH\", val, val2), va=va-4)\nif coproc & 0b1110 != 0b1010: # apparently coproc 10 and 11 are not allowed...\nif op1 == 0b000100:\n@@ -1933,7 +1933,12 @@ bcc_ops = {\n# FIXME: thumb and arm opcode numbers don't line up. - FIX\nthumb_base = [\n- ('00000', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n+ ('0000000001', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n+ ('0000000000', ( INS_MOV,'mov', rm_rd, IF_PSR_S)), # MOVS<c> <Rd>,<Rm>\n+ ('000000001', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n+ ('00000001', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n+ ('0000001', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n+ ('000001', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n('00001', ( INS_LSR,'lsr', imm5_rm_rd, IF_PSR_S)), # LSR<c> <Rd>,<Rm>,#<imm>\n('00010', ( INS_ASR,'asr', imm5_rm_rd, IF_PSR_S)), # ASR<c> <Rd>,<Rm>,#<imm>\n('0001100', ( INS_ADD,'add', rm_rn_rd, IF_PSR_S)), # ADD<c> <Rd>,<Rn>,<Rm>\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: lsls/mov thumb decoding
otherwise, mostly cosmetic logging improvements
|
718,770 |
27.02.2019 14:39:49
| 18,000 |
f7cca0f90cb5b357fca6a5c644807b9e9df0fee1
|
improvements in ordering, ARM reloc coverage, and logging.
|
[
{
"change_type": "MODIFY",
"old_path": "Elf/__init__.py",
"new_path": "Elf/__init__.py",
"diff": "@@ -598,7 +598,10 @@ class Elf(vs_elf.Elf32, vs_elf.Elf64):\nreturn self.e_type == ET_EXEC\ndef __repr__(self, verbose=False):\n- \"\"\" Returns a string summary of this ELF. If (verbose) the summary will include Symbols, Relocs, Dynamics and Dynamic Symbol tables\"\"\"\n+ \"\"\"\n+ Returns a string summary of this ELF.\n+ If (verbose) the summary will include Symbols, Relocs, Dynamics and Dynamic Symbol tables\n+ \"\"\"\nmystr = 'Elf Binary:'\nmystr+= \"\\n= Intimate Details:\"\nmystr+= \"\\n==Magic:\\t\\t\\t\\t\" + self.e_ident\n"
},
{
"change_type": "MODIFY",
"old_path": "Elf/elf_lookup.py",
"new_path": "Elf/elf_lookup.py",
"diff": "@@ -655,6 +655,7 @@ DT_HIOS = 0x6ffff000\nDT_LOPROC = 0x70000000\nDT_HIPROC = 0x7fffffff\n#DT_PROCNUM = DT_MIPS_NUM\n+dt_names = { v:k for k,v in globals().items() if k.startswith('DT_')}\ndt_types = {\nDT_NULL : \"Marks end of dynamic section \",\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -3,6 +3,7 @@ import struct\nimport logging\nimport Elf\n+import envi\nimport vivisect\nimport vivisect.parsers as v_parsers\nimport envi.bits as e_bits\n@@ -13,6 +14,9 @@ from cStringIO import StringIO\nlogger = logging.getLogger(__name__)\n+# FIXME: TODO: Reorder, so that Dynamics Data is applied first... with optional ELF Section data afterwards (default to apply if not already there)\n+# FIXME: we're causing Functions and Code to happen... *before* any analysis modules are put into place.\n+\ndef parseFile(vw, filename, baseaddr=None):\nfd = file(filename, 'rb')\nelf = Elf.Elf(fd)\n@@ -44,7 +48,7 @@ def makeStringTable(vw, va, maxva):\nl = vw.makeString(va)\nva += l[vivisect.L_SIZE]\nexcept Exception, e:\n- print \"makeStringTable\",e\n+ logger.warn(\"makeStringTable\\t%r\",e)\nreturn\ndef makeSymbolTable(vw, va, maxva):\n@@ -91,6 +95,10 @@ archcalls = {\n}\ndef loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\n+ # analysis of discovered functions and data locations should be stored until the end of loading\n+ data_ptrs = []\n+ new_pointers = []\n+ new_functions = []\narch = arch_names.get(elf.e_machine)\nif arch is None:\n@@ -202,7 +210,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nelif sname == \".init\":\nvw.makeName(sva, \"init_function\", filelocal=True)\n- vw.addEntryPoint(sva)\n+ new_functions.append((\"init_function\", sva))\nelif sname == \".init_array\":\n# handle pseudo-fixups first: these pointers require base-addresses\n@@ -217,15 +225,15 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n- vw.makePointer(sh_addr + off, addr)\n+ new_pointers.append((sh_addr + off, addr))\nvw.makeName(addr, \"init_function_%d\" % ptr_count, filelocal=True)\nvw.addXref(sh_addr + off, addr, REF_PTR)\n- vw.addEntryPoint(addr)\n+ new_functions.append((\"init_function\", addr))\nptr_count += 1\nelif sname == \".fini\":\nvw.makeName(sva, \"fini_function\", filelocal=True)\n- vw.addEntryPoint(sva)\n+ new_functions.append((\"fini_function\", sva))\nelif sname == \".fini_array\":\n# handle pseudo-fixups first: these pointers require base-addresses\n@@ -240,10 +248,10 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\naddr, = struct.unpack_from(pfmt, secbytes, off)\nif addbase: addr += baseaddr\n- vw.makePointer(sh_addr + off, addr)\n+ new_pointers.append((sh_addr + off, addr))\nvw.makeName(addr, \"fini_function_%d\" % ptr_count, filelocal=True)\nvw.addXref(sec.sh_addr + off, addr, REF_PTR)\n- vw.addEntryPoint(addr)\n+ new_functions.append((\"fini_array entry\", addr))\nptr_count += 1\nelif sname == \".dynamic\": # Imports\n@@ -254,7 +262,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nmakeStringTable(vw, sva, sva+size)\nelif sname == \".dynsym\":\n- #print \"LINK\",sec.sh_link\n+ logger.debug(\"LINK\\t%r\",sec.sh_link)\nfor s in makeSymbolTable(vw, sva, sva+size):\npass\n#print \"########################.dynsym\",s\n@@ -272,7 +280,17 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nif sec.sh_flags & Elf.SHF_STRINGS:\nmakeStringTable(vw, sva, sva+size)\n+ # get \"Dynamics\" based items, like NEEDED libraries (dependencies)\n+ for d in elf.getDynamics():\n+ if d.d_tag == Elf.DT_NEEDED:\n+ name = d.getName()\n+ name = name.split('.')[0].lower()\n+ vw.addLibraryDependancy(name)\n+ else:\n+ logger.debug(\"DYNAMIC DYNAMIC DYNAMIC\\t%r\",d)\n+\n# Let pyelf do all the stupid string parsing...\n+ dsyms = elf.getDynSyms()\nrelocs = elf.getRelocs()\nfor r in relocs:\nrtype = Elf.getRelocType(r.r_info)\n@@ -298,28 +316,82 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nvw.setComment(rlva, dmglname)\nelse:\n- vw.verbprint('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n+ logging.info('unknown reloc type: %d %s (at %s)', rtype, name, hex(rlva))\nif arch in ('arm', 'thumb', 'thumb16'):\n- if rtype in (Elf.R_ARM_JUMP_SLOT, Elf.R_ARM_GLOB_DAT):\n+ if rtype == Elf.R_ARM_JUMP_SLOT:\n+ symidx = Elf.getRelocSymTabIndex(r.r_info)\n+ sym = dsyms[symidx]\n+\n+ ptr = sym.st_value\n+\n+ #quick check to make sure we don't provide this symbol\n+ if ptr:\n+ logger.info('R_ARM_JUMP_SLOT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ pname = \"ptr_%s\" % name\n+ if vw.vaByName(pname) == None:\n+ vw.makeName(rlva, pname)\n+\n+ if addbase: ptr += baseaddr\n+ vw.makeName(ptr, name)\n+ vw.setComment(ptr, dmglname)\n+ else:\n+ logger.info('R_ARM_JUMP_SLOT: adding Import 0x%x (%s) ', rlva, dmglname)\nvw.makeImport(rlva, \"*\", name)\n- vw.setComment(sva, dmglname)\n+ vw.setComment(rlva, dmglname)\n+\n+ elif rtype == Elf.R_ARM_GLOB_DAT:\n+ symidx = Elf.getRelocSymTabIndex(r.r_info)\n+ sym = dsyms[symidx]\n+ ptr = sym.st_value\n+\n+ #quick check to make sure we don't provide this symbol\n+ if ptr:\n+ logger.info('R_ARM_GLOB_DAT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ pname = \"ptr_%s\" % name\n+ if vw.vaByName(pname) == None:\n+ vw.makeName(rlva, pname)\n+\n+ if addbase: ptr += baseaddr\n+ vw.makeName(ptr, name)\n+ vw.setComment(ptr, dmglname)\n+ else:\n+ logger.info('R_ARM_GLOB_DAT: adding Import 0x%x (%s) ', rlva, dmglname)\n+ vw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\nelif rtype == Elf.R_ARM_ABS32:\n+ symidx = Elf.getRelocSymTabIndex(r.r_info)\n+ sym = dsyms[symidx]\n+ ptr = sym.st_value\n+\n+ if ptr:\n+ logger.info('R_ARM_ABS32: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ else:\n+ logger.info('R_ARM_ABS32: adding Import 0x%x (%s) ', rlva, dmglname)\nvw.makeImport(rlva, \"*\", name)\n- vw.setComment(sva, dmglname)\n+\n+ vw.setComment(rlva, dmglname)\nelif rtype == Elf.R_ARM_RELATIVE: # Adjust locations for the rebasing\n- vw.addRelocation(rlva, vivisect.RTYPE_BASERELOC)\n+ ptr = vw.readMemoryPtr(rlva)\n+ logger.info('R_ARM_RELATIVE: adding Relocation 0x%x -> 0x%x (name: %s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ if len(name):\n+ vw.makeName(rlva, name, makeuniq=True)\nvw.setComment(rlva, dmglname)\nelse:\n- vw.verbprint('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n+ logger.warn('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\nexcept vivisect.InvalidLocation, e:\n- print \"NOTE\",e\n+ logger.warn(\"NOTE\\t%r\",e)\n+ # process Dynamic Symbols\nfor s in elf.getDynSyms():\nstype = s.getInfoType()\nsva = s.st_value\n@@ -335,7 +407,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nif stype == Elf.STT_FUNC or (stype == Elf.STT_GNU_IFUNC and arch in ('i386','amd64')): # HACK: linux is what we're really after.\ntry:\n- vw.addEntryPoint(sva)\n+ new_functions.append((\"DynSym: STT_FUNC\", sva))\nvw.addExport(sva, EXP_FUNCTION, s.name, fname)\nvw.setComment(sva, dmglname)\nexcept Exception, e:\n@@ -356,15 +428,13 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\ntry:\n- vw.addEntryPoint(sva)\n+ new_functions.append((\"DynSym: STT_HIOS\", sva))\nvw.addExport(sva, EXP_FUNCTION, s.name, fname)\nvw.setComment(sva, dmglname)\nexcept Exception, e:\nvw.vprint('WARNING: %s' % e)\nelif stype == 14:# OMG WTF FUCK ALL THIS NONSENSE! FIXME\n- # So aparently Elf64 binaries on amd64 use HIOS and then\n- # s.st_other cause that's what all the kewl kids are doing...\nsva = s.st_other\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva):\n@@ -375,17 +445,7 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nvw.vprint('WARNING: %s' % e)\nelse:\n- pass\n- #print \"DYNSYM DYNSYM\",repr(s),s.getInfoType(),'other',hex(s.st_other)\n-\n- for d in elf.getDynamics():\n- if d.d_tag == Elf.DT_NEEDED:\n- name = d.getName()\n- name = name.split('.')[0].lower()\n- vw.addLibraryDependancy(name)\n- else:\n- pass\n- #print \"DYNAMIC DYNAMIC DYNAMIC\",d\n+ logger.debug(\"DYNSYM DYNSYM\\t%r\\t%r\\t%r\\t%r\",s,s.getInfoType(),'other',hex(s.st_other))\nvw.addVaSet(\"FileSymbols\", ((\"Name\",VASET_STRING),(\"va\",VASET_ADDRESS)))\nvw.addVaSet(\"WeakSymbols\", ((\"Name\",VASET_STRING),(\"va\",VASET_ADDRESS)))\n@@ -406,12 +466,28 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\ncontinue\nif s.st_info == Elf.STT_NOTYPE:\n- logger.info('skipping NOTYPE symbol: 0x%x: %r',sva, s.name)\n- continue\n+ # mapping symbol\n+ if arch in ('arm', 'thumb', 'thumb16'):\n+ symname = s.getName()\n+ if addbase: sva += baseaddr\n+ if symname == '$a':\n+ # ARM code\n+ logger.info('mapping (NOTYPE) ARM symbol: 0x%x: %r',sva, s.name)\n+ #vw.makeCode(sva)\n+ new_functions.append((\"Mapping Symbol: $a\", sva))\n+\n+ elif symname == '$t':\n+ # Thumb code\n+ logger.info('mapping (NOTYPE) Thumb symbol: 0x%x: %r',sva, s.name)\n+ #vw.makeCode(sva)\n+ new_functions.append((\"Mapping Symbol: $t\", sva + 1))\n+\n+ elif symname == '$d':\n+ # Data Items (eg. literal pool)\n+ logger.info('mapping (NOTYPE) data symbol: 0x%x: %r',sva, s.name)\n+ #vw.followPointer(sva)\n+ data_ptrs.append(sva)\n- if sva in impvas or sva in expvas:\n- logginer.debug('skipping Symbol naming for existing Import/Export: 0x%x (%r)', sva, s.name)\n- continue\n# if the symbol has a value of 0, it is likely a relocation point which gets updated\nsname = normName(s.name)\n@@ -425,6 +501,8 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\ndmglname = demangle(sname)\n+ # TODO: make use of _ZTSN (typeinfo) and _ZTVN (vtable) entries if name demangles cleanly\n+\nif addbase: sva += baseaddr\nif vw.isValidPointer(sva) and len(dmglname):\ntry:\n@@ -433,12 +511,18 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nvw.setVaSetRow('WeakSymbols', (sname, sva))\ndmglname = '__weak_' + dmglname\n+ if sva in impvas or sva in expvas:\n+ imps = [imp for imp in vw.getImports() if imp[0] == sva]\n+ exps = [exp for exp in vw.getExports() if exp[0] == sva]\n+ logger.debug('skipping Symbol naming for existing Import/Export: 0x%x (%r) (%r) (%r)', sva, s.name, imps, exps)\n+ else:\nvw.makeName(sva, dmglname, filelocal=True, makeuniq=True)\n+\nexcept Exception, e:\n- print \"WARNING:\",e\n+ logger.warn(\"WARNING:\\t%r\",e)\nif s.st_info == Elf.STT_FUNC:\n- vw.addEntryPoint(sva)\n+ new_functions.append((\"STT_FUNC\", sva))\nif addbase:\neentry = baseaddr + elf.e_entry\n@@ -447,11 +531,19 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nif vw.isValidPointer(eentry):\nvw.addExport(eentry, EXP_FUNCTION, '__entry', fname)\n- vw.addEntryPoint(eentry)\n+ new_functions.append((\"ELF Entry\", eentry))\nif vw.isValidPointer(baseaddr):\nvw.makeStructure(baseaddr, \"elf.Elf32\")\n+ # do we add data_ptrs here? ideally they would be marked out, but analyzed after all other analysis...\n+ # for now, ignore them.\n+ for cmnt, fva in new_functions:\n+ logger.info('adding function from ELF metadata: 0x%x (%s)', fva, cmnt)\n+ vw.makeFunction(fva)\n+\n+ for va, tva in new_pointers:\n+ logger.info('adding pointer 0x%x -> 0x%x', va, tva)\nreturn fname\ndef normName(name):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
improvements in ordering, ARM reloc coverage, and logging.
|
718,770 |
27.02.2019 14:52:38
| 18,000 |
2d5eec0aae767c95e6b19ba03ac3f0b489e0d097
|
reordering and breaking out Relocation processing into a function. might do with other components of loadElfIntoWorkspace()
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -289,108 +289,6 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nelse:\nlogger.debug(\"DYNAMIC DYNAMIC DYNAMIC\\t%r\",d)\n- # Let pyelf do all the stupid string parsing...\n- dsyms = elf.getDynSyms()\n- relocs = elf.getRelocs()\n- for r in relocs:\n- rtype = Elf.getRelocType(r.r_info)\n- rlva = r.r_offset\n- if addbase: rlva += baseaddr\n- try:\n- # If it has a name, it's an externally\n- # resolved \"import\" entry, otherwise, just a regular reloc\n- name = r.getName()\n- dmglname = demangle(name)\n- logger.debug('relocs: 0x%x: %r', rlva, name)\n- if arch in ('i386','amd64'):\n- if name:\n- if rtype == Elf.R_386_JMP_SLOT:\n- vw.makeImport(rlva, \"*\", name)\n- vw.setComment(rlva, dmglname)\n-\n- elif rtype == Elf.R_386_32:\n- pass\n-\n- elif rtype == Elf.R_X86_64_GLOB_DAT: # Elf.R_386_GLOB_DAT is same number\n- vw.makeImport(rlva, \"*\", name)\n- vw.setComment(rlva, dmglname)\n-\n- else:\n- logging.info('unknown reloc type: %d %s (at %s)', rtype, name, hex(rlva))\n-\n-\n- if arch in ('arm', 'thumb', 'thumb16'):\n- if rtype == Elf.R_ARM_JUMP_SLOT:\n- symidx = Elf.getRelocSymTabIndex(r.r_info)\n- sym = dsyms[symidx]\n-\n- ptr = sym.st_value\n-\n- #quick check to make sure we don't provide this symbol\n- if ptr:\n- logger.info('R_ARM_JUMP_SLOT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n- vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n- pname = \"ptr_%s\" % name\n- if vw.vaByName(pname) == None:\n- vw.makeName(rlva, pname)\n-\n- if addbase: ptr += baseaddr\n- vw.makeName(ptr, name)\n- vw.setComment(ptr, dmglname)\n- else:\n- logger.info('R_ARM_JUMP_SLOT: adding Import 0x%x (%s) ', rlva, dmglname)\n- vw.makeImport(rlva, \"*\", name)\n- vw.setComment(rlva, dmglname)\n-\n- elif rtype == Elf.R_ARM_GLOB_DAT:\n- symidx = Elf.getRelocSymTabIndex(r.r_info)\n- sym = dsyms[symidx]\n- ptr = sym.st_value\n-\n- #quick check to make sure we don't provide this symbol\n- if ptr:\n- logger.info('R_ARM_GLOB_DAT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n- vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n- pname = \"ptr_%s\" % name\n- if vw.vaByName(pname) == None:\n- vw.makeName(rlva, pname)\n-\n- if addbase: ptr += baseaddr\n- vw.makeName(ptr, name)\n- vw.setComment(ptr, dmglname)\n- else:\n- logger.info('R_ARM_GLOB_DAT: adding Import 0x%x (%s) ', rlva, dmglname)\n- vw.makeImport(rlva, \"*\", name)\n- vw.setComment(rlva, dmglname)\n-\n- elif rtype == Elf.R_ARM_ABS32:\n- symidx = Elf.getRelocSymTabIndex(r.r_info)\n- sym = dsyms[symidx]\n- ptr = sym.st_value\n-\n- if ptr:\n- logger.info('R_ARM_ABS32: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n- vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n- else:\n- logger.info('R_ARM_ABS32: adding Import 0x%x (%s) ', rlva, dmglname)\n- vw.makeImport(rlva, \"*\", name)\n-\n- vw.setComment(rlva, dmglname)\n-\n- elif rtype == Elf.R_ARM_RELATIVE: # Adjust locations for the rebasing\n- ptr = vw.readMemoryPtr(rlva)\n- logger.info('R_ARM_RELATIVE: adding Relocation 0x%x -> 0x%x (name: %s) ', rlva, ptr, dmglname)\n- vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n- if len(name):\n- vw.makeName(rlva, name, makeuniq=True)\n- vw.setComment(rlva, dmglname)\n-\n- else:\n- logger.warn('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n-\n- except vivisect.InvalidLocation, e:\n- logger.warn(\"NOTE\\t%r\",e)\n-\n# process Dynamic Symbols\nfor s in elf.getDynSyms():\nstype = s.getInfoType()\n@@ -447,10 +345,14 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nelse:\nlogger.debug(\"DYNSYM DYNSYM\\t%r\\t%r\\t%r\\t%r\",s,s.getInfoType(),'other',hex(s.st_other))\n+ # Let pyelf do all the stupid string parsing...\n+ applyRelocs(elf, vw, addbase, baseaddr)\n+\nvw.addVaSet(\"FileSymbols\", ((\"Name\",VASET_STRING),(\"va\",VASET_ADDRESS)))\nvw.addVaSet(\"WeakSymbols\", ((\"Name\",VASET_STRING),(\"va\",VASET_ADDRESS)))\n# apply symbols to workspace (if any)\n+ relocs = elf.getRelocs()\nimpvas = [va for va,x,y,z in vw.getImports()]\nexpvas = [va for va,x,y,z in vw.getExports()]\nfor s in elf.getSymbols():\n@@ -546,6 +448,116 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nlogger.info('adding pointer 0x%x -> 0x%x', va, tva)\nreturn fname\n+def applyRelocs(elf, vw, addbase=False, baseaddr=0):\n+ # process relocations / strings (relocs use Dynamic Symbols)\n+ arch = arch_names.get(elf.e_machine)\n+ dsyms = elf.getDynSyms()\n+ relocs = elf.getRelocs()\n+ for r in relocs:\n+ rtype = Elf.getRelocType(r.r_info)\n+ rlva = r.r_offset\n+ if addbase: rlva += baseaddr\n+ try:\n+ # If it has a name, it's an externally\n+ # resolved \"import\" entry, otherwise, just a regular reloc\n+ name = r.getName()\n+ dmglname = demangle(name)\n+ logger.debug('relocs: 0x%x: %r', rlva, name)\n+ if arch in ('i386','amd64'):\n+ if name:\n+ if rtype == Elf.R_386_JMP_SLOT:\n+ vw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\n+\n+ elif rtype == Elf.R_386_32:\n+ pass\n+\n+ elif rtype == Elf.R_X86_64_GLOB_DAT: # Elf.R_386_GLOB_DAT is same number\n+ vw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\n+\n+ else:\n+ logger.info('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n+\n+\n+ if arch in ('arm', 'thumb', 'thumb16'):\n+ if rtype == Elf.R_ARM_JUMP_SLOT:\n+ symidx = Elf.getRelocSymTabIndex(r.r_info)\n+ sym = dsyms[symidx]\n+ ptr = sym.st_value\n+\n+ #quick check to make sure we don't provide this symbol\n+ if ptr:\n+ logger.info('R_ARM_JUMP_SLOT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ pname = \"ptr_%s\" % name\n+ if vw.vaByName(pname) == None:\n+ vw.makeName(rlva, pname)\n+\n+ if addbase: ptr += baseaddr\n+ vw.makeName(ptr, name)\n+ vw.setComment(ptr, dmglname)\n+ else:\n+ logger.info('R_ARM_JUMP_SLOT: adding Import 0x%x (%s) ', rlva, dmglname)\n+ vw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\n+\n+ elif rtype == Elf.R_ARM_GLOB_DAT:\n+ symidx = Elf.getRelocSymTabIndex(r.r_info)\n+ sym = dsyms[symidx]\n+ ptr = sym.st_value\n+\n+ #quick check to make sure we don't provide this symbol\n+ if ptr:\n+ logger.info('R_ARM_GLOB_DAT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ pname = \"ptr_%s\" % name\n+ if vw.vaByName(pname) == None:\n+ vw.makeName(rlva, pname)\n+\n+ if addbase: ptr += baseaddr\n+ vw.makeName(ptr, name)\n+ vw.setComment(ptr, dmglname)\n+ else:\n+ logger.info('R_ARM_GLOB_DAT: adding Import 0x%x (%s) ', rlva, dmglname)\n+ vw.makeImport(rlva, \"*\", name)\n+ vw.setComment(rlva, dmglname)\n+\n+ elif rtype == Elf.R_ARM_ABS32:\n+ symidx = Elf.getRelocSymTabIndex(r.r_info)\n+ sym = dsyms[symidx]\n+ ptr = sym.st_value\n+\n+ if ptr:\n+ logger.info('R_ARM_ABS32: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ else:\n+ logger.info('R_ARM_ABS32: adding Import 0x%x (%s) ', rlva, dmglname)\n+ vw.makeImport(rlva, \"*\", name)\n+\n+ vw.setComment(rlva, dmglname)\n+\n+ elif rtype == Elf.R_ARM_RELATIVE: # Adjust locations for the rebasing\n+ ptr = vw.readMemoryPtr(rlva)\n+ logger.info('R_ARM_RELATIVE: adding Relocation 0x%x -> 0x%x (name: %s) ', rlva, ptr, dmglname)\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASEOFF, ptr)\n+ if len(name):\n+ vw.makeName(rlva, name, makeuniq=True)\n+ vw.setComment(rlva, dmglname)\n+\n+ else:\n+ logger.warn('unknown reloc type: %d %s (at %s)' % (rtype, name, hex(rlva)))\n+\n+ except vivisect.InvalidLocation, e:\n+ logger.warn(\"NOTE\\t%r\",e)\n+\n+def connectSymbols(vw):\n+ for lva,lsize,ltype,linfo in vw.getImports():\n+ for va, etype, name, filename in vw.getExports():\n+ pass\n+\n+\n+\ndef normName(name):\n'''\nNormalize symbol names. ie. drop the @@GOBBLEDEGOOK from the end\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
reordering and breaking out Relocation processing into a function. might do with other components of loadElfIntoWorkspace()
|
718,770 |
27.02.2019 15:47:29
| 18,000 |
81f0a81d36cd5177ca8bfefddf2dbb4948321b23
|
want the debug message.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -253,7 +253,7 @@ class VivWorkspaceCore(object,viv_impapi.ImportApi):\nwith self.getAdminRights():\nself.writeMemoryPtr(rva, ptr)\n- #logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\n+ logger.info('_handleADDRELOC: %x -> %x (map: 0x%x)', rva, ptr, imgbase)\ndef _handleADDMODULE(self, einfo):\nprint('DEPRICATED (ADDMODULE) ignored: %s' % einfo)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
want the debug message.
|
718,770 |
27.02.2019 15:52:54
| 18,000 |
8bb375269772dac92e0253147c13bf4e5117cc7a
|
bugfix and log fix
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -15,7 +15,7 @@ import logging\nlogger = logging.getLogger(__name__)\n# Pre-initialize a default stack size\n-init_stack_size = 0x7fff\n+init_stack_size = 0x8000\ninit_stack_map = b'\\xfe' * init_stack_size\ndef imphook(impname):\n@@ -374,7 +374,7 @@ class WorkspaceEmulator:\nexcept envi.UnsupportedInstruction, e:\nif self.strictops:\n- logger.debug(\"STRICTOPS: BREAK!\")\n+ logger.debug('runFunction failed: unsupported instruction: 0x%08x %s', e.op.va, e.op.mnem)\nbreak\nelse:\nlogger.debug('runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix and log fix
|
718,765 |
13.03.2019 23:53:46
| 14,400 |
3e19a7ba218f2f8a5a846df62122a7188ebab020
|
Fix pyasn1 compat issue for getting cert info. Add basic stab at requirements.txt
|
[
{
"change_type": "MODIFY",
"old_path": "PE/__init__.py",
"new_path": "PE/__init__.py",
"diff": "@@ -1033,7 +1033,7 @@ class PE(object):\ncbytes = pyasn1.codec.der.encoder.encode( i['certificate'] )\niparts = []\n- for rdnsequence in i[\"certificate\"][\"tbsCertificate\"][\"issuer\"]:\n+ for _, rdnsequence in i[\"certificate\"][\"tbsCertificate\"][\"issuer\"].items():\nfor rdn in rdnsequence:\nrtype = rdn[0][\"type\"]\nrvalue = rdn[0][\"value\"][2:]\n@@ -1042,7 +1042,7 @@ class PE(object):\nissuer = ','.join( iparts )\nsparts = []\n- for rdnsequence in i[\"certificate\"][\"tbsCertificate\"][\"subject\"]:\n+ for _, rdnsequence in i[\"certificate\"][\"tbsCertificate\"][\"subject\"].items():\nfor rdn in rdnsequence:\nrtype = rdn[0][\"type\"]\nrvalue = rdn[0][\"value\"][2:]\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "requirements.txt",
"diff": "+pyasn1=0.4.5\n+pyans1-modules=0.2.4\n+cxxfilter\n+msgpack\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Fix pyasn1 compat issue for getting cert info. Add basic stab at requirements.txt
|
718,765 |
18.03.2019 12:44:23
| 14,400 |
f27c01f73addc65ac37a25d2feea8f9057cc73c9
|
Bring more things into Imperial Compliance
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/h8/parsers.py",
"new_path": "envi/archs/h8/parsers.py",
"diff": "@@ -206,7 +206,7 @@ def p_Rd(va, val, buf, off, tsize):\nRd = val & 0xf\nopers = (\n- H8RegDirOper(Rd, tsize, va, 0),\n+ h8_operands.H8RegDirOper(Rd, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -219,8 +219,8 @@ def p_Rs_Rd(va, val, buf, off, tsize):\nRd = val & 0xf\nopers = (\n- H8RegDirOper(Rs, tsize, va, 0),\n- H8RegDirOper(Rd, tsize, va, 0),\n+ h8_operands.H8RegDirOper(Rs, tsize, va, 0),\n+ h8_operands.H8RegDirOper(Rd, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -232,8 +232,8 @@ def p_Rs_Rd_mul(va, val, buf, off, tsize):\nRd = val & 0xf\nopers = (\n- H8RegDirOper(Rs, 1, va, 0),\n- H8RegDirOper(Rd, 2, va, 0),\n+ h8_operands.H8RegDirOper(Rs, 1, va, 0),\n+ h8_operands.H8RegDirOper(Rd, 2, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -250,8 +250,8 @@ def p_Rs_Rd_4b(va, val, buf, off, tsize):\nRd = val2 & 0xf\nopers = (\n- H8RegDirOper(Rs, stsize, va, 0),\n- H8RegDirOper(Rd, dtsize, va, 0),\n+ h8_operands.H8RegDirOper(Rs, stsize, va, 0),\n+ h8_operands.H8RegDirOper(Rd, dtsize, va, 0),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -265,8 +265,8 @@ def p_Rs_ERd(va, val, buf, off, tsize):\n# FIXME: make sure ER# and R# have correct metaregister values\nopers = (\n- H8RegDirOper(Rs, tsize, va, 0),\n- H8RegDirOper(ERd, 4, va, 0),\n+ h8_operands.H8RegDirOper(Rs, tsize, va, 0),\n+ h8_operands.H8RegDirOper(ERd, 4, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -279,8 +279,8 @@ def p_ERs_ERd(va, val, buf, off, tsize):\nERd = val & 0x7\nopers = (\n- H8RegDirOper(ERs, tsize, va, 0),\n- H8RegDirOper(ERd, tsize, va, 0),\n+ h8_operands.H8RegDirOper(ERs, tsize, va, 0),\n+ h8_operands.H8RegDirOper(ERd, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -294,8 +294,8 @@ def p_Rs_ERd_4b(va, val, buf, off, tsize):\nERd = val2 & 0x7\nopers = (\n- H8RegDirOper(Rs, tsize, va, 0),\n- H8RegDirOper(ERd, tsize, va, 0),\n+ h8_operands.H8RegDirOper(Rs, tsize, va, 0),\n+ h8_operands.H8RegDirOper(ERd, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -306,9 +306,7 @@ def p_ERd(va, val, buf, off, tsize):\nop = val >> 4\nERd = val & 0x7\n- opers = (\n- H8RegDirOper(ERd, tsize, va, 0),\n- )\n+ opers = (h8_operands.H8RegDirOper(ERd, tsize, va, 0),)\nreturn (op, None, opers, iflags, 2)\n@@ -320,8 +318,8 @@ def p_Rn_Rd(va, val, buf, off, tsize):\nRd = val & 0xf\nopers = (\n- H8RegDirOper(Rn, tsize, va, 0),\n- H8RegDirOper(Rd, tsize, va, 0),\n+ h8_operands.H8RegDirOper(Rn, tsize, va, 0),\n+ h8_operands.H8RegDirOper(Rd, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -343,13 +341,13 @@ def p_68_69_6e_6f(va, val, buf, off, tsize):\nif val & 0x80: # reverse operand order\nopers = (\n- H8RegDirOper(Rd, tsize, va, 0),\n- H8RegIndirOper(aERs, tsize, va, disp=disp, dispsz=dispsz, oflags=0),\n+ h8_operands.H8RegDirOper(Rd, tsize, va, 0),\n+ h8_operands.H8RegIndirOper(aERs, tsize, va, disp=disp, dispsz=dispsz, oflags=0),\n)\nelse:\nopers = (\n- H8RegIndirOper(aERs, tsize, va, disp=disp, dispsz=dispsz, oflags=0),\n- H8RegDirOper(Rd, tsize, va, 0),\n+ h8_operands.H8RegIndirOper(aERs, tsize, va, disp=disp, dispsz=dispsz, oflags=0),\n+ h8_operands.H8RegDirOper(Rd, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, isz)\n@@ -364,8 +362,8 @@ def p_Rn_aERd(va, val, buf, off, tsize):\nRn = (val2 >> 4) & 0xf\nopers = (\n- H8RegDirOper(Rn, tsize, va, 0),\n- H8RegIndirOper(aERd, tsize, va, disp=0, oflags=0),\n+ h8_operands.H8RegDirOper(Rn, tsize, va, 0),\n+ h8_operands.H8RegIndirOper(aERd, tsize, va, disp=0, oflags=0),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -380,8 +378,8 @@ def p_Rn_aAA8(va, val, buf, off, tsize):\naAA8 = val & 0xff\nopers = (\n- H8RegDirOper(Rn, tsize, va, 0),\n- H8AbsAddrOper(aAA8, tsize, aasize=1),\n+ h8_operands.H8RegDirOper(Rn, tsize, va, 0),\n+ h8_operands.H8AbsAddrOper(aAA8, tsize, aasize=1),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -393,7 +391,7 @@ def p_aERn(va, val, buf, off, tsize):\naERn = (val >> 4) & 0x7\nopers = (\n- H8RegIndirOper(aERn, tsize, va, 0),\n+ h8_operands.H8RegIndirOper(aERn, tsize, va, 0),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -407,7 +405,7 @@ def p_aAA24(va, val, buf, off, tsize):\naAA24 = ((val & 0xf) << 16) | val2\nopers = (\n- H8AbsAddrOper(aAA24, tsize, aasize=3),\n+ h8_operands.H8AbsAddrOper(aAA24, tsize, aasize=3),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -419,7 +417,7 @@ def p_aaAA8(va, val, buf, off, tsize):\naaAA8 = val & 0xff\nopers = (\n- H8MemIndirOper(aaAA8),\n+ h8_operands.H8MemIndirOper(aaAA8),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -431,7 +429,7 @@ def p_disp8(va, val, buf, off, tsize):\ndisp8 = e_bits.signed(val & 0xfe, 1)\nopers = (\n- H8PcOffsetOper(disp8, va, 1),\n+ h8_operands.H8PcOffsetOper(disp8, va, 1),\n)\nreturn (op, None, opers, iflags, 2)\n@@ -450,7 +448,7 @@ def p_disp16(va, val, buf, off, tsize):\nmnem, iflags = bcc[opnibble]\nopers = (\n- H8PcOffsetOper(disp16, va, 2),\n+ h8_operands.H8PcOffsetOper(disp16, va, 2),\n)\nreturn (op, mnem, opers, iflags, 4)\n@@ -464,8 +462,8 @@ def p_Rs_aAA16(va, val, buf, off, tsize):\naAA16 = val2\nopers = (\n- H8RegDirOper(Rs, tsize, va),\n- H8AbsAddrOper(aAA16, tsize, aasize=2),\n+ h8_operands.H8RegDirOper(Rs, tsize, va),\n+ h8_operands.H8AbsAddrOper(aAA16, tsize, aasize=2),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -479,8 +477,8 @@ def p_Rs_aAA24(va, val, buf, off, tsize):\naAA24 = val2 & 0xffffff\nopers = (\n- H8RegDirOper(Rs, tsize, va),\n- H8AbsAddrOper(aAA24, tsize, aasize=4),\n+ h8_operands.H8RegDirOper(Rs, tsize, va),\n+ h8_operands.H8AbsAddrOper(aAA24, tsize, aasize=4),\n)\nreturn (op, None, opers, iflags, 6)\n@@ -494,8 +492,8 @@ def p_aAA16_Rd(va, val, buf, off, tsize):\naAA16 = val2\nopers = (\n- H8AbsAddrOper(aAA16, tsize, aasize=2),\n- H8RegDirOper(Rd, tsize, va),\n+ h8_operands.H8AbsAddrOper(aAA16, tsize, aasize=2),\n+ h8_operands.H8RegDirOper(Rd, tsize, va),\n)\nreturn (op, None, opers, iflags, 4)\n@@ -509,8 +507,8 @@ def p_aAA24_Rd(va, val, buf, off, tsize):\naAA24 = val2 & 0xffffff\nopers = (\n- H8AbsAddrOper(aAA24, tsize, aasize=4),\n- H8RegDirOper(Rd, tsize, va),\n+ h8_operands.H8AbsAddrOper(aAA24, tsize, aasize=4),\n+ h8_operands.H8RegDirOper(Rd, tsize, va),\n)\nreturn (op, None, opers, iflags, 6)\n@@ -615,13 +613,13 @@ def p_01(va, val, buf, off, tsize):\ners = val2 & 7\nif val2 & 0x80:\nopers = (\n- H8RegDirOper(ers, tsize, va),\n- H8RegIndirOper(erd, tsize, va),\n+ h8_operands.H8RegDirOper(ers, tsize, va),\n+ h8_operands.H8RegIndirOper(erd, tsize, va),\n)\nelse:\nopers = (\n- H8RegIndirOper(erd, tsize, va),\n- H8RegDirOper(ers, tsize, va),\n+ h8_operands.H8RegIndirOper(erd, tsize, va),\n+ h8_operands.H8RegDirOper(ers, tsize, va),\n)\nelif d2 == 0x6b:\n@@ -633,16 +631,16 @@ def p_01(va, val, buf, off, tsize):\nerd = val2 & 7\naa = val3 & 0xffffffff\nopers = (\n- H8RegDirOper(erd, tsize, va),\n- H8AbsAddrOper(aa, tsize, aasize=4),\n+ h8_operands.H8RegDirOper(erd, tsize, va),\n+ h8_operands.H8AbsAddrOper(aa, tsize, aasize=4),\n)\nelse:\n# 2\ners = val2 & 7\naa = val3 & 0xffffffff\nopers = (\n- H8AbsAddrOper(aa, tsize, aasize=4),\n- H8RegDirOper(ers, tsize, va),\n+ h8_operands.H8AbsAddrOper(aa, tsize, aasize=4),\n+ h8_operands.H8RegDirOper(ers, tsize, va),\n)\nelse:\nval3, = struct.unpack('>H', buf[off+4:off+6])\n@@ -652,16 +650,16 @@ def p_01(va, val, buf, off, tsize):\nerd = val2 & 7\naa = val3 & 0xffff\nopers = (\n- H8RegDirOper(erd, tsize, va),\n- H8AbsAddrOper(aa, tsize, aasize=2),\n+ h8_operands.H8RegDirOper(erd, tsize, va),\n+ h8_operands.H8AbsAddrOper(aa, tsize, aasize=2),\n)\nelse:\n# 0\ners = val2 & 7\naa = val3 & 0xffff\nopers = (\n- H8AbsAddrOper(aa, tsize, aasize=2),\n- H8RegDirOper(ers, tsize, va),\n+ h8_operands.H8AbsAddrOper(aa, tsize, aasize=2),\n+ h8_operands.H8RegDirOper(ers, tsize, va),\n)\nelif d2 == 0x6d: # TODO: test me!!\n@@ -677,14 +675,14 @@ def p_01(va, val, buf, off, tsize):\nif val2 & 0x80:\n# mov.l ERs, @(d:16,ERd)\nopers = (\n- H8RegDirOper(er0, tsize, va),\n- H8RegIndirOper(er1, tsize, va, disp, dispsz=2),\n+ h8_operands.H8RegDirOper(er0, tsize, va),\n+ h8_operands.H8RegIndirOper(er1, tsize, va, disp, dispsz=2),\n)\nelse:\n# mov.l @(d:16,ERs), ERd\nopers = (\n- H8RegIndirOper(er1, tsize, va, disp, dispsz=2),\n- H8RegDirOper(er0, tsize, va),\n+ h8_operands.H8RegIndirOper(er1, tsize, va, disp, dispsz=2),\n+ h8_operands.H8RegDirOper(er0, tsize, va),\n)\nelif d2 == 0x78:\n@@ -698,15 +696,15 @@ def p_01(va, val, buf, off, tsize):\nif (val3 & 0x80):\n# mov.l ERs, @(d:24,ERd)\nopers = (\n- H8RegDirOper(er0, tsize, va),\n- H8RegIndirOper(er1, tsize, va, disp, dispsz=4),\n+ h8_operands.H8RegDirOper(er0, tsize, va),\n+ h8_operands.H8RegIndirOper(er1, tsize, va, disp, dispsz=4),\n)\nelse:\n# mov.l @(d:24,ERs), ERd\nopers = (\n- H8RegIndirOper(er1, tsize, va, disp, dispsz=4),\n- H8RegDirOper(er0, tsize, va),\n+ h8_operands.H8RegIndirOper(er1, tsize, va, disp, dispsz=4),\n+ h8_operands.H8RegDirOper(er0, tsize, va),\n)\nelif diff in (1, 2, 3):\n@@ -721,15 +719,15 @@ def p_01(va, val, buf, off, tsize):\nif optest == 0x6df0:\nmnem = 'stm'\nopers = (\n- H8RegMultiOper(rn, rcount),\n- H8RegIndirOper(e_const.REG_SP, tsize, va, 0, oflags=e_const.OF_PREDEC),\n+ h8_operands.H8RegMultiOper(rn, rcount),\n+ h8_operands.H8RegIndirOper(e_const.REG_SP, tsize, va, 0, oflags=e_const.OF_PREDEC),\n)\nelif optest == 0x6d70:\nmnem = 'ldm'\nopers = (\n- H8RegIndirOper(e_const.REG_SP, tsize, va, 0, oflags=e_const.OF_POSTINC),\n- H8RegMultiOper(rn-diff, rcount),\n+ h8_operands.H8RegIndirOper(e_const.REG_SP, tsize, va, 0, oflags=e_const.OF_POSTINC),\n+ h8_operands.H8RegMultiOper(rn-diff, rcount),\n)\nelse:\n@@ -771,8 +769,8 @@ def p_01(va, val, buf, off, tsize):\noflags = e_const.OF_POSTINC\ners = (val2 >> 4) & 0x7\nopers = (\n- H8RegIndirOper(ers, tsize, va, oflags=oflags),\n- H8RegDirOper(e_regs.REG_CCR + exr, 4, va)\n+ h8_operands.H8RegIndirOper(ers, tsize, va, oflags=oflags),\n+ h8_operands.H8RegDirOper(e_regs.REG_CCR + exr, 4, va)\n)\nelif d2 in (0x6f, 0x78): # @(d:16,ERs),CCR / @(d:24,ERs)\n@@ -787,8 +785,8 @@ def p_01(va, val, buf, off, tsize):\ndispsz = 2\ners = (val2 >> 4) & 0x7\nopers = (\n- H8RegIndirOper(ers, tsize, va, disp, dispsz),\n- H8RegDirOper(e_regs.REG_CCR + exr, 4, va)\n+ h8_operands.H8RegIndirOper(ers, tsize, va, disp, dispsz),\n+ h8_operands.H8RegDirOper(e_regs.REG_CCR + exr, 4, va)\n)\nelif d2 == 0x6b: # @aa:16,CCR / @aa:24,CCR\n@@ -802,8 +800,8 @@ def p_01(va, val, buf, off, tsize):\naasize = 2\nisStc = (val2 >> 7) & 1\nopers = (\n- H8AbsAddrOper(aa, tsize, aasize),\n- H8RegDirOper(e_regs.REG_CCR + exr, 4, va)\n+ h8_operands.H8AbsAddrOper(aa, tsize, aasize),\n+ h8_operands.H8RegDirOper(e_regs.REG_CCR + exr, 4, va)\n)\n# after all the decisions...\n@@ -832,9 +830,7 @@ def p_01(va, val, buf, off, tsize):\nmnem = 'tas' # FIXME: check out what this decodes to\ntsize = 1\nerd = (val2 >> 4) & 7\n- opers = (\n- H8RegIndirOper(erd, tsize, va, oflags=0),\n- )\n+ opers = (h8_operands.H8RegIndirOper(erd, tsize, va, oflags=0),)\nelse:\nraise envi.InvalidInstruction(bytez=buf[off:off+16], va=va)\n@@ -935,9 +931,7 @@ def p_0f_1f(va, val, buf, off, tsize):\nmnem = ('daa', 'das')[aors]\niflags = 0\nrd = val & 0xf\n- opers = (\n- H8RegDirOper(rd, 1, va=va, oflags=0),\n- )\n+ opers = (h8_operands. H8RegDirOper(rd, 1, va=va, oflags=0),)\nelif diff >= 0x80:\nmnem = ('mov', 'cmp')[aors]\nop, nmnem, opers, iflags, isz = p_ERs_ERd(va, val, buf, off, tsize=4)\n@@ -987,9 +981,7 @@ def p_shift_10_11_12_13_17(va, val, buf, off, tsize):\nh8_operands.H8RegDirOper(rd, osz, va, 0),\n)\nelse:\n- opers = (\n- H8RegDirOper(rd, osz, va, 0),\n- )\n+ opers = (h8_operands.H8RegDirOper(rd, osz, va, 0),)\nreturn (op, mnem, opers, iflags, 2)\n@@ -1040,8 +1032,8 @@ def p_6A_6B(va, val, buf, off, tsize):\nelse:\nrn = (val2 >> 4) & 0xf\nopers = (\n- H8RegDirOper(rn, tsize, va, ),\n- H8AbsAddrOper(aa, tsize, aasize),\n+ h8_operands.H8RegDirOper(rn, tsize, va, ),\n+ h8_operands.H8AbsAddrOper(aa, tsize, aasize),\n)\nreturn op, mnem, opers, 0, isz\n@@ -1063,30 +1055,26 @@ def p_6c_6d_0100(va, val, buf, off, tsize):\nif val & 0xf0 == 0xf0:\n# push\nmnem = 'push'\n- opers = (\n- H8RegDirOper(er0, tsize, va),\n- )\n+ opers = (h8_operands.H8RegDirOper(er0, tsize, va),)\nelse:\n# mov\nmnem = 'mov'\nopers = (\n- H8RegDirOper(er0, tsize, va),\n- H8RegIndirOper(er1, tsize, va, 0, oflags=e_const.OF_PREDEC),\n+ h8_operands.H8RegDirOper(er0, tsize, va),\n+ h8_operands.H8RegIndirOper(er1, tsize, va, 0, oflags=e_const.OF_PREDEC),\n)\nelse:\n# mov @ERs+,ERd\nif val & 0xf0 == 0x70:\n# pop\nmnem = 'pop'\n- opers = (\n- H8RegDirOper(er0, tsize, va),\n- )\n+ opers = (h8_operands.H8RegDirOper(er0, tsize, va),)\nelse:\n# mov\nmnem = 'mov'\nopers = (\n- H8RegIndirOper(er1, tsize, va, 0, oflags=e_const.OF_POSTINC),\n- H8RegDirOper(er0, tsize, va),\n+ h8_operands.H8RegIndirOper(er1, tsize, va, 0, oflags=e_const.OF_POSTINC),\n+ h8_operands.H8RegDirOper(er0, tsize, va),\n)\nreturn (op, mnem, opers, iflags, isz)\n@@ -1110,15 +1098,15 @@ def p_Mov_78(va, val, buf, off, tsize):\nerd = (val >> 4) & 0x7\nrs = val2 & 0xf\nopers = (\n- H8RegDirOper(rs, tsize),\n- H8RegIndirOper(erd, tsize, va, disp=disp, dispsz=4, oflags=0),\n+ h8_operands.H8RegDirOper(rs, tsize),\n+ h8_operands.H8RegIndirOper(erd, tsize, va, disp=disp, dispsz=4, oflags=0),\n)\nelse:\ners = (val >> 4) & 0x7\nrd = val2 & 0xf\nopers = (\n- H8RegIndirOper(ers, tsize, va, disp=disp, dispsz=4, oflags=0),\n- H8RegDirOper(rd, tsize),\n+ h8_operands.H8RegIndirOper(ers, tsize, va, disp=disp, dispsz=4, oflags=0),\n+ h8_operands.H8RegDirOper(rd, tsize),\n)\nreturn (op, mnem, opers, iflags, 8)\n@@ -1178,8 +1166,8 @@ def p_7c(va, val, buf, off, tsize):\nerd = (val >> 4) & 0x7\nrn = (val2 >> 4) & 0xf\nopers = (\n- H8RegDirOper(rn, tsize=tsize),\n- H8RegIndirOper(erd, tsize, va),\n+ h8_operands.H8RegDirOper(rn, tsize=tsize),\n+ h8_operands.H8RegIndirOper(erd, tsize, va),\n)\nelif telltale == 0x73:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/h8.py",
"new_path": "vivisect/impemu/platarch/h8.py",
"diff": "-import envi.archs.h8 as e_h8\nimport envi.archs.h8.emu as h8_emu\nimport envi.archs.h8.regs as h8_regs\nimport vivisect.impemu.emulator as v_i_emulator\n@@ -9,5 +8,5 @@ class H8WorkspaceEmulator(v_i_emulator.WorkspaceEmulator, h8_emu.H8Emulator):\ntaintregs = [h8_regs.REG_ER0, h8_regs.REG_ER1, h8_regs.REG_ER2]\ndef __init__(self, vw, logwrite=False, logread=False):\n- e_h8.H8Emulator.__init__(self)\n+ h8_emu.H8Emulator.__init__(self)\nv_i_emulator.WorkspaceEmulator.__init__(self, vw, logwrite=logwrite, logread=logread)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Bring more things into Imperial Compliance
|
718,765 |
18.03.2019 15:50:04
| 14,400 |
bd75e994209bd82f297dd8f1082a7ccf0268933d
|
So many little flake8 cleanups as I track down this unittest failure
|
[
{
"change_type": "MODIFY",
"old_path": "envi/cli.py",
"new_path": "envi/cli.py",
"diff": "@@ -456,8 +456,7 @@ class EnviCli(Cmd):\ncode.interact(local=locals)\ndef parseExpression(self, expr):\n- l = self.getExpressionLocals()\n- return long(e_expr.evaluate(expr, l))\n+ return long(e_expr.evaluate(expr, self.getExpressionLocals()))\ndef do_binstr(self, line):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -14,13 +14,14 @@ class ExpressionFail(Exception):\ndef __str__(self):\nreturn self.__repr__()\n-def evaluate(pycode, locals):\n+\n+def evaluate(pycode, locs):\ntry:\n- val = eval(pycode, {}, locals)\n- except Exception, e:\n+ val = eval(pycode, {}, locs)\n+ except Exception:\ntry:\n# check through the keys for anything we might want to replace\n- keys = locals.keys()\n+ keys = locs.keys()\n# sort the keys in reverse order so that longer matching strings take priority\nkeys.sort(reverse=True)\n@@ -28,16 +29,17 @@ def evaluate(pycode, locals):\n# replace the substrings with the string versions of the lookup value\nfor key in keys:\nif key in pycode:\n- pval = locals[key]\n+ pval = locs[key]\npycode = pycode.replace(key, str(pval))\n- val = eval(pycode, {}, locals)\n+ val = eval(pycode, {}, locs)\n- except Exception, e:\n+ except Exception as e:\nraise ExpressionFail(pycode, e)\nreturn val\n+\nclass ExpressionLocals(dict):\n\"\"\"\nAn object to act as the locals dictionary for the evaluation\n@@ -49,9 +51,10 @@ class ExpressionLocals(dict):\nself.symobj = symobj\ndef __getitem__(self, name):\n- if self.symobj != None:\n+ if self.symobj is not None:\nret = self.symobj.getSymByName(name)\n- if ret != None: return ret.value\n+ if ret is not None:\n+ return ret.value\nreturn dict.__getitem__(self, name)\nget = __getitem__\n@@ -66,7 +69,7 @@ class ExpressionLocals(dict):\nreturn [key for key in self]\ndef __contains__(self, key):\n- return self.__getitem__(key) != None\n+ return self.__getitem__(key) is not None\nhas_key = __contains__\n@@ -134,4 +137,3 @@ class MemoryExpressionLocals(ExpressionLocals):\nthe address pointed to by addr.\n\"\"\"\nreturn self.memobj.readMemoryPtr(address)\n-\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "import re\nimport struct\n-import collections\nimport envi\nimport envi.bits as e_bits\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/symstore/resolver.py",
"new_path": "envi/symstore/resolver.py",
"diff": "@@ -47,7 +47,7 @@ class Symbol:\nreturn self.size\ndef __str__(self):\n- if self.fname != None:\n+ if self.fname is not None:\nreturn \"%s.%s\" % (self.fname, self.name)\nreturn self.name\n@@ -59,6 +59,7 @@ class FunctionSymbol(Symbol):\nUsed to represent functions.\n\"\"\"\nsymtype = SYMSTOR_SYM_FUNCTION\n+\ndef __repr__(self):\nreturn \"%s.%s()\" % (self.fname, self.name)\n@@ -67,6 +68,7 @@ class SectionSymbol(Symbol):\nUsed for file sections/segments.\n\"\"\"\nsymtype = SYMSTOR_SYM_SECTION\n+\ndef __repr__(self):\nreturn \"%s[%s]\" % (self.fname, self.name)\n@@ -103,15 +105,15 @@ class SymbolResolver:\nsymval = long(sym)\nself.symaddrs.pop(symval, None)\n- bbase = symval & self.bucketmask\n+ # bbase = symval & self.bucketmask\n# self.objbuckets[bbase].remove(sym)\nsubres = None\n- if sym.fname != None:\n+ if sym.fname is not None:\nsubres = self.symnames.get(sym.fname)\n# Potentially del it from the sub resolver's namespace\n- if subres != None:\n+ if subres is not None:\nsubres.delSymbol(sym)\n# Otherwise del it from our namespace\n@@ -127,7 +129,7 @@ class SymbolResolver:\n\"\"\"\n# Fake these out for the API ( optimized implementations should *not* call this )\nsymtup = (sym.value, sym.size, sym.name, sym.symtype, sym.fname)\n- symtups = [symtup,]\n+ symtups = [symtup]\nself._nomSymTupAddrs(symtups)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -177,7 +177,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nbased workspace used to store to the server.\n'''\nvivGuid = self.getMeta('GUID')\n- if vivGuid == None:\n+ if vivGuid is None:\nvivGuid = guid()\nself.setMeta('GUID', vivGuid)\n@@ -222,10 +222,10 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\narch = self.getMeta('Architecture')\neclass = viv_imp_lookup.workspace_emus.get((plat, arch))\n- if eclass == None:\n+ if eclass is None:\neclass = viv_imp_lookup.workspace_emus.get(arch)\n- if eclass == None:\n+ if eclass is None:\nraise Exception(\"WorkspaceEmulation not supported on %s yet!\" % arch)\nemu = eclass(self, logwrite=logwrite, logread=logread)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/emulator.py",
"new_path": "vivisect/symboliks/emulator.py",
"diff": "@@ -32,7 +32,6 @@ class SymbolikEmulator:\ndict(self._sym_mem),\nself._sym_rseed)\n-\ndef setSymSnapshot(self, snap):\n(self._sym_meta,\nself._sym_vars,\n@@ -104,17 +103,17 @@ class SymbolikEmulator:\n# check for a previous write first...\nsymmem = self._sym_mem.get(addrval)\n- if symmem != None:\n+ if symmem is not None:\nsymaddr, symval = symmem\nreturn symval\n# If we have a workspace, check it for meaningful\n# symbols etc...\n- if self._sym_vw != None:\n+ if self._sym_vw is not None:\n# Make a special check for imports...\nloc = self._sym_vw.getLocation(addrval)\n- if loc != None:\n+ if loc is not None:\nlva, lsize, ltype, linfo = loc\nif ltype == LOC_IMPORT:\nreturn Var(linfo, self.__width__)\n@@ -129,7 +128,7 @@ class SymbolikEmulator:\nself._sym_mem[addrval] = (symaddr, symval)\ndef setSymVariable(self, name, symval, width=None):\n- if width == None:\n+ if width is None:\nwidth = self.__width__\nself._sym_vars[name] = symval\n@@ -141,7 +140,7 @@ class SymbolikEmulator:\nv = self.getSymVariable('eax')\n'''\nret = self._sym_vars.get(name)\n- if ret == None and create:\n+ if ret is None and create:\nreturn Var(name, self.__width__)\nreturn ret\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/__init__.py",
"new_path": "vtrace/__init__.py",
"diff": "@@ -149,7 +149,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\n# Set us up with an envi arch module\n# FIXME eventually we should just inherit one...\n- if archname == None:\n+ if archname is None:\narchname = envi.getCurrentArch()\narch = envi.getArchByName(archname)\n@@ -183,7 +183,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nif num <= 0:\nraise Exception('you must specify a positive number of opcodes')\n- if va == None:\n+ if va is None:\nva = self.getProgramCounter()\nops = []\n@@ -245,7 +245,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nself.platformAttach(pid)\nself._justAttached(pid)\nself.wait()\n- except Exception, msg:\n+ except Exception as msg:\nraise PlatformException(str(msg))\ndef stepi(self):\n@@ -282,7 +282,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nself.steploop()\nelse:\n- if until != None:\n+ if until is not None:\nself.setMode(\"RunForever\", True)\nself.addBreakpoint(StopAndRemoveBreak(until))\n@@ -356,7 +356,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\n\"\"\"\nself._loadBinaryNorm(libname)\nsym = self.getSymByName(libname)\n- if sym == None:\n+ if sym is None:\nraise Exception('Invalid Library Name: %s' % libname)\nreturn sym.getSymList()\n@@ -369,12 +369,12 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\n# file parsing.\nr = e_resolv.SymbolResolver.getSymByAddr(self, addr, exact=exact)\n- if r != None:\n+ if r is not None:\nreturn r\n# See if we need to parse the file.\nmmap = self.getMemoryMap(addr)\n- if mmap == None:\n+ if mmap is None:\nreturn None\nva, size, perms, fname = mmap\n@@ -397,17 +397,17 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nreturns a tuple (sym, is_thunk). sym is None if no sym is found.\n'''\nsym = self.getSymByAddr(va)\n- if sym != None:\n+ if sym is not None:\nreturn str(sym), False\ntry:\nop = self.parseOpcode(va)\nfor tva, tflags in op.getTargets(emu=self):\n- if tva == None:\n+ if tva is None:\ncontinue\nsym = self.getSymByAddr(tva)\n- if sym != None:\n+ if sym is not None:\nreturn str(sym), True\nexcept Exception as e:\n@@ -1294,13 +1294,13 @@ class VtraceExpressionLocals(e_expr.MemoryExpressionLocals):\nregs = self.trace.getRegisters()\nr = regs.get(name, None)\n- if r != None:\n+ if r is not None:\nreturn r\n# Check local variables\nlocs = self.trace.getVariables()\nr = locs.get(name, None)\n- if r != None:\n+ if r is not None:\nreturn r\nreturn e_expr.MemoryExpressionLocals.__getitem__(self, name)\n@@ -1311,7 +1311,7 @@ class VtraceExpressionLocals(e_expr.MemoryExpressionLocals):\nbreakpoint code (or similar even processors) to begin\nexecution again after event processing...\n'''\n- self.trace.runAgain();\n+ self.trace.runAgain()\ndef frame(self, index):\n\"\"\"\n@@ -1331,12 +1331,12 @@ class VtraceExpressionLocals(e_expr.MemoryExpressionLocals):\nstack base or whatever. If threadid is left out, it\nuses the threadid of the current thread context.\n\"\"\"\n- if threadnum == None:\n+ if threadnum is None:\n# Get the thread ID of the current Thread Context\nthreadnum = self.trace.getMeta(\"ThreadId\")\nteb = self.trace.getThreads().get(threadnum, None)\n- if teb == None:\n+ if teb is None:\nraise Exception(\"ERROR - Unknown Thread Id %d\" % threadnum)\nreturn teb\n@@ -1347,7 +1347,7 @@ class VtraceExpressionLocals(e_expr.MemoryExpressionLocals):\nbreakpoint\n\"\"\"\nbp = self.trace.getBreakpoint(bpid)\n- if bp == None:\n+ if bp is None:\nraise Exception(\"Unknown Breakpoint ID: %d\" % bpid)\nreturn bp.resolveAddress(self.trace)\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/notifiers.py",
"new_path": "vtrace/notifiers.py",
"diff": "@@ -40,11 +40,11 @@ class Notifier(object):\nself.notify(event, trace)\ndef notify(self, event, trace):\n- print \"Got event: %d from pid %d\" % (event, trace.getPid())\n+ print(\"Got event: %d from pid %d\" % (event, trace.getPid()))\nclass VerboseNotifier(Notifier):\ndef notify(self, event, trace):\n- print \"PID %d - ThreadID (%d) got\" % (trace.getPid(), trace.getMeta(\"ThreadId\")),\n+ print(\"PID %d - ThreadID (%d) got\" % (trace.getPid(), trace.getMeta(\"ThreadId\")))\nif event == vtrace.NOTIFY_ALL:\nprint(\"WTF, how did we get a vtrace.NOTIFY_ALL event?!?!\")\nelif event == vtrace.NOTIFY_SIGNAL:\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/base.py",
"new_path": "vtrace/platforms/base.py",
"diff": "@@ -214,7 +214,7 @@ class TracerBase(vtrace.Notifier):\n# Resolve deferred breaks\nfor bp in self.deferred:\naddr = bp.resolveAddress(self)\n- if addr != None:\n+ if addr is not None:\nself.deferred.remove(bp)\nself.breakpoints[addr] = bp\n@@ -226,7 +226,7 @@ class TracerBase(vtrace.Notifier):\n\"\"\"\nSync the reg-cache into the target process\n\"\"\"\n- if self.regcache != None:\n+ if self.regcache is not None:\nfor tid, ctx in self.regcache.items():\nif ctx.isDirty():\nself.platformSetRegCtx(tid, ctx)\n@@ -236,10 +236,10 @@ class TracerBase(vtrace.Notifier):\n\"\"\"\nMake sure the reg-cache is populated\n\"\"\"\n- if self.regcache == None:\n+ if self.regcache is None:\nself.regcache = {}\nret = self.regcache.get(threadid)\n- if ret == None:\n+ if ret is None:\nret = self.platformGetRegCtx(threadid)\nret.setIsDirty(False)\nself.regcache[threadid] = ret\n@@ -256,7 +256,7 @@ class TracerBase(vtrace.Notifier):\n# Steal a reference because the step should\n# clear curbp...\nbp = self.curbp\n- if bp != None and bp.isEnabled():\n+ if bp is not None and bp.isEnabled():\nif bp.active:\nbp.deactivate(self)\norig = self.getMode(\"FastStep\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/tests/__init__.py",
"new_path": "vtrace/tests/__init__.py",
"diff": "import os\nimport sys\nimport unittest\n-import platform\nimport subprocess\nimport vtrace\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/tests/testbasic.py",
"new_path": "vtrace/tests/testbasic.py",
"diff": "@@ -2,6 +2,7 @@ import os\nimport unittest\nimport vtrace.tests as vt_tests\n+\nclass VtraceBasicTest(vt_tests.VtraceProcessTest):\nbreakpoints = {\n@@ -28,7 +29,7 @@ class VtraceBasicTest(vt_tests.VtraceProcessTest):\ndef test_vtrace_breakpoint(self):\nplat = self.trace.getMeta('Platform')\nsymname = self.breakpoints.get(plat)\n- if symname == None:\n+ if symname is None:\nraise unittest.SkipTest('no platform breakpoint: %s' % plat)\npycode = 'trace.setMeta(\"testbphit\", 1)'\n@@ -38,7 +39,7 @@ class VtraceBasicTest(vt_tests.VtraceProcessTest):\nbp = self.trace.getBreakpoint(bpid)\n- self.assertTrue(bp.address != None)\n+ self.assertTrue(bp.address is not None)\nself.assertTrue(self.trace.getMeta('testbphit'))\ndef test_vtrace_exename(self):\n@@ -54,6 +55,7 @@ class VtraceBasicTest(vt_tests.VtraceProcessTest):\nbreak\nself.assertTrue(pymapfound)\n+\n# All of the above \"simple\" tests should also work in the \"exec\" case\nclass VtraceBasicExecTest(VtraceBasicTest, vt_tests.VtraceExecTest):\nbreakpoints = {\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/tests/testthread.py",
"new_path": "vtrace/tests/testthread.py",
"diff": "@@ -36,5 +36,3 @@ class VtraceThreadTest(vt_tests.VtraceProcessTest):\nself.assertTrue(n.threadexit)\nself.assertTrue(n.threadcreate)\n-\n-\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
So many little flake8 cleanups as I track down this unittest failure
|
718,765 |
20.03.2019 09:54:39
| 14,400 |
758495a90f7b14ab5b37e92931c6509d3b51603f
|
Fix a bunch of flake8 and whitespace issues. And also fix some of the unittests that weren't passing
|
[
{
"change_type": "MODIFY",
"old_path": ".travis.yml",
"new_path": ".travis.yml",
"diff": "@@ -18,4 +18,4 @@ install:\n- \"travis_retry sudo apt-get -qq install libfreetype6-dev liblcms2-dev python-qt4 ghostscript libffi-dev libjpeg-turbo-progs cmake imagemagick\"\n- pip install msgpack-python\n-script: py.test\n+script: python -m unittest discover\n"
},
{
"change_type": "MODIFY",
"old_path": "Elf/__init__.py",
"new_path": "Elf/__init__.py",
"diff": "@@ -252,6 +252,7 @@ class Elf(vs_elf.Elf32, vs_elf.Elf64):\nraise Exception('Unrecognized e_class: %d' % e.e_class)\nself.fd = fd\n+ self.inmem = inmem\nself.bigend = bigend\nbytes = self.readAtOffset(0, len(self))\n@@ -673,6 +674,10 @@ class Elf(vs_elf.Elf32, vs_elf.Elf64):\ndef getSymbols(self):\nreturn self.symbols\n+def elfFromMemoryObject(memobj, baseaddr):\n+ fd = vstruct.MemObjFile(memobj, baseaddr)\n+ return Elf(fd)\n+\ndef getRelocType(val):\nreturn val & 0xff\n"
},
{
"change_type": "MODIFY",
"old_path": "PE/__init__.py",
"new_path": "PE/__init__.py",
"diff": "@@ -1100,32 +1100,8 @@ class PE(object):\nelse:\nraise AttributeError\n-\n-class MemObjFile:\n- \"\"\"\n- A file like object that wraps a MemoryObject (envi) compatable\n- object with a file-like object where seek == VA.\n- \"\"\"\n-\n- def __init__(self, memobj, baseaddr):\n- self.baseaddr = baseaddr\n- self.offset = baseaddr\n- self.memobj = memobj\n-\n- def seek(self, offset):\n- self.offset = self.baseaddr + offset\n-\n- def read(self, size):\n- ret = self.memobj.readMemory(self.offset, size)\n- self.offset += size\n- return ret\n-\n- def write(self, bytes):\n- self.memobj.writeMemory(self.offset, bytes)\n- self.offset += len(bytes)\n-\ndef peFromMemoryObject(memobj, baseaddr):\n- fd = MemObjFile(memobj, baseaddr)\n+ fd = vstruct.MemObjFile(memobj, baseaddr)\nreturn PE(fd, inmem=True)\ndef peFromFileName(fname):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "\"\"\"\nUnified expression helpers.\n\"\"\"\n+\n+\nclass ExpressionFail(Exception):\ndef __init__(self, pycode, exception):\nException.__init__(self)\n@@ -54,12 +56,16 @@ class ExpressionLocals(dict):\nif self.symobj is not None:\nret = self.symobj.getSymByName(name)\nif ret is not None:\n+ if ret.symtype == 3:\n+ return ret\n+ else:\nreturn ret.value\nreturn dict.__getitem__(self, name)\nget = __getitem__\ndef __iter__(self):\n+ if self.symobj is not None:\nfor va, name in self.symobj.getNames():\nyield name\n"
},
{
"change_type": "MODIFY",
"old_path": "vdb/tests/teststalker.py",
"new_path": "vdb/tests/teststalker.py",
"diff": "-import unittest\n-\nimport vdb.stalker as v_stalker\nimport vtrace.tests as vt_tests\n@@ -9,12 +7,12 @@ breakpoints = {\n'freebsd': 'libc.exit',\n}\n+\nclass VdbStalkerTest(vt_tests.VtraceProcessTest):\ndef test_vdb_stalker(self):\nplat = self.trace.getMeta('Platform')\nsymname = breakpoints.get(plat)\n-\nentry = self.trace.parseExpression(symname)\nv_stalker.addStalkerEntry(self.trace, entry)\n"
},
{
"change_type": "MODIFY",
"old_path": "vstruct/__init__.py",
"new_path": "vstruct/__init__.py",
"diff": "@@ -2,10 +2,33 @@ import struct\nfrom copy import deepcopy\nfrom inspect import isclass\n-from StringIO import StringIO\nimport vstruct.primitives as vs_prims\n+\n+class MemObjFile:\n+ \"\"\"\n+ A file like object that wraps a MemoryObject (envi) compatable\n+ object with a file-like object where seek == VA.\n+ \"\"\"\n+\n+ def __init__(self, memobj, baseaddr):\n+ self.baseaddr = baseaddr\n+ self.offset = baseaddr\n+ self.memobj = memobj\n+\n+ def seek(self, offset):\n+ self.offset = self.baseaddr + offset\n+\n+ def read(self, size):\n+ ret = self.memobj.readMemory(self.offset, size)\n+ self.offset += size\n+ return ret\n+\n+ def write(self, bytes):\n+ self.memobj.writeMemory(self.offset, bytes)\n+ self.offset += len(bytes)\n+\ndef isVstructType(x):\nreturn isinstance(x, vs_prims.v_base)\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/__init__.py",
"new_path": "vtrace/__init__.py",
"diff": "@@ -129,6 +129,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nself.modes = {}\nself.modedocs = {}\nself.notifiers = {}\n+ self.namecache = []\n# For all transient data (if notifiers want\n# to track stuff per-trace\n@@ -360,6 +361,15 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nraise Exception('Invalid Library Name: %s' % libname)\nreturn sym.getSymList()\n+ def getNames(self):\n+ if not self.namecache:\n+ names = []\n+ for lib in self.getNormalizedLibNames():\n+ for sym in self.getSymsForFile(lib):\n+ names.append((sym.value, str(sym)))\n+ self.namecache = sorted(names, key=lambda n: len(n[1]), reverse=True)\n+ return self.namecache\n+\ndef getSymByAddr(self, addr, exact=True):\n\"\"\"\nReturn an envi Symbol object for an address.\n@@ -1071,10 +1081,10 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nelse:\nvs = vstruct.getStructure(sname)\n- if vs == None:\n+ if vs is None:\nreturn None\n- if va == None:\n+ if va is None:\nreturn vs\nbytez = self.readMemory(va, len(vs))\n@@ -1303,6 +1313,12 @@ class VtraceExpressionLocals(e_expr.MemoryExpressionLocals):\nif r is not None:\nreturn r\n+ # Check the loaded libraries\n+ for lib in self.trace.getNormalizedLibNames():\n+ for sym in self.trace.getSymsForFile(lib):\n+ if str(sym) == name:\n+ return sym\n+\nreturn e_expr.MemoryExpressionLocals.__getitem__(self, name)\ndef go(self):\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/base.py",
"new_path": "vtrace/platforms/base.py",
"diff": "@@ -539,7 +539,7 @@ class TracerBase(vtrace.Notifier):\nself.setMeta(\"LatestLibraryNorm\", None)\nnormname = self.normFileName(libname)\n- if self.getSymByName(normname) != None:\n+ if self.getSymByName(normname) is not None:\nnormname = \"%s_%.8x\" % (normname, address)\nself.getMeta(\"LibraryPaths\")[address] = libname\n@@ -588,7 +588,7 @@ class TracerBase(vtrace.Notifier):\ndef _loadBinaryNorm(self, normname):\nif not self.libloaded.get(normname, False):\nfname = self.libpaths.get(normname)\n- if fname != None:\n+ if fname is not None:\nself._loadBinary(fname)\nreturn True\nreturn False\n@@ -601,7 +601,7 @@ class TracerBase(vtrace.Notifier):\nnormname = self.normFileName(filename)\nif not self.libloaded.get(normname, False):\naddress = self.getMeta(\"LibraryBases\").get(normname)\n- if address == None:\n+ if address is None:\nreturn False\nself.platformParseBinary(filename, address, normname)\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/linux.py",
"new_path": "vtrace/platforms/linux.py",
"diff": "@@ -343,13 +343,13 @@ class LinuxMixin(v_posix.PtraceMixin, v_posix.PosixMixin):\nif v_posix.ptrace(v_posix.PT_STEP, pid, 0, 0) != 0:\nraise Exception(\"PT_CONTINUE failed! linux platformExec\")\n- self.pthreads = [pid,]\n+ self.pthreads = [pid]\nself.setMeta(\"ExeName\", self._findExe(pid))\nreturn pid\n@v_base.threadwrap\ndef platformAttach(self, pid):\n- self.pthreads = [pid,]\n+ self.pthreads = [pid]\nself.setMeta(\"ThreadId\", pid)\nif v_posix.ptrace(PT_ATTACH, pid, 0, 0) != 0:\nraise Exception(\"PT_ATTACH failed!\")\n@@ -776,7 +776,6 @@ class LinuxAmd64Trace(\nv_posix.ElfMixin.__init__(self)\nv_amd64.Amd64Mixin.__init__(self)\nLinuxMixin.__init__(self)\n-\nself.dbgidx = self.archGetRegCtx().getRegisterIndex(\"debug0\")\n@v_base.threadwrap\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/posix.py",
"new_path": "vtrace/platforms/posix.py",
"diff": "Posix Signaling Module\n\"\"\"\n# Copyright (C) 2007 Invisigoth - See LICENSE file for details\n-import sys\nimport os\n+import sys\nimport struct\nimport signal\nimport platform\n@@ -57,7 +57,7 @@ class PosixMixin:\ndef handleAttach(self):\nself.fireNotifiers(vtrace.NOTIFY_ATTACH)\n- self._findLibraryMaps('\\x7fELF')\n+ self._findLibraryMaps('\\x7fELF', always=True)\nself._simpleCreateThreads()\n# We'll emulate windows here and send an additional\n# break after our library load events to make things easy\n@@ -138,8 +138,16 @@ class ElfMixin:\nElf.STT_SECTION: e_resolv.SectionSymbol,\n}\n+ try:\nfd = self.platformOpenFile(filename)\nelf = Elf.Elf(fd)\n+ except IOError:\n+ try:\n+ # it's possible we hit vdso or something similar\n+ elf = Elf.elfFromMemoryObject(self, baseaddr)\n+ except:\n+ raise\n+ # elf = Elf.Elf(fd)\naddbase = 0\nif not elf.isPreLinked() and elf.isSharedObject():\naddbase = baseaddr\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/tests/tests_envitools.py",
"new_path": "vtrace/tests/tests_envitools.py",
"diff": "-import unittest\n-\nimport vtrace\nimport vtrace.envitools\n+\nclass EnvitoolsTests(vtrace.tests.VtraceProcessTest):\ndef test_emulatorFromTrace(self):\nemu = vtrace.envitools.emuFromTrace(self.trace)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Fix a bunch of flake8 and whitespace issues. And also fix some of the unittests that weren't passing
|
718,765 |
20.03.2019 13:35:47
| 14,400 |
0ea236c05c0b1eb1a76ed7254b4785fdeac6311e
|
Another unittest works. One left I think
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/__init__.py",
"new_path": "envi/archs/i386/__init__.py",
"diff": "import envi\n-import envi.bits as e_bits\n-#TODO\n-# f0 0f c7 4d 00 75 f0 5d 5b - this is NOT right in disasm\n-\n-import copy\n-import struct\n-import traceback\n+# TODO: f0 0f c7 4d 00 75 f0 5d 5b - this is NOT right in disasm\n# Gank in our bundled libdisassemble\nimport opcode86\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/__init__.py",
"new_path": "vtrace/__init__.py",
"diff": "@@ -578,7 +578,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nnot only will the default be returned, but the key will\nbe set to the default specified.\n\"\"\"\n- if default != None:\n+ if default is not None:\nif not self.metadata.has_key(name):\nself.metadata[name] = default\nreturn self.metadata.get(name, None)\n@@ -679,7 +679,7 @@ class Trace(e_mem.IMemory, e_reg.RegisterContext, e_resolv.SymbolResolver, objec\nbreakpoint.id = self.nextBpId()\naddr = breakpoint.resolveAddress(self)\n- if addr == None:\n+ if addr is None:\nself.bpbyid[breakpoint.id] = breakpoint\nself.deferred.append(breakpoint)\nreturn breakpoint.id\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/envitools.py",
"new_path": "vtrace/envitools.py",
"diff": "import sys\n-import traceback\nimport envi\n+import envi.memory as e_memory\nimport envi.archs.i386 as e_i386 # FIXME This should NOT have to be here\nclass RegisterException(Exception):\npass\ndef cmpRegs(emu, trace):\n- for idx,name in reg_map:\n+ for idx, name in reg_map: # TODO: Where is reg_map supposed to come from?\ner = emu.getRegister(idx)\ntr = trace.getRegisterByName(name)\nif er != tr:\n@@ -26,6 +26,9 @@ def emuFromTrace(trace):\n# could use {get,set}MemorySnap if trace inherited from MemoryObject\nfor va, size, perms, fname in trace.getMemoryMaps():\ntry:\n+ # So linux maps in a PROT_NONE page for efficient library sharing, so we have to take that into account\n+ if (not perms & e_memory.MM_READ) and trace.getMeta('Platform') == 'linux':\n+ continue\nbytez = trace.readMemory(va, size)\nemu.addMemoryMap(va, perms, fname, bytez)\nexcept vtrace.PlatformException:\n@@ -42,20 +45,21 @@ def emuFromTrace(trace):\ndef lockStepEmulator(emu, trace):\nwhile True:\n- print \"Lockstep: 0x%.8x\" % emu.getProgramCounter()\n+ print(\"Lockstep: 0x%.8x\" % emu.getProgramCounter())\ntry:\npc = emu.getProgramCounter()\nop = emu.parseOpcode(pc)\ntrace.stepi()\nemu.stepi()\ncmpRegs(emu, trace)\n- except RegisterException, msg:\n- print \"Lockstep Error: %s: %s\" % (repr(op),msg)\n- setRegs(emu, trace)\n+ except RegisterException as msg:\n+ print(\"Lockstep Error: %s: %s\" % (repr(op), msg))\n+ setRegs(emu, trace) # TODO: Where is this from?\nsys.stdin.readline()\n- except Exception, msg:\n+ except Exception as msg:\n+ import traceback\ntraceback.print_exc()\n- print \"Lockstep Error: %s\" % msg\n+ print(\"Lockstep Error: %s\" % msg)\nreturn\nimport vtrace\n@@ -109,7 +113,7 @@ class TraceEmulator(vtrace.Trace, v_base.TracerBase):\nreturn self.emu.getMemoryMaps()\ndef platformGetThreads(self):\n- return {1:0xffff0000,}\n+ return {1: 0xffff0000}\ndef platformGetFds(self):\nreturn [] # FIXME perhaps tie this into magic?\n@@ -133,7 +137,7 @@ def main():\nt.run()\nsnap = t.takeSnapshot()\n# snap.saveToFile(\"woot.snap\") # You may open in vdb to follow along\n- emu = emulatorFromTrace(snap)\n+ emu = emuFromTrace(snap)\nlockStepEmulator(emu, t)\nif __name__ == \"__main__\":\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/base.py",
"new_path": "vtrace/platforms/base.py",
"diff": "@@ -327,12 +327,12 @@ class TracerBase(vtrace.Notifier):\ndef __del__(self):\nif not self._released:\n- print 'Warning! tracer del w/o release()!'\n+ print('Warning! tracer del w/o release()!')\ndef fireTracerThread(self):\n# Fire the threadwrap proxy thread for this tracer\n# (if it hasnt been fired...)\n- if self.thread == None:\n+ if self.thread is None:\nself.thread = TracerThread()\ndef fireNotifiers(self, event):\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/linux.py",
"new_path": "vtrace/platforms/linux.py",
"diff": "@@ -318,7 +318,7 @@ class LinuxMixin(v_posix.PtraceMixin, v_posix.PosixMixin):\nos.kill(os.getpid(), signal.SIGSTOP)\nos.execv(cmdlist[0], cmdlist)\nexcept Exception as e:\n- print e\n+ print(e)\nsys.exit(-1)\n# Attach to child. should cause SIGSTOP\n@@ -468,7 +468,8 @@ class LinuxMixin(v_posix.PtraceMixin, v_posix.PosixMixin):\nfor ptrace.\n\"\"\"\nopts = PT_O_TRACESYSGOOD\n- if platform.release()[:3] in ('2.6','3.0','3.1','3.2'):\n+ ver = tuple(platform.release()[:3].split('.'))\n+ if (int(ver[0]), int(ver[1])) >= (2, 6):\nopts |= PT_O_TRACECLONE | PT_O_TRACEEXIT\nx = v_posix.ptrace(PT_SETOPTIONS, tid, 0, opts)\nif x != 0:\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/posix.py",
"new_path": "vtrace/platforms/posix.py",
"diff": "@@ -88,7 +88,7 @@ class PosixMixin:\nself.handlePosixSignal(sig)\nelse:\n- print \"OMG WTF JUST HAPPENED??!?11/!?1?>!\"\n+ print(\"OMG WTF JUST HAPPENED??!?11/!?1?>!\")\ndef handlePosixSignal(self, sig):\n\"\"\"\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/tests/testthread.py",
"new_path": "vtrace/tests/testthread.py",
"diff": "import os\n-import time\n-import unittest\nimport vtrace\nimport vtrace.tests as vt_tests\n@@ -26,13 +24,10 @@ class VtraceThreadTest(vt_tests.VtraceProcessTest):\npypath = os.path.join('vtrace','tests','mains','mainthreads.py')\ndef test_vtrace_threads(self):\n- #if self.trace.getMeta('Platform') not in ('windows',):\n- #raise unittest.SkipTest('Thread Catching Fails...')\n-\nn = ThreadNotifier()\nself.trace.registerNotifier(vtrace.NOTIFY_ALL, n)\nself.runUntilExit()\n- self.assertTrue(n.threadexit)\nself.assertTrue(n.threadcreate)\n+ self.assertTrue(n.threadexit)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Another unittest works. One left I think
|
718,765 |
20.03.2019 14:39:26
| 14,400 |
34065ddbc4557c58c8e905f9a1c587e8e5d6ecee
|
It's a bit hacky, but all the tests pass now
|
[
{
"change_type": "MODIFY",
"old_path": "vtrace/envitools.py",
"new_path": "vtrace/envitools.py",
"diff": "@@ -8,11 +8,12 @@ class RegisterException(Exception):\npass\ndef cmpRegs(emu, trace):\n- for idx, name in reg_map: # TODO: Where is reg_map supposed to come from?\n+ ctx = trace.getRegisterContext()\n+ for rname, idx in ctx.getRegisterNameIndexes():\ner = emu.getRegister(idx)\n- tr = trace.getRegisterByName(name)\n+ tr = trace.getRegisterByName(rname)\nif er != tr:\n- raise RegisterException(\"REGISTER MISMATCH: %s 0x%.8x 0x%.8x\" % (name, tr, er))\n+ raise RegisterException(\"REGISTER MISMATCH: %s 0x%.8x 0x%.8x\" % (rname, tr, er))\nreturn True\ndef emuFromTrace(trace):\n@@ -20,6 +21,7 @@ def emuFromTrace(trace):\nProduce an envi emulator for this tracer object.\n'''\narch = trace.getMeta('Architecture')\n+ plat = trace.getMeta('Platform')\namod = envi.getArchModule(arch)\nemu = amod.getEmulator()\n@@ -27,7 +29,9 @@ def emuFromTrace(trace):\nfor va, size, perms, fname in trace.getMemoryMaps():\ntry:\n# So linux maps in a PROT_NONE page for efficient library sharing, so we have to take that into account\n- if (not perms & e_memory.MM_READ) and trace.getMeta('Platform') == 'linux':\n+ if (not perms & e_memory.MM_READ):\n+ continue\n+ if plat == 'linux' and fname in ['[vvar]']:\ncontinue\nbytez = trace.readMemory(va, size)\nemu.addMemoryMap(va, perms, fname, bytez)\n@@ -38,7 +42,7 @@ def emuFromTrace(trace):\nrsnap = trace.getRegisterContext().getRegisterSnap()\nemu.setRegisterSnap(rsnap)\n- if trace.getMeta('Platform') == 'windows':\n+ if plat == 'windows':\nemu.setSegmentInfo(e_i386.SEG_FS, trace.getThreads()[trace.getMeta('ThreadId')], 0xffffffff)\nreturn emu\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/linux.py",
"new_path": "vtrace/platforms/linux.py",
"diff": "@@ -253,8 +253,8 @@ class LinuxMixin(v_posix.PtraceMixin, v_posix.PosixMixin):\n\"\"\"\nA utility to open (if necessary) and seek the memfile\n\"\"\"\n- if self.memfd == None:\n- self.memfd = libc.open(\"/proc/%d/mem\" % self.pid, O_RDWR | O_LARGEFILE, 0755)\n+ if self.memfd is None:\n+ self.memfd = libc.open(\"/proc/%d/mem\" % self.pid, O_RDWR | O_LARGEFILE, 755)\nx = libc.lseek64(self.memfd, offset, 0)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
It's a bit hacky, but all the tests pass now
|
718,765 |
25.03.2019 12:19:19
| 14,400 |
0b69b648d81b4f67fc3c61921d3fdf9a3848fd90
|
Flake8. Fix exception 'long object has not attribute kids' for gcc-7 binary. Add coveragerc for getting code coverage and update gitignore
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": ".coveragerc",
"diff": "+[run]\n+branch=True\n+\n+[report]\n+omit =\n+ */vdb/qt/*\n+ */envi/qt/*\n+ */vstruct/qt/*\n+ */vivisect/qt/*\n+ */visgraph/drawing/*\n+ */vdb/tests/__init__.py\n+ */vdb/tests/teststalker.py*\n+ */vtrace/qt.py\n+ */vivisect/symboliks/tests/__init__.py\n+ */vivisect/symboliks/tests/test*\n+ */vivisect/tests/__init__.py\n+ */vivisect/tests/test*\n+ */vivisect/tests/helpers.py\n+ */vivisect/tests/vivbins.py\n+ */vivisect/tests/samplecode.py\n+ */vtrace/tests/*\n+ */envi/test_*\n+ */envi/tests/*\n+ */vdb/tests/*\n+ */visgraph/tests/__init__.py\n+ */visgraph/tests/test*\n+ */vivisect/contrib/*\n+ */PE/tests/__init__.py\n+ */PE/tests/test*\n+ */cobra/tests/__init__.py\n+ */cobra/tests/test*\n+ */vstruct/tests/__init__.py\n+ */vstruct/tests/test*\n+\n+[paths]\n+source =\n+ */vivisect/*\n+ */PE/*\n+ */Elf/*\n+ */vdb/*\n+ */vtrace/*\n+ */vstruct/*\n+ */visgraph/*\n+ */envi/*\n+ */cobra/*\n+\n+[html]\n+directory = coverage_html_report\n"
},
{
"change_type": "MODIFY",
"old_path": ".gitignore",
"new_path": ".gitignore",
"diff": "*.py~\n.hg*\n.idea\n+coverage_html_report*\n"
},
{
"change_type": "RENAME",
"old_path": "envi/tests_memory.py",
"new_path": "envi/tests/test_memmap.py",
"diff": ""
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/analysis.py",
"new_path": "vivisect/symboliks/analysis.py",
"diff": "@@ -162,7 +162,7 @@ class SymbolikFunctionEmulator(vsym_emulator.SymbolikEmulator):\nif self.cconv == None:\nraise Exception('Unknown CallingConvention (%s) for: 0x%.8x' % (ccname, fva))\n- if args == None:\n+ if args is None:\n# Initialize arguments by setting variables based on their arg indexes\nargc = len(self._sym_vw.getFunctionArgs(fva))\nargs = [Var('arg%d' % i, self.__width__) for i in xrange(argc)]\n@@ -209,9 +209,9 @@ class SymbolikFunctionEmulator(vsym_emulator.SymbolikEmulator):\nthunk = vw.getFunctionMeta(fva, 'Thunk')\napictx = self._sym_vw.getFunctionApi(fva)\n- if apictx == None:\n+ if apictx is None:\ndefcall = vw.getMeta(\"DefaultCall\")\n- if defcall == None:\n+ if defcall is None:\nraise Exception('No API context for function %x and DefaultCall metadata not set' % fva)\n# fake out 4 args\nargv = (('int', None), ('int', None), ('int', None), ('int', None))\n@@ -223,18 +223,18 @@ class SymbolikFunctionEmulator(vsym_emulator.SymbolikEmulator):\n# Either way, if we have a calling convention and a function def\n# lets parse out our arguments so the FofX() effect can have\n# more info\n- if cconv != None:\n+ if cconv is not None:\nsymargs = cconv.getSymbolikArgs(self, argv, update=True)\n# First of all, if the name of the function has a callback\nfunccb = self.getFunctionCallback(fname)\n- if funccb != None:\n+ if funccb is not None:\nfret = funccb(self, fname, symargs)\n# Next highest priority is \"thunks\" where there is a callback\n- elif thunk != None:\n+ elif thunk is not None:\nfunccb = self.getFunctionCallback(thunk)\n- if funccb != None:\n+ if funccb is not None:\nfret = funccb(self, thunk, symargs)\nelse:\n@@ -243,9 +243,9 @@ class SymbolikFunctionEmulator(vsym_emulator.SymbolikEmulator):\n# Attempt to use import api definitions...\napidef = self._sym_vw.getImpApi(funcname)\n- if apidef == None:\n+ if apidef is None:\ndefcall = vw.getMeta(\"DefaultCall\")\n- if defcall == None:\n+ if defcall is None:\nraise Exception('No API context for function %x and DefaultCall metadata not set' % fva)\n# fake out 4 args\nargv = (('int', None), ('int', None), ('int', None), ('int', None))\n@@ -256,17 +256,17 @@ class SymbolikFunctionEmulator(vsym_emulator.SymbolikEmulator):\ncconv = self.getCallingConvention(cc)\n# If we managed to get a calling convention *and* argument def...\n- if cconv != None and argv != None:\n+ if cconv is not None and argv is not None:\nsymargs = cconv.getSymbolikArgs(self, argv, update=True)\n# Give the function callback a shot...\nfunccb = self.getFunctionCallback(funcname)\n- if funccb != None:\n+ if funccb is not None:\nfret = funccb(self, funcname, symargs)\n# If we have a calling convention here, set the return state\n- if cconv != None:\n- if fret == None:\n+ if cconv is not None:\n+ if fret is None:\n# TODO: yuck. take ez way out and use width on emu.\n# should get return value def from cc and set width according\n# to width of that?\n@@ -371,9 +371,8 @@ class SymbolikAnalysisContext:\nis stored in 'symbolik_effects' list in the node properties.\n'''\nxlate = self.getTranslator()\n- graph = SymbolikFunctionGraph()\n- if fgraph == None:\n+ if fgraph is None:\nfgraph = viv_graph.buildFunctionGraph(self.vw, fva)\nfor nodeva, ninfo in fgraph.getNodes():\n@@ -399,7 +398,7 @@ class SymbolikAnalysisContext:\nfor coneff in conlist:\naddrva = coneff.addrsym.solve()\nclist = con_lookup.get(addrva)\n- if clist == None:\n+ if clist is None:\nclist = []\ncon_lookup[addrva] = clist\nclist.append(coneff)\n@@ -411,7 +410,7 @@ class SymbolikAnalysisContext:\n# Add the constraints to the edges\nfor eid, fromid, toid, einfo in fgraph.getRefsFromByNid(nodeva):\nclist = con_lookup.pop(toid, None)\n- if clist == None:\n+ if clist is None:\ncontinue\neinfo['symbolik_constraints'] = clist\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/amd64.py",
"new_path": "vivisect/symboliks/archs/amd64.py",
"diff": "-from envi.const import *\n+import hashlib\n+\nimport envi.archs.amd64 as e_amd64\n-from vivisect.symboliks.common import *\n+import vivisect.symboliks.common as vsym_common\nimport vivisect.symboliks.archs.i386 as vsym_i386\nimport vivisect.symboliks.analysis as vsym_analysis\nimport vivisect.symboliks.callconv as vsym_callconv\nfrom envi.archs.amd64.vmcslookup import VMCS_NAMES\n-class VMCS_Field (Var):\n+class VMCS_Field(vsym_common.Var):\ndef __init__(self, offset, width):\n- SymbolikBase.__init__(self)\n+ vsym_common.SymbolikBase.__init__(self)\nself.offset = offset\nself.width = width\n@@ -29,7 +30,7 @@ class VMCS_Field (Var):\ndef _solve(self, emu=None):\nname = 'vmcs%s' % self.offset\n- if emu != None:\n+ if emu is not None:\nname += emu.getRandomSeed()\nreturn long(hashlib.md5(name).hexdigest()[:self.width*2], 16)\n@@ -61,13 +62,13 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nridx = regidx & 0xffff\nrname = self._reg_ctx.getRegisterName(ridx)\nrbitwidth = self._reg_ctx.getRegisterWidth(ridx)\n- val = Var(rname, rbitwidth / 8 )\n+ val = vsym_common.Var(rname, rbitwidth / 8)\n# Translate to native if needed...\nif ridx != regidx:\n# 64 bit mode setting to 32bit regs, 0-extends to 64 bits\nif regidx == ridx | e_amd64.RMETA_LOW32:\n- val = Var(rname, 8)\n+ val = vsym_common.Var(rname, 8)\nelse:\n# we cannot call _xlateToNativReg since we'd pass in a symbolik\n# object that would trigger an or operation; the code in envi\n@@ -80,34 +81,32 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\n# cut hole in mask\nfinalmask = basemask ^ (mask << lshift)\nif lshift != 0:\n- obj <<= Const(lshift, rbitwidth / 8)\n+ obj <<= vsym_common.Const(lshift, rbitwidth / 8)\n- obj = obj | (val & Const(finalmask, rbitwidth / 8))\n+ obj = obj | (val & vsym_common.Const(finalmask, rbitwidth / 8))\nself.effSetVariable(rname, obj)\ndef getOperAddrObj(self, op, idx):\noper = op.opers[idx]\nif isinstance(oper, e_amd64.Amd64RipRelOper):\n- return Const(op.va + len(op) + oper.imm, 8)\n+ return vsym_common.Const(op.va + len(op) + oper.imm, 8)\nreturn vsym_i386.IntelSymbolikTranslator.getOperAddrObj(self, op, idx)\ndef getOperObj(self, op, idx):\noper = op.opers[idx]\nif isinstance(oper, e_amd64.Amd64RipRelOper):\n- return Mem( Const( op.va + len(op) + oper.imm, 8), Const(oper.tsize, 8))\n+ return vsym_common.Mem(vsym_common.Const(op.va + len(op) + oper.imm, 8), vsym_common.Const(oper.tsize, 8))\nreturn vsym_i386.IntelSymbolikTranslator.getOperObj(self, op, idx)\ndef i_movsxd(self, op):\ndsize = op.opers[0].tsize\nssize = op.opers[1].tsize\n- v2 = o_sextend( self.getOperObj(op,1), Const(ssize, self._psize))\n+ v2 = vsym_common.o_sextend(self.getOperObj(op, 1), vsym_common.Const(ssize, self._psize))\nself.setOperObj(op, 0, v2)\n-\n-\ndef i_div(self, op):\noper = op.opers[0]\ndenom = self.getOperObj(op, 1)\n@@ -116,9 +115,9 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nraise Exception('#DE, divide by zero')\nif oper.tsize == 8:\n- rax = Var('rax', self._psize)\n- rdx = Var('rdx', self._psize)\n- num = (rdx << Const(64, self._psize)) + rax\n+ rax = vsym_common.Var('rax', self._psize)\n+ rdx = vsym_common.Var('rdx', self._psize)\n+ num = (rdx << vsym_common.Const(64, self._psize)) + rax\ntemp = num / denom\nif temp > (2**64)-1:\n# TODO: make effect\n@@ -135,30 +134,30 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nreturn vsym_i386.IntelSymbolikTranslator.i_jecxz(self, op)\ndef i_jrcxz(self, op):\n- return self._cond_jmp(op, eq(Var('rcx', self._psize), Const(0, self._psize)))\n+ return self._cond_jmp(op, eq(vsym_common.Var('rcx', self._psize), vsym_common.Const(0, self._psize)))\ndef i_movsq(self, op):\n- si = Var(self.__srcp__, self._psize)\n- di = Var(self.__destp__, self._psize)\n- mem = Mem(si, Const(8))\n- self.effWriteMemory(di, Const(8, self._psize), mem)\n- self.effSetVariable(self.__srcp__, si + Const(8, self._psize))\n- self.effSetVariable(self.__destp__, di + Const(8, self._psize))\n+ si = vsym_common.Var(self.__srcp__, self._psize)\n+ di = vsym_common.Var(self.__destp__, self._psize)\n+ mem = vsym_common.Mem(si, vsym_common.Const(8))\n+ self.effWriteMemory(di, vsym_common.Const(8, self._psize), mem)\n+ self.effSetVariable(self.__srcp__, si + vsym_common.Const(8, self._psize))\n+ self.effSetVariable(self.__destp__, di + vsym_common.Const(8, self._psize))\ndef i_pushfd(self, op):\nsp = self.getRegObj(self._reg_ctx._rctx_spindex)\nsr = self.getRegObj(self._reg_ctx._rctx_srindex)\n- self.effSetVariable(self.__sp__, sp - Const(8, self._psize))\n- self.effWriteMemory(Var(self.__sp__, self._psize), Const(8, self._psize), sr)\n+ self.effSetVariable(self.__sp__, sp - vsym_common.Const(8, self._psize))\n+ self.effWriteMemory(vsym_common.Var(self.__sp__, self._psize), vsym_common.Const(8, self._psize), sr)\ndef i_vmread(self, op):\nvmcsoff = self.getOperObj(op, 1)\n- self.setOperObj(op, 0, LookupVar(\"VMCS\", vmcsoff, VMCS_NAMES, vmcsoff.getWidth()))\n+ self.setOperObj(op, 0, vsym_common.LookupVar(\"VMCS\", vmcsoff, VMCS_NAMES, vmcsoff.getWidth()))\ndef i_bt(self, op):\noper = self.getOperObj(op, 0)\nbit = self.getOperObj(op, 1)\n- cf = (oper >> bit) & Const(1, 1)\n+ cf = (oper >> bit) & vsym_common.Const(1, 1)\nself.effSetVariable('eflags_cf', cf)\ndef i_bts(self, op):\n@@ -166,11 +165,11 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nopersize = oper.getWidth()\nbit = self.getOperObj(op, 1)\nif bit.isDiscrete():\n- mask = Const(1 << bit.solve(), opersize)\n+ mask = vsym_common.Const(1 << bit.solve(), opersize)\nelse:\n- mask = Const(1, self._psize) << bit\n+ mask = vsym_common.Const(1, self._psize) << bit\nval = oper | mask\n- bitinfo = (oper >> bit) & Const(1, opersize)\n+ bitinfo = (oper >> bit) & vsym_common.Const(1, opersize)\nself.effSetVariable('eflags_cf', bitinfo)\nself.setOperObj(op, 0, val)\n@@ -180,11 +179,11 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nopersize = oper.getWidth()\nbit = self.getOperObj(op, 1)\nif bit.isDiscrete():\n- mask = Const(-1 ^ (1 << bit.solve()), opersize)\n+ mask = vsym_common.Const(-1 ^ (1 << bit.solve()), opersize)\nelse:\n- mask = Const(-1, opersize) ^ (Const(1, opersize) << bit)\n+ mask = vsym_common.Const(-1, opersize) ^ (vsym_common.Const(1, opersize) << bit)\nval = oper & mask\n- bitinfo = (oper >> bit) & Const(1, opersize)\n+ bitinfo = (oper >> bit) & vsym_common.Const(1, opersize)\nself.effSetVariable('eflags_cf', bitinfo)\nself.setOperObj(op, 0, val)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "-import sys\n-\nimport envi\nimport envi.bits as e_bits\nimport envi.registers as e_registers\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/callconv.py",
"new_path": "vivisect/symboliks/callconv.py",
"diff": "@@ -25,7 +25,7 @@ class SymbolikCallingConvention(object):\nfofx effects...\n'''\nargs = self.getPreCallArgs(self.argdefemu, len(argv))\n- if update == True:\n+ if update:\nargs = [arg.update(emu) for arg in args]\nreturn args\n@@ -65,7 +65,7 @@ class SymbolikCallingConvention(object):\nstate introduced by our callee.\nExample:\n- cconv.setSymbolikReturn(emu, Var('foo', self._psize),\n+ cconv.setSymbolikReturn(emu, Var('foo', self._psize))\n'''\n# TODO: consider renaming func name (see new envi cc stuff)\n# we could get more re-use here if we plumb/snap in methods that map\n@@ -77,7 +77,7 @@ class SymbolikCallingConvention(object):\nrname = self.argdefemu.xlator._reg_ctx.getRegisterName(aval)\nemu.setSymVariable(rname, sym)\n- spdelta = self.deallocateCallSpace(self.argdefemu, len(argv), precall=precall)\n+ spdelta = self.deallocateCallSpace(self.argdefemu, Const(len(argv), self._width), precall=precall)\nspidx = self.argdefemu.xlator._reg_ctx._rctx_spindex\nspname = self.argdefemu.xlator._reg_ctx.getRegisterName(spidx)\n@@ -91,4 +91,3 @@ class SymbolikCallingConvention(object):\nrname = self.argdefemu.xlator._reg_ctx.getRegisterName(aval)\nreturn emu.getSymVariable(rname)\n-\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/common.py",
"new_path": "vivisect/symboliks/common.py",
"diff": "@@ -241,7 +241,12 @@ class SymbolikBase:\n'''\nif idx > len(self.kids)-1:\nself.kids.append(kid)\n+ try:\nself.kids[idx].parents.append(self)\n+ except:\n+ import pdb\n+ pdb.set_trace()\n+ print(\"WAT\")\nelse:\n# kid already exists\noldkid = self.kids[idx]\n@@ -802,7 +807,7 @@ class Operator(SymbolikBase):\n@symcache\ndef __str__(self):\n- if self.operstr == None:\n+ if self.operstr is None:\nraise Exception('Operators *must* set operstr')\nx,y = self.kids\nreturn '(%s %s %s)' % (str(x), self.operstr, str(y))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_analysis.py",
"new_path": "vivisect/symboliks/tests/test_analysis.py",
"diff": "+import sys\nimport unittest\nimport vivisect.symboliks.analysis as vsym_analysis\n@@ -40,14 +41,13 @@ class AnalysisTests(unittest.TestCase):\nself.assertIs(offset, None)\n-import sys\nimport vivisect.tests.vivbins as vivbins\n-from vivisect.tests.vivbins import getTestWorkspace, getAnsWorkspace\n+from vivisect.tests.vivbins import getAnsWorkspace\ndef cb_astNodeCount(path, obj, ctx):\nctx['count'] += 1\nif len(path) > ctx['depth']:\nctx['depth'] = len(path)\n- #print \"\\n\\t%r\\n\\t\\t%s\" % (obj, '\\n\\t\\t'.join([repr(x) for x in path]))\n+ # print(\"\\n\\t%r\\n\\t\\t%s\" % (obj, '\\n\\t\\t'.join([repr(x) for x in path])))\nclass WalkTreeTest(unittest.TestCase):\n@@ -63,11 +63,10 @@ class WalkTreeTest(unittest.TestCase):\ntry:\nvw = getAnsWorkspace('test_elf_i386')\nwalkTreeDoer(vw)\n- except Exception as e:\n+ except Exception:\nsys.excepthook(*sys.exc_info())\n-\ndef walkTreeDoer(vw):\nsctx = vsym_analysis.getSymbolikAnalysisContext(vw)\n@@ -84,24 +83,24 @@ def walkTreeDoer(vw):\ncontinue\neff = effs[-1]\n- #print \"=====\\n %r \\n=====\" % (eff)\n+ # print(\"=====\\n %r \\n=====\" % (eff))\n# this is ugly\nsymast = getattr(eff, 'symobj', None)\n- if symast == None:\n+ if symast is None:\nsymast = getattr(eff, 'addrsym', None)\n- if symast == None:\n+ if symast is None:\nsymast = getattr(eff, 'cons', None)\n- if symast == None:\n+ if symast is None:\nsymast = getattr(eff, 'funcsym', None)\n- if symast == None:\n+ if symast is None:\nsymast = getattr(eff, 'argsyms', None)\n- if symast == None:\n+ if symast is None:\nsymast = getattr(eff, 'symaddr', None)\n- if symast == None:\n+ if symast is None:\nsymast = getattr(eff, 'symval', None)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/translator.py",
"new_path": "vivisect/symboliks/translator.py",
"diff": "@@ -45,14 +45,14 @@ class SymbolikTranslator:\ndef translateOpcode(self, op):\nself._cur_va = op.va\nmeth = self._op_methods.get(op.mnem, None)\n- if meth == None:\n- #print '%s Needs: %s' % (self.__class__.__name__,repr(op))\n+ if meth is None:\n+ print('%s Needs: %s' % (self.__class__.__name__,repr(op)))\nself.effDebug(\"%s Needs %s\" % (self.__class__.__name__, repr(op)))\nreturn DebugEffect(op.va, \"%s Needs %s\" % (self.__class__.__name__, repr(op)))\n# instruction translator methods may return branches / constraints\nret = meth(op)\n- if ret != None:\n+ if ret is not None:\nfor symaddr, symcons in ret:\nself.effConstrain(symaddr, symcons)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Flake8. Fix exception 'long object has not attribute kids' for gcc-7 binary. Add coveragerc for getting code coverage and update gitignore
|
718,765 |
26.03.2019 15:15:44
| 14,400 |
a179a88c69e4d3851bd530f6ea213d893bbd04b3
|
Even more flake8 and more instructions plumbed through symboliks
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -903,8 +903,6 @@ class Emulator(e_reg.RegisterContext, e_mem.MemoryObject):\nreturn res\n-\n-\nclass CallingConvention(object):\n'''\nBase class for all calling conventions. You must define class locals that\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/__init__.py",
"new_path": "envi/archs/amd64/__init__.py",
"diff": "@@ -132,4 +132,3 @@ class Amd64Emulator(Amd64RegisterContext, e_i386.IntelEmulator):\ni_movntps = e_i386.IntelEmulator.i_mov\ni_movntdq = e_i386.IntelEmulator.i_mov\ni_movntdqa = e_i386.IntelEmulator.i_mov\n-\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/disasm.py",
"new_path": "envi/archs/amd64/disasm.py",
"diff": "@@ -37,8 +37,6 @@ amd64_prefixes[0xc4] = (0x40 << 16) # VEX 3byte\nmandatory_prefixes = [0x66, 0xf2, 0xf3]\n-\n-\n# NOTE: some notes from the intel manual...\n# REX.W overrides 66, but alternate registers (via REX.B etc..) can have 66 to be 16 bit..\n# REX.R only modifies reg for GPR/SSE(SIMD)/ctrl/debug addressing modes.\n@@ -114,9 +112,10 @@ class Amd64RipRelOper(envi.DerefOper):\nself._is_deref = True\ndef getOperValue(self, op, emu=None):\n- if self._is_deref == False: # Special lea behavior\n+ if not self._is_deref: # Special lea behavior\nreturn self.getOperAddr(op)\n- if emu == None: return None\n+ if emu is None:\n+ return None\nreturn emu.readMemValue(self.getOperAddr(op, emu), self.tsize)\ndef setOperValue(self, op, emu, val):\n@@ -197,7 +196,7 @@ class Amd64Disasm(e_i386.i386Disasm):\nmode = MODE_32\nsizelist = opcode86.OPERSIZE.get(opertype, None)\n- if sizelist == None:\n+ if sizelist is None:\nraise Exception(\"OPERSIZE FAIL\")\nif operflags & opcode86.OP_64AUTO:\n@@ -236,18 +235,18 @@ class Amd64Disasm(e_i386.i386Disasm):\n# This line changes in 64 bit mode\np = self._dis_prefixes[obyte]\n- if p == None:\n+ if p is None:\nbreak\n- #print \"OBYTE\",hex(obyte)\n+ # print(\"OBYTE\",hex(obyte))\nif obyte in mandatory_prefixes:\npho_prefixes |= p\n# ratchet through the tables\ntabidx = ((obyte - tabdesc[4]) >> tabdesc[2]) & tabdesc[3]\n- #print \"TABIDX: %d\" % tabidx\n+ # print(\"TABIDX: %d\" % tabidx)\nopdesc = tabdesc[0][tabidx]\n- #print 'OPDESC: %s -> %s' % (repr(opdesc), opcode86.tables_lookup.get(opdesc[0]))\n+ # print('OPDESC: %s -> %s' % (repr(opdesc), opcode86.tables_lookup.get(opdesc[0])))\ntabdesc = all_tables[opdesc[0]]\nelse:\nprefixes |= p\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "from envi.archs.i386.opconst import *\nimport regs as e_amd64_regs\n-\n-\n-\n# in order to be included, table name must be listed here.\ntablenames = [ None, # nexttable index 0 means NO TABLE!\n'tbl32_0F',\n@@ -271,12 +268,14 @@ tbl32_Main = [\n(0, INS_MOV, ADDRMETH_O | OPTYPE_b | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, e_amd64_regs.REG_AL, 0),\n(0, INS_MOV, ADDRMETH_O | OPTYPE_v | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, e_amd64_regs.REG_EAX, 0),\n(0, INS_STRMOV, 0, 0, 0, cpu_80386, \"movsb\", 0, 0, 0),\n+# Yes there should be movsw here, but it shares the same opcode as movsw, so skip it\n(0, INS_STRMOV, 0, 0, 0, cpu_80386, \"movsd\", 0, 0, 0),\n(0, INS_STRCMP, 0, 0, 0, cpu_80386, \"cmpsb\", 0, 0, 0),\n(0, INS_STRCMP, 0, 0, 0, cpu_80386, \"cmpsd\", 0, 0, 0),\n(0, INS_TEST, OP_REG | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, \"test\", e_amd64_regs.REG_AL, 0, 0),\n(0, INS_TEST, OP_REG | OP_R, ADDRMETH_I | OPTYPE_z | OP_R, ARG_NONE, cpu_80386, \"test\", e_amd64_regs.REG_EAX, 0, 0),\n(0, INS_STRSTOR, 0, 0, 0, cpu_80386, \"stosb\", 0, 0, 0),\n+# Yes there should be stosw here, but it shares the same opcode as stosd, so skip it\n(0, INS_STRSTOR, 0, 0, 0, cpu_80386, \"stosd\", 0, 0, 0),\n(0, INS_STRLOAD, 0, 0, 0, cpu_80386, \"lodsb\", 0, 0, 0),\n(0, INS_STRLOAD, 0, 0, 0, cpu_80386, \"lodsd\", 0, 0, 0),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/__init__.py",
"new_path": "envi/archs/i386/__init__.py",
"diff": "import envi\n-import envi.bits as e_bits\n#TODO\n# f0 0f c7 4d 00 75 f0 5d 5b - this is NOT right in disasm\n-import copy\n-import struct\n-import traceback\n-\n-# Gank in our bundled libdisassemble\n-import opcode86\n-\nfrom envi.archs.i386.regs import *\nfrom envi.archs.i386.disasm import *\n@@ -51,4 +43,3 @@ class i386Module(envi.ArchitectureModule):\n# NOTE: This one must be after the definition of i386Module\nfrom envi.archs.i386.emu import *\n-\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/disasm.py",
"new_path": "envi/archs/i386/disasm.py",
"diff": "@@ -821,7 +821,7 @@ class i386Disasm:\n# This line changes in 64 bit mode\np = self._dis_prefixes[obyte]\n- if p == None:\n+ if p is None:\nbreak\nif obyte == 0x66 and ord(bytez[offset+1]) == 0x0f:\nbreak\n@@ -862,7 +862,7 @@ class i386Disasm:\ncontinue\n# We are now on the final table...\n- #print repr(opdesc)\n+ # print(repr(opdesc))\nmnem = opdesc[6]\noptype = opdesc[1]\nif tabdesc[2] == 0xff:\n@@ -891,23 +891,22 @@ class i386Disasm:\nif operflags == 0:\nbreak\n- #print \"ADDRTYPE: %.8x OPERTYPE: %.8x\" % (addrmeth, opertype)\n+ # print(\"ADDRTYPE: %.8x OPERTYPE: %.8x\" % (addrmeth, opertype))\ntsize = self._dis_calc_tsize(opertype, prefixes, operflags)\n- #print hex(opertype),hex(addrmeth), hex(tsize)\n+ # print(hex(opertype),hex(addrmeth), hex(tsize))\n# If addrmeth is zero, we have operands embedded in the opcode\nif addrmeth == 0:\nosize = 0\noper = self.ameth_0(operflags, opdesc[5+i], tsize, prefixes)\n-\nelse:\n- #print \"ADDRTYPE\",hex(addrmeth)\n+ # print(\"ADDRTYPE\", hex(addrmeth))\nameth = self._dis_amethods[addrmeth >> 16]\n- #print \"AMETH\",ameth\n- if ameth == None:\n+ # print(\"AMETH\", ameth)\n+ if ameth is None:\nraise Exception(\"Implement Addressing Method 0x%.8x\" % addrmeth)\n# NOTE: Depending on your addrmethod you may get beginning of operands, or offset\n@@ -925,11 +924,11 @@ class i386Disasm:\nelse:\nosize, oper = ameth(bytez, offset, tsize, prefixes, operflags)\n- except struct.error, e:\n+ except struct.error as e:\n# Catch struct unpack errors due to insufficient data length\nraise envi.InvalidInstruction(bytez=bytez[startoff:startoff+16])\n- if oper != None:\n+ if oper is not None:\n# This is a filty hack for now...\noper._dis_regctx = self._dis_regctx\noperands.append(oper)\n@@ -967,7 +966,7 @@ class i386Disasm:\nimm = e_bits.parsebytes(bytez, offset, tsize)\n# seg = e_bits.parsebytes(bytez, offset+tsize, 2)\n# THIS BEING GHETTORIGGED ONLY EFFECTS callf jmpf - unghettorigged by atlas\n- #print \"FIXME: envi.intel.ameth_a skipping seg prefix %d\" % seg\n+ # print(\"FIXME: envi.intel.ameth_a skipping seg prefix %d\" % seg)\nreturn (tsize, i386ImmOper(imm, tsize))\ndef ameth_e(self, bytez, offset, tsize, prefixes, operflags):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opconst.py",
"new_path": "envi/archs/i386/opconst.py",
"diff": "@@ -111,8 +111,8 @@ INS_CALL = INS_EXEC | 0x03\nINS_CALLCC = INS_EXEC | 0x04\nINS_RET = INS_EXEC | 0x05\nINS_LOOP = INS_EXEC | 0x06\n-\nINS_ADD= INS_ARITH | 0x01\n+\nINS_SUB= INS_ARITH | 0x02\nINS_MUL= INS_ARITH | 0x03\nINS_DIV= INS_ARITH | 0x04\n@@ -140,8 +140,8 @@ INS_LEAVE = INS_STACK | 0x08\nINS_TEST = INS_COND | 0x01\nINS_CMP = INS_COND | 0x02\n-\nINS_MOV = INS_LOAD | 0x01\n+\nINS_MOVCC = INS_LOAD | 0x02\nINS_XCHG = INS_LOAD | 0x03\nINS_XCHGCC = INS_LOAD | 0x04\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/msp430/emu.py",
"new_path": "envi/archs/msp430/emu.py",
"diff": "@@ -10,8 +10,7 @@ from envi.archs.msp430.const import *\nclass Msp430Call(envi.CallingConvention):\n- arg_def = [(CC_REG, REG_R15), (CC_REG, REG_R14), (CC_REG, REG_R13), (CC_REG, REG_R12),\n- (CC_STACK_INF, 2)]\n+ arg_def = [(CC_REG, REG_R15), (CC_REG, REG_R14), (CC_REG, REG_R13), (CC_REG, REG_R12), (CC_STACK_INF, 2)]\nretaddr_def = (CC_STACK, 0)\nretval_def = (CC_REG, REG_R15)\nflags = CC_CALLEE_CLEANUP\n@@ -29,7 +28,7 @@ class Msp430Emulator(Msp430RegisterContext, envi.Emulator):\nenvi.Emulator.__init__(self, self.archmod)\nMsp430RegisterContext.__init__(self)\n- self._emu_segments = [ (0, 0xffff), ]\n+ self._emu_segments = [(0, 0xffff)]\nself.addCallingConvention('msp430call', msp430call)\ndef getArchModule(self):\n@@ -37,18 +36,19 @@ class Msp430Emulator(Msp430RegisterContext, envi.Emulator):\ndef setFlag(self, which, state):\nflags = self.getRegister(REG_SR)\n- if flags == None:\n+ if flags is None:\nraise envi.PDEUndefinedFlag(self)\nif state:\nflags |= which\nelse:\nflags &= ~which\n+\nself.setRegister(REG_SR, flags)\ndef getFlag(self, which):\nflags = self.getRegister(REG_SR)\n- if flags == None:\n+ if flags is None:\nraise envi.PDEUndefinedFlag(self)\nreturn bool(flags & which)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_memmap.py",
"new_path": "envi/tests/test_memmap.py",
"diff": "@@ -12,8 +12,7 @@ class Memory(unittest.TestCase):\n# gap\n(0x2000, envi.memory.MM_READ, None, 0x100 * '\\x43'),\n(0x2100, envi.memory.MM_NONE, None, 0x1000 * '\\x44'),\n- (0x3100, envi.memory.MM_READ, None, 0x200 * '\\x45'),\n- ]\n+ (0x3100, envi.memory.MM_READ, None, 0x200 * '\\x45')]\n# reverse the list just to make sure we aren't making assumptions\n# about ascending order.\n@@ -32,8 +31,7 @@ class Memory(unittest.TestCase):\n(0x2150, 0),\n(0xffff, 0), # last va in map\n(0x2fff, 0), # last va in map\n- (0x123456789, 0) # no mans land.\n- ]\n+ (0x123456789, 0)] # no mans land.\nfor va, answer in answers:\nsize = self.mem.getMaxReadSize(va)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -152,7 +152,7 @@ class WorkspaceEmulator:\n# We can make an opcode *faster* with the workspace because of\n# getByteDef etc... use it.\nop = self.opcache.get(va)\n- if op == None:\n+ if op is None:\nop = envi.Emulator.parseOpcode(self, va, arch=arch)\nself.opcache[va] = op\nreturn op\n@@ -170,21 +170,18 @@ class WorkspaceEmulator:\nargv = callconv.getCallArgs(self, len(funcargs))\nret = None\n- if self.emumon != None:\n+ if self.emumon is not None:\ntry:\nret = self.emumon.apicall(self, op, endeip, api, argv)\n- except Exception, e:\n+ except Exception as e:\nself.emumon.logAnomaly(self, endeip, \"%s.apicall failed: %s\" % (self.emumon.__class__.__name__, e))\nhook = self.hooks.get(callname)\n- if ret == None and hook:\n+ if ret is None and hook:\nhook(self, callconv, api, argv)\n-\nelse:\n-\n- if ret == None:\n+ if ret is None:\nret = self.setVivTaint('apicall', (op, endeip, api, argv))\n-\ncallconv.execCallReturn(self, ret, len(funcargs))\n# Either way, if it's a call PC goes to next instruction\n@@ -234,8 +231,8 @@ class WorkspaceEmulator:\n# If there is more than one branch target, we need a new code block\nif len(blist) > 1:\nfor bva, bflags in blist:\n- if bva == None:\n- print \"Unresolved branch even WITH an emulator?\"\n+ if bva is None:\n+ print(\"Unresolved branch even WITH an emulator?\")\ncontinue\nbpath = self.getBranchNode(self.curpath, bva)\n@@ -278,7 +275,7 @@ class WorkspaceEmulator:\nvg_path.setNodeProp(self.curpath, 'bva', funcva)\nhits = {}\n- todo = [(funcva,self.getEmuSnap(),self.path),]\n+ todo = [(funcva, self.getEmuSnap(), self.path)]\nvw = self.vw # Save a dereference many many times\nwhile len(todo):\n@@ -290,7 +287,7 @@ class WorkspaceEmulator:\nself.setProgramCounter(va)\n# Check if we are beyond our loop max...\n- if maxloop != None:\n+ if maxloop is not None:\nlcount = vg_path.getPathLoopCount(self.curpath, 'bva', va)\nif lcount > maxloop:\ncontinue\n@@ -306,7 +303,7 @@ class WorkspaceEmulator:\nreturn\n# Check straight hit count...\n- if maxhit != None:\n+ if maxhit is not None:\nh = hits.get(starteip, 0)\nh += 1\nif h > maxhit:\n@@ -315,7 +312,7 @@ class WorkspaceEmulator:\n# If we ran out of path (branches that went\n# somewhere that we couldn't follow?\n- if self.curpath == None:\n+ if self.curpath is None:\nbreak\ntry:\n@@ -360,15 +357,15 @@ class WorkspaceEmulator:\nif op.iflags & envi.IF_RET:\nvg_path.setNodeProp(self.curpath, 'cleanret', True)\nbreak\n- except envi.UnsupportedInstruction, e:\n+ except envi.UnsupportedInstruction as e:\nif self.strictops:\nbreak\nelse:\n- print 'runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\n+ print('runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem))\nself.setProgramCounter(e.op.va + e.op.size)\n- except Exception, e:\n+ except Exception as e:\n# traceback.print_exc()\n- if self.emumon != None:\n+ if self.emumon is not None:\nself.emumon.logAnomaly(self, starteip, str(e))\nbreak # If we exc during execution, this branch is dead.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/amd64.py",
"new_path": "vivisect/symboliks/archs/amd64.py",
"diff": "@@ -2,15 +2,15 @@ import hashlib\nimport envi.archs.amd64 as e_amd64\n-import vivisect.symboliks.common as vsym_common\n+from vivisect.symboliks.common import *\nimport vivisect.symboliks.archs.i386 as vsym_i386\nimport vivisect.symboliks.analysis as vsym_analysis\nimport vivisect.symboliks.callconv as vsym_callconv\nfrom envi.archs.amd64.vmcslookup import VMCS_NAMES\n-class VMCS_Field(vsym_common.Var):\n+class VMCS_Field(Var):\ndef __init__(self, offset, width):\n- vsym_common.SymbolikBase.__init__(self)\n+ SymbolikBase.__init__(self)\nself.offset = offset\nself.width = width\n@@ -62,13 +62,13 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nridx = regidx & 0xffff\nrname = self._reg_ctx.getRegisterName(ridx)\nrbitwidth = self._reg_ctx.getRegisterWidth(ridx)\n- val = vsym_common.Var(rname, rbitwidth / 8)\n+ val = Var(rname, rbitwidth / 8)\n# Translate to native if needed...\nif ridx != regidx:\n# 64 bit mode setting to 32bit regs, 0-extends to 64 bits\nif regidx == ridx | e_amd64.RMETA_LOW32:\n- val = vsym_common.Var(rname, 8)\n+ val = Var(rname, 8)\nelse:\n# we cannot call _xlateToNativReg since we'd pass in a symbolik\n# object that would trigger an or operation; the code in envi\n@@ -81,30 +81,30 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\n# cut hole in mask\nfinalmask = basemask ^ (mask << lshift)\nif lshift != 0:\n- obj <<= vsym_common.Const(lshift, rbitwidth / 8)\n+ obj <<= Const(lshift, rbitwidth / 8)\n- obj = obj | (val & vsym_common.Const(finalmask, rbitwidth / 8))\n+ obj = obj | (val & Const(finalmask, rbitwidth / 8))\nself.effSetVariable(rname, obj)\ndef getOperAddrObj(self, op, idx):\noper = op.opers[idx]\nif isinstance(oper, e_amd64.Amd64RipRelOper):\n- return vsym_common.Const(op.va + len(op) + oper.imm, 8)\n+ return Const(op.va + len(op) + oper.imm, 8)\nreturn vsym_i386.IntelSymbolikTranslator.getOperAddrObj(self, op, idx)\ndef getOperObj(self, op, idx):\noper = op.opers[idx]\nif isinstance(oper, e_amd64.Amd64RipRelOper):\n- return vsym_common.Mem(vsym_common.Const(op.va + len(op) + oper.imm, 8), vsym_common.Const(oper.tsize, 8))\n+ return Mem(Const(op.va + len(op) + oper.imm, 8), Const(oper.tsize, 8))\nreturn vsym_i386.IntelSymbolikTranslator.getOperObj(self, op, idx)\ndef i_movsxd(self, op):\ndsize = op.opers[0].tsize\nssize = op.opers[1].tsize\n- v2 = vsym_common.o_sextend(self.getOperObj(op, 1), vsym_common.Const(ssize, self._psize))\n+ v2 = o_sextend(self.getOperObj(op, 1), Const(ssize, self._psize))\nself.setOperObj(op, 0, v2)\ndef i_div(self, op):\n@@ -115,9 +115,9 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nraise Exception('#DE, divide by zero')\nif oper.tsize == 8:\n- rax = vsym_common.Var('rax', self._psize)\n- rdx = vsym_common.Var('rdx', self._psize)\n- num = (rdx << vsym_common.Const(64, self._psize)) + rax\n+ rax = Var('rax', self._psize)\n+ rdx = Var('rdx', self._psize)\n+ num = (rdx << Const(64, self._psize)) + rax\ntemp = num / denom\nif temp > (2**64)-1:\n# TODO: make effect\n@@ -134,30 +134,22 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nreturn vsym_i386.IntelSymbolikTranslator.i_jecxz(self, op)\ndef i_jrcxz(self, op):\n- return self._cond_jmp(op, eq(vsym_common.Var('rcx', self._psize), vsym_common.Const(0, self._psize)))\n-\n- def i_movsq(self, op):\n- si = vsym_common.Var(self.__srcp__, self._psize)\n- di = vsym_common.Var(self.__destp__, self._psize)\n- mem = vsym_common.Mem(si, vsym_common.Const(8))\n- self.effWriteMemory(di, vsym_common.Const(8, self._psize), mem)\n- self.effSetVariable(self.__srcp__, si + vsym_common.Const(8, self._psize))\n- self.effSetVariable(self.__destp__, di + vsym_common.Const(8, self._psize))\n+ return self._cond_jmp(op, eq(Var('rcx', self._psize), Const(0, self._psize)))\ndef i_pushfd(self, op):\nsp = self.getRegObj(self._reg_ctx._rctx_spindex)\nsr = self.getRegObj(self._reg_ctx._rctx_srindex)\n- self.effSetVariable(self.__sp__, sp - vsym_common.Const(8, self._psize))\n- self.effWriteMemory(vsym_common.Var(self.__sp__, self._psize), vsym_common.Const(8, self._psize), sr)\n+ self.effSetVariable(self.__sp__, sp - Const(8, self._psize))\n+ self.effWriteMemory(Var(self.__sp__, self._psize), Const(8, self._psize), sr)\ndef i_vmread(self, op):\nvmcsoff = self.getOperObj(op, 1)\n- self.setOperObj(op, 0, vsym_common.LookupVar(\"VMCS\", vmcsoff, VMCS_NAMES, vmcsoff.getWidth()))\n+ self.setOperObj(op, 0, LookupVar(\"VMCS\", vmcsoff, VMCS_NAMES, vmcsoff.getWidth()))\ndef i_bt(self, op):\noper = self.getOperObj(op, 0)\nbit = self.getOperObj(op, 1)\n- cf = (oper >> bit) & vsym_common.Const(1, 1)\n+ cf = (oper >> bit) & Const(1, 1)\nself.effSetVariable('eflags_cf', cf)\ndef i_bts(self, op):\n@@ -165,11 +157,11 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nopersize = oper.getWidth()\nbit = self.getOperObj(op, 1)\nif bit.isDiscrete():\n- mask = vsym_common.Const(1 << bit.solve(), opersize)\n+ mask = Const(1 << bit.solve(), opersize)\nelse:\n- mask = vsym_common.Const(1, self._psize) << bit\n+ mask = Const(1, self._psize) << bit\nval = oper | mask\n- bitinfo = (oper >> bit) & vsym_common.Const(1, opersize)\n+ bitinfo = (oper >> bit) & Const(1, opersize)\nself.effSetVariable('eflags_cf', bitinfo)\nself.setOperObj(op, 0, val)\n@@ -179,11 +171,11 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nopersize = oper.getWidth()\nbit = self.getOperObj(op, 1)\nif bit.isDiscrete():\n- mask = vsym_common.Const(-1 ^ (1 << bit.solve()), opersize)\n+ mask = Const(-1 ^ (1 << bit.solve()), opersize)\nelse:\n- mask = vsym_common.Const(-1, opersize) ^ (vsym_common.Const(1, opersize) << bit)\n+ mask = Const(-1, opersize) ^ (Const(1, opersize) << bit)\nval = oper & mask\n- bitinfo = (oper >> bit) & vsym_common.Const(1, opersize)\n+ bitinfo = (oper >> bit) & Const(1, opersize)\nself.effSetVariable('eflags_cf', bitinfo)\nself.setOperObj(op, 0, val)\n@@ -229,6 +221,15 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\ni_cmovz = i_cmove\ni_cmovnz = i_cmovne\n+ def i_movsq(self, op):\n+ return self._movs(op, width=8)\n+\n+ def i_stosq(self, op):\n+ return self._stos(op, width=8)\n+\n+ def i_cmpsq(self, op):\n+ return self._cmps(op, width=8)\n+\nclass Amd64ArgDefSymEmu(vsym_i386.ArgDefSymEmu):\n__xlator__ = Amd64SymbolikTranslator\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "import envi\nimport envi.bits as e_bits\n-import envi.registers as e_registers\nimport envi.archs.i386 as e_i386\n+import envi.archs.i386.opconst as i386_opconst\nimport vivisect.symboliks.analysis as vsym_analysis\nimport vivisect.symboliks.callconv as vsym_callconv\n-import vivisect.symboliks.emulator as vsym_emulator\nimport vivisect.symboliks.translator as vsym_trans\nfrom vivisect.const import *\n@@ -224,7 +223,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\naddrsym = self.getOperAddrObj(op, idx)\nreturn self.effWriteMemory(addrsym, Const(oper.tsize, self._psize), obj)\n- raise Exception('Umm..... really?')\n+ raise Exception('setOperObj failed')\ndef __get_dest_maxes(self, op):\ntsize = op.opers[0].tsize\n@@ -441,10 +440,8 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\ndef _cond_jmp(self, op, cond):\n# Construct the tuple for the conditional jump\n- return (\n- ( self.getOperObj(op, 0), cond ),\n- ( Const(op.va + len(op), self._psize), cnot(cond)),\n- )\n+ return ((self.getOperObj(op, 0), cond ),\n+ (Const(op.va + len(op), self._psize), cnot(cond)))\ndef i_jg(self, op):\nreturn self._cond_jmp(op, Var('eflags_gt', self._psize))\n@@ -521,32 +518,31 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\no = self.getOperObj(op, 1)\nself.setOperObj(op, 0, o)\n- def i_movsb(self, op):\n+ def _movs(self, op, width=-1):\nsi = Var(self.__srcp__, self._psize)\ndi = Var(self.__destp__, self._psize)\n- mem = Mem(si, Const(1, self._psize))\n- self.effWriteMemory(di, Const(1, self._psize), mem)\n- self.effSetVariable(self.__srcp__, si + Const(1, self._psize))\n- self.effSetVariable(self.__destp__, di + Const(1, self._psize))\n+ mem = Mem(si, Const(width, self._psize))\n+ self.effWriteMemory(di, Const(width, self._psize), mem)\n+ # XXX: So...in reality these could be + or - depending on\n+ # what is in the DF flag in the EFLAGS register. But that's a\n+ # conditional and we're in symboliks town, so...whiff past that for now\n+ self.effSetVariable(self.__srcp__, si + Const(width, self._psize))\n+ self.effSetVariable(self.__destp__, di + Const(width, self._psize))\n+\n+ # TODO: When we move to python 3.4 or greater, we can change these to just\n+ # functools.partialmethod. Cleaner that way\n+ def i_movsb(self, op):\n+ return self._movs(op, width=1)\ndef i_movsd(self, op):\n- si = Var(self.__srcp__, self._psize)\n- di = Var(self.__destp__, self._psize)\n- mem = Mem(si, Const(4, self._psize))\n- self.effWriteMemory(di, Const(4, self._psize), mem)\n-\n- # FIXME *symbolic* flags!\n- #if self.getFlag(EFLAGS_DF):\n- #esi -= 4\n- #edi -= 4\n-\n- #else:\n- #esi += 4\n- #edi += 4\n- #print 'FIXME how to handle DF bit?'\n-\n- self.effSetVariable(self.__srcp__, si + Const(4, self._psize))\n- self.effSetVariable(self.__destp__, di + Const(4, self._psize))\n+ # Unfortunately, these have the same mnemonic\n+ if op.opcode & i386_opconst.INS_STRMOV:\n+ # Since x86 doesn't differentiate movsw and movsd via opcode, we could try to infer it via the operators,\n+ # but those are for documention only (and even intel says those could be nothing but lies), so just go with\n+ # the default for now\n+ return self._movs(op, width=4)\n+ else:\n+ return self.i_mov(op)\ndef i_movsx(self, op):\ndsize = op.opers[0].tsize\n@@ -801,6 +797,36 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\ndata = self.getOperObj(op, 1)\nself.setOperObj(op, 0, data)\n+ def _stos(self, op, width=-1):\n+ # FIXME omg segments in symboliks?\n+ # base, size = self.segments[SEG_ES]\n+ di = Var(self.__destp__, self._psize)\n+ self.effWriteMemory(di, Const(self._psize, self._psize), Var('eax', self._psize))\n+ self.effSetVariable(self.__destp__, di + Const(width, self._psize))\n+\n+ def i_stosb(self, op):\n+ return self._stos(op, width=1)\n+\n+ def i_stosd(self, op):\n+ return self._stos(op, width=4)\n+\n+ def _cmps(self, op, width=-1):\n+ si = Var(self.__srcp__, self._psize)\n+ di = Var(self.__destp__, self._psize)\n+ v1 = Mem(si, Const(width, self._psize))\n+ v2 = Mem(di, Const(width, self._psize))\n+ self.effSetVariable('eflags_cf', gt(v2, v1)) #\n+ self.effSetVariable('eflags_gt', gt(v1, v2)) # v1 - v2 > 0 :: v1 > v2\n+ self.effSetVariable('eflags_lt', lt(v1, v2)) # v1 - v2 < 0 :: v1 < v2\n+ self.effSetVariable('eflags_sf', lt(v1, v2)) # v1 - v2 < 0 :: v1 < v2\n+ self.effSetVariable('eflags_eq', eq(v1, v2)) # v1 - v2 == 0 :: v1 == v2\n+\n+ def i_cmpsb(self, op):\n+ return self._cmps(op, width=1)\n+\n+ def i_cmpsd(self, op):\n+ return self._cmps(op, width=4)\n+\nclass i386SymbolikTranslator(IntelSymbolikTranslator):\n__arch__ = e_i386.i386Module\n__ip__ = 'eip' # we could use regctx.getRegisterName if we want.\n@@ -809,7 +835,6 @@ class i386SymbolikTranslator(IntelSymbolikTranslator):\n__srcp__ = 'esi'\n__destp__ = 'edi'\n-\ndef i_pushad(self, op):\nesp = self.getRegObj(e_i386.REG_ESP)\nself.effWriteMemory(esp - Const(4, self._psize), Const(4, self._psize), self.getRegObj(e_i386.REG_EAX))\n@@ -854,22 +879,6 @@ class i386SymbolikTranslator(IntelSymbolikTranslator):\nself.setOperObj(op, 0, ((v1 << v2) | (v1 >> ( Const(op.opers[0].tsize*8, self._psize) - v2))))\n# XXX - set cf flag with last bit moved\n- def i_stosd(self, op):\n- #eax = self.getRegObj(e_i386.REG_EAX)\n- #edi = self.getRegObj(e_i386.REG_EDI)\n- # FIXME omg segments in symboliks?\n- #base,size = self.segments[SEG_ES]\n- di = Var(self.__destp__, self._psize)\n- self.effWriteMemory(di, Const(self._psize, self._psize), Var('eax', self._psize))\n- # FIXME flags?\n- #if self.getFlag(e_i386.EFLAGS_DF):\n- #edi -= 4\n- #else:\n- #edi += 4\n- #print 'FIXME DF IN stosd'\n- di += Const(4, self._psize)\n- self.effSetVariable(self.__destp__, di)\n-\nclass i386ArgDefSymEmu(ArgDefSymEmu):\n__xlator__ = i386SymbolikTranslator\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/common.py",
"new_path": "vivisect/symboliks/common.py",
"diff": "-import sys\nimport hashlib\nimport operator\nimport functools\nimport itertools\n-import traceback\nimport vstruct\nimport envi.bits as e_bits\n@@ -14,7 +12,7 @@ from vivisect.symboliks.constraints import *\ndef symcache(f):\ndef docache(*args, **kwargs):\nret = args[0].cache.get(f.__name__)\n- if ret != None:\n+ if ret is not None:\nreturn ret\nret = f(*args, **kwargs)\n@@ -30,7 +28,7 @@ def varsolve(name,width,emu=None):\n\"solves\" ( aka, generates a repeatable entropic\nvalue ) for a varible by name.\n'''\n- if emu != None:\n+ if emu is not None:\nname += emu.getRandomSeed()\nmd5sum = hashlib.md5(name).hexdigest()\n@@ -69,7 +67,6 @@ def cb_astNodeCount(path,obj,ctx):\nif len(path) > ctx['depth']:\nctx['depth'] = len(path)\n-\nclass SymbolikBase:\nidgen = itertools.count()\n@@ -151,7 +148,7 @@ class SymbolikBase:\ndef __eq__(self, other):\n- if other == None:\n+ if other is None:\nreturn False\nif type(other) in (int, long):\n@@ -241,12 +238,7 @@ class SymbolikBase:\n'''\nif idx > len(self.kids)-1:\nself.kids.append(kid)\n- try:\nself.kids[idx].parents.append(self)\n- except:\n- import pdb\n- pdb.set_trace()\n- print(\"WAT\")\nelse:\n# kid already exists\noldkid = self.kids[idx]\n@@ -280,7 +272,6 @@ class SymbolikBase:\nself.kids[idx] = kid\nself.kids[idx].parents.append(self)\n-\n@symcache\ndef isDiscrete(self, emu=None):\n'''\n@@ -544,7 +535,7 @@ class Var(SymbolikBase):\nreturn\nsym = vw.getSymByName(strval)\n- if sym != None:\n+ if sym is not None:\nvalue = long(sym)\ncanvas.addVaText(strval, va=value)\nreturn\n@@ -561,9 +552,9 @@ class Var(SymbolikBase):\nreturn self.name\ndef _solve(self, emu=None, vals=None):\n- if vals != None:\n+ if vals is not None:\nret = vals.get(self.name)\n- if ret != None:\n+ if ret is not None:\nreturn ret\nreturn varsolve(self.name, self.width, emu=emu)\n@@ -770,7 +761,7 @@ class Operator(SymbolikBase):\n# FIXME - dependancy loop. does this effect perf?\nfrom vivisect.symboliks.reducers import reduceoper\nret = reduceoper(self,emu=emu)\n- if ret != None:\n+ if ret is not None:\nreturn ret\nreturn self._op_reduce(v1, v1val, v2, v2val, emu)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/constraints.py",
"new_path": "vivisect/symboliks/constraints.py",
"diff": "-\nfrom vivisect.symboliks.common import *\nclass Constraint:\n@@ -70,7 +69,7 @@ class Constraint:\nreturn False\ndef reverse(self):\n- if self.revclass == None:\n+ if self.revclass is None:\nraise Exception('Constraints Must Define revclass!')\nreturn self.revclass(self._v1, self._v2)\n@@ -149,6 +148,7 @@ class ge(Constraint):\nclass UNK(Constraint):\noperstr = 'UNK'\nsymtype = SYMT_CON_UNK\n+\nclass NOTUNK(Constraint):\noperstr = '!UNK'\nsymtype = SYMT_CON_NOTUNK\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Even more flake8 and more instructions plumbed through symboliks
|
718,765 |
26.03.2019 16:03:41
| 14,400 |
5ab71f0753e0e2073cc2328c1cc458c33d5468eb
|
Translate eflags_df to algebra
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -158,22 +158,22 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nelif isinstance(oper, e_i386.i386SibOper):\nbase = None\n- if oper.imm != None:\n+ if oper.imm is not None:\nbase = Const(oper.imm, self._psize)\n- if oper.reg != None:\n+ if oper.reg is not None:\nrobj = self.getRegObj(oper.reg)\n- if base == None:\n+ if base is None:\nbase = robj\nelse:\nbase = o_add(base, robj, self._psize)\n# Base is set by here for sure!\n- if oper.index != None:\n+ if oper.index is not None:\nrobj = self.getRegObj(oper.index)\nbase = o_add(base, o_mul(robj, Const(oper.scale, self._psize), self._psize), self._psize)\n- if oper.disp != None:\n+ if oper.disp is not None:\nif oper.disp > 0:\nbase = o_add(base, Const(oper.disp, self._psize), self._psize)\nelse:\n@@ -513,21 +513,18 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.setOperObj(op, 0, o)\ni_movnti = i_mov\n-\n- def i_movq(self, op):\n- o = self.getOperObj(op, 1)\n- self.setOperObj(op, 0, o)\n+ i_movq = i_mov\ndef _movs(self, op, width=-1):\nsi = Var(self.__srcp__, self._psize)\ndi = Var(self.__destp__, self._psize)\nmem = Mem(si, Const(width, self._psize))\nself.effWriteMemory(di, Const(width, self._psize), mem)\n- # XXX: So...in reality these could be + or - depending on\n- # what is in the DF flag in the EFLAGS register. But that's a\n- # conditional and we're in symboliks town, so...whiff past that for now\n- self.effSetVariable(self.__srcp__, si + Const(width, self._psize))\n- self.effSetVariable(self.__destp__, di + Const(width, self._psize))\n+ # This is a translation of if df == 0: add, else subtract that\n+ # the movs{b,w,d,q} are supposed to deal with\n+ mod = Const(width, self._psize) * (Const(1, self._psize) - Const(2, self._psize) * Var('eflags_df', self._psize))\n+ self.effSetVariable(self.__srcp__, si + mod)\n+ self.effSetVariable(self.__destp__, di + mod)\n# TODO: When we move to python 3.4 or greater, we can change these to just\n# functools.partialmethod. Cleaner that way\n@@ -704,7 +701,6 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.effSetVariable('eflags_gt', u)\nself.effSetVariable('eflags_lt', lt(obj, Const(0, self._psize))) # ( SF != OF ) ( OF is cleared )\n-\nself.effSetVariable('eflags_sf', lt(obj, Const(0, self._psize))) # v1 & v2 < 0\nself.effSetVariable('eflags_eq', eq(obj, Const(0, self._psize))) # v1 & v2 == 0\n@@ -801,8 +797,9 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\n# FIXME omg segments in symboliks?\n# base, size = self.segments[SEG_ES]\ndi = Var(self.__destp__, self._psize)\n+ mod = Const(width, self._psize) * (Const(1, self._psize) - Const(2, self._psize) * Var('eflags_df', self._psize))\nself.effWriteMemory(di, Const(self._psize, self._psize), Var('eax', self._psize))\n- self.effSetVariable(self.__destp__, di + Const(width, self._psize))\n+ self.effSetVariable(self.__destp__, di + mod)\ndef i_stosb(self, op):\nreturn self._stos(op, width=1)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Translate eflags_df to algebra
|
718,765 |
26.03.2019 17:03:56
| 14,400 |
c48f52a327d48a9dcb1575c603742fa59057ab77
|
add more mov types and cwde
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -512,8 +512,15 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\no = self.getOperObj(op, 1)\nself.setOperObj(op, 0, o)\n+ # All of these mov's are technically different in i386/amd64, but really only differ by widths and sizes, and not by\n+ # actual mathematical operation\ni_movnti = i_mov\ni_movq = i_mov\n+ i_movaps = i_mov\n+ i_movapd = i_mov\n+ i_movups = i_mov\n+ i_movdqu = i_mov\n+ i_movdqa = i_mov\ndef _movs(self, op, width=-1):\nsi = Var(self.__srcp__, self._psize)\n@@ -642,6 +649,10 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\n# FIXME\nself.setOperObj(op, 0, Const(1, self._psize)) #cnot(Var('eflags_eq', self._psize)))\n+ def i_cwde(self, op):\n+ v1 = o_sextend(self.getRegObj(e_i386.REG_AX), Const(self._psize, self._psize))\n+ self.effSetVariable('eax', v1)\n+\ndef i_setz(self, op):\n# FIXME\nself.setOperObj(op, 0, Const(0, self._psize)) #Var('eflags_eq', self._psize))\n@@ -781,18 +792,6 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nval |= (oper >> bit)\nself.setOperObj(op, 0, val)\n- def i_movups(self, op):\n- # lots of writing in the spec on different things about opersizes...\n- # but all seems to be a big mov.\n- data = self.getOperObj(op, 1)\n- self.setOperObj(op, 0, data)\n-\n- def i_movaps(self, op):\n- # lots of writing in the spec on different things about opersizes...\n- # but all seems to be a big mov.\n- data = self.getOperObj(op, 1)\n- self.setOperObj(op, 0, data)\n-\ndef _stos(self, op, width=-1):\n# FIXME omg segments in symboliks?\n# base, size = self.segments[SEG_ES]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
add more mov types and cwde
|
718,765 |
01.04.2019 15:13:13
| 14,400 |
19cd2afd5f14b73a1abc816ac07286ef23b9d258
|
Even more flake8. Chagne Constraints into inheriting from Operator, which makes things a little cleaner and opens up more avenues for using eflags in algebra.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/symboliks.py",
"new_path": "vivisect/qt/symboliks.py",
"diff": "@@ -11,7 +11,6 @@ import vivisect.symboliks.common as viv_sym_common\nimport vivisect.symboliks.effects as viv_sym_effects\nimport vivisect.symboliks.analysis as viv_sym_analysis\nimport vivisect.symboliks.expression as viv_sym_expression\n-import vivisect.symboliks.constraints as viv_sym_constraints\ntry:\nfrom PyQt5 import QtCore\n@@ -140,7 +139,7 @@ class VivSymbolikFuncPane(e_q_memory.EnviNavMixin, vq_save.SaveableWidget, QWidg\nfor e in exprparts[1:]:\ns = self.symexpr.parseExpression(e)\n- if isinstance(s, viv_sym_constraints.Constraint):\n+ if isinstance(s, viv_sym_common.Constraint):\nprecons.append(s)\ncontinue\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -9,7 +9,6 @@ import vivisect.symboliks.translator as vsym_trans\nfrom vivisect.const import *\nfrom vivisect.symboliks.common import *\n-from vivisect.symboliks.constraints import *\ndef getSegmentSymbol(op):\nif op.prefixes & e_i386.PREFIX_CS:\n@@ -236,8 +235,6 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nv2 = self.getOperObj(op, 1)\n# self.effSetVariable('eflags_zf', eq(add, Const(0)))\n- # TODO: This causes an exception sometimes with no attribute parents\n- #self.setOperObj(op, 0, v1 + v2)\nself.setOperObj(op, 0, v1 + v2 + Var('eflags_cf', 1))\ndef i_add(self, op):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/common.py",
"new_path": "vivisect/symboliks/common.py",
"diff": "@@ -7,7 +7,6 @@ import vstruct\nimport envi.bits as e_bits\nfrom vivisect.const import *\n-from vivisect.symboliks.constraints import *\ndef symcache(f):\ndef docache(*args, **kwargs):\n@@ -385,7 +384,6 @@ class cnot(SymbolikBase):\ndef _reduce(self, emu=None):\n'''\n# FIXME dependancy loop...\n- from vivisect.symboliks.constraints import Constraint\nif self._reduced:\nreturn self\n@@ -898,3 +896,107 @@ class o_sextend(SymbolikBase):\ndef update(self, emu):\nkids = [k.update(emu) for k in self.kids]\nreturn self.__class__(*kids)\n+\n+class Constraint(Operator):\n+ '''\n+ A class to represent algebraic constraints that are tracked by a given\n+ polynomial.\n+ '''\n+ revclass = None\n+ operstr = None\n+\n+ def __init__(self, v1, v2, width=None):\n+ if width is None:\n+ width = v1.getWidth()\n+ Operator.__init__(self, v1, v2, width)\n+\n+ def getWidth(self):\n+ return self.kids[0].getWidth()\n+\n+ def __repr__(self):\n+ return '%s(%s,%s)' % (self.__class__.__name__, repr(self.kids[0]), repr(self.kids[1]))\n+\n+ def __eq__(self, con):\n+ '''\n+ Is this constraint the same as some other?\n+ '''\n+ if not isinstance(con, Constraint):\n+ return False\n+\n+ c1v1 = self.kids[0].solve()\n+ c1v2 = self.kids[1].solve()\n+ c2v1 = con.kids[0].solve()\n+ c2v2 = con.kids[1].solve()\n+\n+ if c1v1 == c2v1 and c1v2 == c2v2 and self.__class__ == con.__class__:\n+ return True\n+\n+ if c1v1 == c2v2 and c1v2 == c2v1 and self.__class__ == con.revclass:\n+ return True\n+\n+ return False\n+\n+ def reverse(self):\n+ if self.revclass is None:\n+ raise Exception('Constraints Must Define revclass!')\n+ return self.revclass(self.kids[0], self.kids[1])\n+\n+ def _op_reduce(self, v1, v1val, v2, v2val, emu):\n+ return self.__class__(v1, v2)\n+\n+\n+def opose(c1, c2):\n+ c1.revclass = c2\n+ c2.revclass = c1\n+\n+\n+class eq(Constraint):\n+ oper = operator.eq\n+ operstr = '=='\n+ symtype = SYMT_CON_EQ\n+\n+\n+class ne(Constraint):\n+ oper = operator.ne\n+ operstr = '!='\n+ symtype = SYMT_CON_NE\n+\n+\n+class le(Constraint):\n+ oper = operator.le\n+ operstr = '<='\n+ symtype = SYMT_CON_LE\n+\n+\n+class gt(Constraint):\n+ oper = operator.gt\n+ operstr = '>'\n+ symtype = SYMT_CON_GT\n+\n+\n+class lt(Constraint):\n+ oper = operator.lt\n+ operstr = '<'\n+ symtype = SYMT_CON_LT\n+\n+\n+class ge(Constraint):\n+ oper = operator.ge\n+ operstr = '>='\n+ symtype = SYMT_CON_GE\n+\n+\n+class UNK(Constraint):\n+ operstr = 'UNK'\n+ symtype = SYMT_CON_UNK\n+\n+\n+class NOTUNK(Constraint):\n+ operstr = '!UNK'\n+ symtype = SYMT_CON_NOTUNK\n+\n+# Create our oposing constraints\n+opose(ne, eq)\n+opose(le, gt)\n+opose(lt, ge)\n+opose(UNK, NOTUNK)\n"
},
{
"change_type": "DELETE",
"old_path": "vivisect/symboliks/constraints.py",
"new_path": null,
"diff": "-from vivisect.symboliks.common import *\n-\n-class Constraint:\n- '''\n- A class to represent algebraic constraints that are tracked by a given\n- polynomial.\n- '''\n- revclass = None\n- operstr = None\n-\n- def __init__(self, v1, v2):\n- self._strval = None\n- self._v1 = v1\n- self._v2 = v2\n-\n- # FIXME consider making constraints into operators...\n- # Their APIs and internals are basically the same!\n-\n- def clearCache(self):\n- self._v1.clearCache()\n- self._v2.clearCache()\n-\n- def walkTree(self, cb, ctx=None, once=True):\n- self._v1 = self._v1.walkTree(cb, ctx=ctx, once=once)\n- self._v2 = self._v2.walkTree(cb, ctx=ctx, once=once)\n-\n- def getWidth(self):\n- return self._v1.getWidth()\n-\n- def setSymSolverContext(self, slvctx):\n- self._v1.setSymSolverContext(slvctx)\n- self._v2.setSymSolverContext(slvctx)\n-\n- def __repr__(self):\n- return '%s(%s,%s)' % (self.__class__.__name__, repr(self._v1), repr(self._v2))\n-\n- def __str__(self):\n- if self._strval:\n- return self._strval\n-\n- self._strval = '%s %s %s' % (str(self._v1), self.operstr, str(self._v2))\n- return self._strval\n-\n- def render(self, canvas, vw):\n- self._v1.render(canvas, vw)\n- canvas.addText(' ')\n- canvas.addNameText(self.operstr)\n- canvas.addText(' ')\n- self._v2.render(canvas, vw)\n-\n- def __eq__(self, con):\n- '''\n- Is this constraint the same as some other?\n- '''\n- if not isinstance(con, Constraint):\n- return False\n-\n- c1v1 = self._v1.solve()\n- c1v2 = self._v2.solve()\n- c2v1 = con._v1.solve()\n- c2v2 = con._v2.solve()\n-\n- if c1v1 == c2v1 and c1v2 == c2v2 and self.__class__ == con.__class__:\n- return True\n-\n- if c1v1 == c2v2 and c1v2 == c2v1 and self.__class__ == con.revclass:\n- return True\n-\n- return False\n-\n- def reverse(self):\n- if self.revclass is None:\n- raise Exception('Constraints Must Define revclass!')\n- return self.revclass(self._v1, self._v2)\n-\n- def reduce(self, emu=None):\n- v1 = self._v1.reduce(emu=emu)\n- v2 = self._v2.reduce(emu=emu)\n- # FIXME transfer discrete values to one side...\n- return self.__class__(v1, v2)\n-\n- def update(self, emu):\n- v1 = self._v1.update(emu)\n- v2 = self._v2.update(emu)\n- return self.__class__(v1, v2)\n-\n- def clone(self):\n- v1 = self._v1.clone()\n- v2 = self._v2.clone()\n- return self.__class__(v1, v2)\n-\n- def prove(self, emu=None, vals=None):\n- v1 = self._v1.solve(emu=emu, vals=vals)\n- v2 = self._v2.solve(emu=emu, vals=vals)\n- return self.testTruth(v1, v2)\n-\n- def solve(self, emu=None, vals=None):\n- # A \"solution\" for a condition is it's boolean state as int...\n- return int(self.prove(emu=emu, vals=vals))\n-\n- def testTruth(self, v1, v2):\n- # raise Exception('Constraint %s must implement testTruth!' % self.__class__.__name__)\n- return True\n-\n- def isDiscrete(self, emu=None):\n- return self._v1.isDiscrete(emu=emu) and self._v2.isDiscrete(emu=emu)\n-\n-\n-def opose(c1, c2):\n- c1.revclass = c2\n- c2.revclass = c1\n-\n-\n-class eq(Constraint):\n- operstr = '=='\n- symtype = SYMT_CON_EQ\n- def testTruth(self, v1, v2):\n- return v1 == v2\n-\n-\n-class ne(Constraint):\n- operstr = '!='\n- symtype = SYMT_CON_NE\n- def testTruth(self, v1, v2):\n- return v1 != v2\n-\n-\n-class le(Constraint):\n- operstr = '<='\n- symtype = SYMT_CON_LE\n- def testTruth(self, v1, v2):\n- return v1 <= v2\n-\n-\n-class gt(Constraint):\n- operstr = '>'\n- symtype = SYMT_CON_GT\n- def testTruth(self, v1, v2):\n- return v1 > v2\n-\n-\n-class lt(Constraint):\n- operstr = '<'\n- symtype = SYMT_CON_LT\n- def testTruth(self, v1, v2):\n- return v1 < v2\n-\n-\n-class ge(Constraint):\n- operstr = '>='\n- symtype = SYMT_CON_GE\n- def testTruth(self, v1, v2):\n- return v1 >= v2\n-\n-\n-class UNK(Constraint):\n- operstr = 'UNK'\n- symtype = SYMT_CON_UNK\n-\n-\n-class NOTUNK(Constraint):\n- operstr = '!UNK'\n- symtype = SYMT_CON_NOTUNK\n-\n-# Create our oposing constraints\n-opose(ne, eq)\n-opose(le, gt)\n-opose(lt, ge)\n-opose(UNK, NOTUNK)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/effects.py",
"new_path": "vivisect/symboliks/effects.py",
"diff": "from vivisect.symboliks.common import *\n-from vivisect.symboliks.constraints import *\nfrom vivisect.const import *\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/expression.py",
"new_path": "vivisect/symboliks/expression.py",
"diff": "@@ -6,7 +6,6 @@ constraints from humon input.\nimport ast\nimport vivisect.symboliks.effects as v_s_eff\n-import vivisect.symboliks.constraints as v_s_cons\nfrom vivisect.symboliks.common import *\n@@ -24,12 +23,12 @@ op2op = {\n}\ncmp2cons = {\n- ast.LtE: v_s_cons.le,\n- ast.GtE: v_s_cons.ge,\n- ast.Lt: v_s_cons.lt,\n- ast.Gt: v_s_cons.gt,\n- ast.Eq: v_s_cons.eq,\n- ast.NotEq: v_s_cons.ne,\n+ ast.LtE: le,\n+ ast.GtE: ge,\n+ ast.Lt: lt,\n+ ast.Gt: gt,\n+ ast.Eq: eq,\n+ ast.NotEq: ne,\n}\ndefexp = {}\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/reducers.py",
"new_path": "vivisect/symboliks/reducers.py",
"diff": "@@ -229,6 +229,7 @@ reducers = {\n('(x1 - c1) + c2', lambda m, emu=None: addsub(m['x1'], m['c2'] - m['c1'])),\n('(c1 - x1) + x2', lambda m, emu=None: addsub(m['x2'] - m['x1'], m['c1'])),\n('(c1 - x1) + c2', lambda m, emu=None: addsub(symneg(m['x1']), m['c1'] + m['c2'])),\n+ ('(x1 - x2) + x2', lambda m, emu=None: m['x1']),\n('(x1 + 0)', lambda m, emu=None: m['x1']),\n('(x1 + x1)', lambda m, emu=None: m['x1'] * Const(2, m['x1'].getWidth())),\n('(x1 + x2) + x1', lambda m, emu=None: m['x2'] + (m['x1'] * Const(2,m['x1'].getWidth()))),\n@@ -248,6 +249,7 @@ reducers = {\n('(x1 + c1) - c2', lambda m,emu=None: addsub(m['x1'], m['c1'] - m['c2'])), # x1 + (c1 - c2) #\n('(x1 - c1) - c2', lambda m,emu=None: addsub(m['x1'], -(m['c1'] + m['c2']))), # x1 - (c1 + c2) #\n('(c1 - x1) - c2', lambda m,emu=None: sub_c_x(m['c1'] - m['c2'], m['x1'])), # (c1 - c2) - x1 #\n+ ('(x1 + x2) - x2', lambda m, emu=None: m['x1']),\n('c1 - (x1 - c2)', lambda m,emu=None: sub_c_x(m['c1'] + m['c2'], m['x1'])), # (c1 + c2) - x1 #\n('c1 - (c2 - x1)', lambda m,emu=None: addsub(m['x1'], m['c1'] - m['c2'])),# (c1 + x1) - c2 # (x1 + c1) - c2 # x1 + (c1 - c2) #\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_constraints.py",
"new_path": "vivisect/symboliks/tests/test_constraints.py",
"diff": "@@ -32,18 +32,24 @@ class TestConstraints(unittest.TestCase):\nself.assertTruth('foo == foo')\ndef test_reduce(self):\n- s1 = '(0 & ((foo * 4) >> 2)) == 0'\n- v1 = symexp('(0 & ((foo * 4) >> 2)) == 0')\n+ s1 = '((0 & ((foo * 4) >> 2)) == 0)'\n+ v1 = symexp('((0 & ((foo * 4) >> 2)) == 0)')\nself.assertTrue(s1 == str(v1))\n- self.assertReduce(s1, '0 == 0')\n+ self.assertReduce(s1, '1')\nself.assertTrue(v1.getWidth() == 4) # default width\n- s2 = '(((foo * bar) * baz) + (131 | 40)) == (((foo * bar) * baz) + 171)'\n+ s2 = '((((foo * bar) * baz) + (131 | 40)) == (((foo * bar) * baz) + 171))'\nv2 = symexp(s2)\nself.assertTrue(s2 == str(v2))\nself.assertReduce(s2, '(((foo * bar) * baz) + 171) == (((foo * bar) * baz) + 171)')\nself.assertTrue(v2.getWidth() == 4) # default width\n+ s2 = '(((((foo - bar) + bar) + (131 | 40)) - 171) == foo)'\n+ v2 = symexp(s2)\n+ self.assertTrue(s2 == str(v2))\n+ self.assertReduce(s2, 'foo == foo')\n+ self.assertTrue(v2.getWidth() == 4) # default width\n+\ndef test_rev(self):\nv1 = symexp('4 < 5')\nv2 = symexp('4 >= 5')\n@@ -90,7 +96,8 @@ class TestConstraints(unittest.TestCase):\n'(((foo ** 2) << 1) + (bar * 3))',\n'4',\n'((((foo ** 2) << 1) + (bar * 3)) - 4)',\n- '0']\n+ '0',\n+ '(((((foo ** 2) << 1) + (bar * 3)) - 4) > 0)']\nif len(order) != len(correct):\nself.fail('test_walktree, visit produced unexpected results')\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Even more flake8. Chagne Constraints into inheriting from Operator, which makes things a little cleaner and opens up more avenues for using eflags in algebra.
|
718,765 |
01.04.2019 16:19:25
| 14,400 |
569e188bed2480bf440461df48e704c671292685
|
Speeeling and aesthetics
|
[
{
"change_type": "MODIFY",
"old_path": "envi/registers.py",
"new_path": "envi/registers.py",
"diff": "@@ -346,8 +346,8 @@ class RegisterContext:\n(used when setting a meta register)\n'''\nridx = index & 0xffff\n- offset = (index >> 24) & 0xff\nwidth = (index >> 16) & 0xff\n+ offset = (index >> 24) & 0xff\n# FIXME is it faster to generate or look thses up?\nmask = (2 ** width) - 1\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -760,7 +760,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\ndef i_xchg(self, op):\n# NOTE: requires using temp var because each asignment occurs\n# seperately. (even though the API makes it look like you've\n- # got your pwn copy... ;) )\n+ # got your own copy... ;) )\nx = self.getOperObj(op, 0)\ny = self.getOperObj(op, 1)\nself.effSetVariable('i386_xchg_tmp', x)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/effects.py",
"new_path": "vivisect/symboliks/effects.py",
"diff": "@@ -230,12 +230,12 @@ class CallFunction(SymbolikEffect):\ndef __str__(self):\nargstr = '?'\n- if self.argsyms != None:\n+ if self.argsyms is not None:\nargstr = ','.join(str(x) for x in self.argsyms)\nreturn '%s(%s)' % (self.funcsym, argstr)\ndef __eq__(self, other):\n- if other == None:\n+ if other is None:\nreturn False\nif self.__class__ != other.__class__:\nreturn False\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Speeeling and aesthetics
|
718,765 |
02.04.2019 13:39:18
| 14,400 |
4b03a506832e44627f61ab0425a58481f3fd45ff
|
add better(?) divide instr for x86/x86_64 and moar tests for constraints
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -298,6 +298,12 @@ class DivideByZero(EmuException):\na 0 divisor...\n\"\"\"\n+class DivideError(EmuException):\n+ \"\"\"\n+ Raised by an Emulator whena a divide falls out\n+ of the specified range.\n+ \"\"\"\n+\nclass BreakpointHit(EmuException):\n\"\"\"\nRaised by an emulator when you execute a breakpoint instruction\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/amd64.py",
"new_path": "vivisect/symboliks/archs/amd64.py",
"diff": "import hashlib\n+import envi\nimport envi.archs.amd64 as e_amd64\nfrom vivisect.symboliks.common import *\n@@ -107,28 +108,35 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nv2 = o_sextend(self.getOperObj(op, 1), Const(ssize, self._psize))\nself.setOperObj(op, 0, v2)\n- def i_div(self, op):\n+ def _div(self, op, isInvalid=None):\noper = op.opers[0]\ndenom = self.getOperObj(op, 1)\nif denom == 0:\n# TODO: make effect\n- raise Exception('#DE, divide by zero')\n+ raise envi.DivideByZero('AMD64 Divide by zero')\n+\n+ if isInvalid is None:\n+ limit = (2 ** (oper.tsize * 8)) - 1\n+ isInvalid = lambda val: val > limit\nif oper.tsize == 8:\nrax = Var('rax', self._psize)\nrdx = Var('rdx', self._psize)\nnum = (rdx << Const(64, self._psize)) + rax\ntemp = num / denom\n- if temp > (2**64)-1:\n+ if isInvalid(temp):\n# TODO: make effect\n- raise Exception('#DE, divide error')\n+ raise envi.DivideError('AMD64 i_div #DE')\nself.effSetVariable('rax', temp)\nself.effSetVariable('rdx', num % denom)\nreturn\n- return vsym_i386.IntelSymbolikTranslator.i_div(self, op)\n+ return vsym_i386.IntelSymbolikTranslator._div(self, op, isInvalid=isInvalid)\n+\n+ def i_div(self, op):\n+ return self._div(op)\ndef i_jecxz(self, op):\nreturn vsym_i386.IntelSymbolikTranslator.i_jecxz(self, op)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -332,29 +332,40 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.setOperObj(op, 0, sub)\n- def i_div(self, op):\n+ def _div(self, op, isInvalid=None):\noper = op.opers[0]\ndivbase = self.getOperObj(op, 1)\n+ if isInvalid is None:\n+ limit = (2 ** (oper.tsize * 8)) - 1\n+ isInvalid = lambda val: val > limit\nif oper.tsize == 1:\n- # TODO: this is broken\n- ax = self._reg_ctx._xlateToNativeReg(e_i386.REG_AX, Var('eax', self._psize))\n+ ax = self.getRegObj(e_i386.REG_AX)\nquot = ax / divbase\nrem = ax % divbase\n- # TODO: this is broken\n- self.effSetVariable('eax', (quot << 8) + rem)\n+ if isInvalid(quot):\n+ raise envi.DivideError('i386 #DE')\n+ self.effSetVariable('eax', (rem << 8) + quot)\nelif oper.tsize == 2:\n- raise Exception(\"16 bit divide needs help!\")\n+ ax = self.getRegObj(e_i386.REG_AX)\n+ dx = self.getRegObj(e_i386.REG_DX)\n+ tot = (edx << Const(16, self._psize)) + eax\n+ quot = tot / divbase\n+ rem = tot % divbase\n+ if isInvalid(quot):\n+ raise envi.DivideError('i386 #DE')\n+ self.effSetVariable('eax', quot)\n+ self.effSetVariable('edx', rem)\nelif oper.tsize == 4:\neax = Var('eax', self._psize)\nedx = Var('edx', self._psize)\n-\n- #FIXME 16 bit over-ride\ntot = (edx << Const(32, self._psize)) + eax\nquot = tot / divbase\nrem = tot % divbase\n+ if isInvalid(quot):\n+ raise envi.DivideError('i386 #DE')\nself.effSetVariable('eax', quot)\nself.effSetVariable('edx', rem)\n# FIXME maybe we need a \"check exception\" effect?\n@@ -362,6 +373,33 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nelse:\nraise envi.UnsupportedInstruction(self, op)\n+ def i_div(self, op):\n+ return self._div(op)\n+\n+ def i_idiv(self, op):\n+ tsize = op.opers[0].tsize\n+ limit = ((-2 ** (tsize * 8 - 1)), 2 ** (tsize * 8 - 1) - 1)\n+ return self._div(op, isInvalid=lambda val: val < limit[0] or val > limit[1])\n+\n+ def i_divsd(self, op):\n+ ocount = len(op.opers)\n+ if ocount == 2:\n+ dst = self.getOperObj(op, 0)\n+ src = self.getOperObj(op, 1)\n+ if src == 0:\n+ raise Exception('#DE, divide error')\n+ res = dst / src\n+ self.setOperObj(op, 0, res)\n+ elif ocount == 3:\n+ src1 = self.getOperObj(op, 1)\n+ src2 = self.getOperObj(op, 2)\n+ if src2 == 0:\n+ raise Exception('#DE, divide error')\n+ res = src1 / src2\n+ self.setOperObj(op, 0, res)\n+ else:\n+ raise envi.UnsupportedInstruction(self, op)\n+\ndef i_hlt(self, op):\n# Nothing to do symbolically....\npass\n@@ -376,7 +414,6 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.setOperObj(op, 0, res)\nelif ocount == 3:\n- dst = self.getOperObj(op, 0)\nsrc1 = self.getOperObj(op, 1)\nsrc2 = self.getOperObj(op, 2)\ndsize = op.opers[0].tsize\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_constraints.py",
"new_path": "vivisect/symboliks/tests/test_constraints.py",
"diff": "@@ -114,3 +114,10 @@ class TestConstraints(unittest.TestCase):\nv1 = v1.update(emu)\nself.assertTrue(v1.isDiscrete(emu))\nself.assertTrue(v1.solve(emu) == 0)\n+\n+ def test_mixed(self):\n+ v1 = symexp('(foo ** 2) << (1 > 0)')\n+ emu = MockEmulator(MockVw())\n+ emu.setSymVariable('foo', Const(5, emu.__width__))\n+ v1 = v1.update(emu).reduce()\n+ self.assertTrue(v1.value == 50)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
add better(?) divide instr for x86/x86_64 and moar tests for constraints
|
718,765 |
02.04.2019 13:45:37
| 14,400 |
b7cc431b8a48f0939f3549d79405f4b595492b50
|
quick doc on testing
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": "TESTING.md",
"diff": "+## Running the unit tests\n+\n+```\n+mkdir code\n+cd code\n+git clone https://github.com/vivisect/vivisect\n+git clone https://github.com/vivisect/vivtestfiles\n+cd vivisect\n+VIVTESTFILES=../vivtestfiles python2 -m unittest discover\n+```\n+\n+If you want to see the code coverage stats:\n+```\n+cd vivisect\n+VIVTESTFILES=../vivtestfiles coverage -m unittest discover\n+coverage html\n+```\n+And then open vivisect/coverage\\_html\\_report/index.html\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
quick doc on testing
|
718,765 |
02.04.2019 16:11:42
| 14,400 |
a12e9d9bff3a3d5b11c074b7087132538b3b50f6
|
Be more aggressive about reduction for equality
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/common.py",
"new_path": "vivisect/symboliks/common.py",
"diff": "@@ -916,6 +916,11 @@ class Constraint(Operator):\ndef __repr__(self):\nreturn '%s(%s,%s)' % (self.__class__.__name__, repr(self.kids[0]), repr(self.kids[1]))\n+ def _solve(self, emu=None, vals=None):\n+ v1 = self.kids[0].solve(emu=emu, vals=vals)\n+ v2 = self.kids[1].solve(emu=emu, vals=vals)\n+ return int(self.oper(v1, v2))\n+\ndef __eq__(self, con):\n'''\nIs this constraint the same as some other?\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/reducers.py",
"new_path": "vivisect/symboliks/reducers.py",
"diff": "@@ -43,7 +43,7 @@ def ismatch(sym,tmp):\nismatch( symexp('eax + 20'), symexp('x1 + c1')) -> {'x1':Var('eax'), 'c1':20}\n'''\n- todo = [(sym,tmp),]\n+ todo = [(sym, tmp)]\nsymwidth = sym.getWidth()\n@@ -77,6 +77,11 @@ def ismatch(sym,tmp):\ntodo.append((s.kids[1], t.kids[1]))\ncontinue\n+ if t.symtype in (SYMT_CON_EQ, SYMT_CON_NE):\n+ todo.append((s.kids[0], t.kids[0]))\n+ todo.append((s.kids[1], t.kids[1]))\n+ continue\n+\nif t.symtype == SYMT_CONST:\nif t.value != s.value:\nreturn None\n@@ -311,6 +316,14 @@ reducers = {\n('(0 << x1)', lambda m, emu=None: 0),\n('(x1 << c1)', lambda m, emu=None: mulbase(m['x1'], 2**m['c1'])),\n]),\n+\n+ SYMT_CON_EQ: xpandrules([\n+ ('(x1 == x1)', lambda m, emu=None: 1),\n+ ]),\n+\n+ SYMT_CON_NE: xpandrules([\n+ ('(x1 != x1)', lambda m, emu=None: 0),\n+ ]),\n}\ndef reduceoper(sym,emu=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_constraints.py",
"new_path": "vivisect/symboliks/tests/test_constraints.py",
"diff": "@@ -20,6 +20,11 @@ class TestConstraints(unittest.TestCase):\nsym2 = symexp(s2)\nself.assertEqual(str(sym1), str(sym2))\n+ @unittest.skip('This takes *forever* to compute')\n+ def test_perf(self):\n+ v1 = symexp('biz = bar ** foo + baz')\n+ v1.reduce()\n+\ndef test_const(self):\nself.assertTruth('0 < 1')\nself.assertTruth('0xab == 0xab')\n@@ -41,14 +46,18 @@ class TestConstraints(unittest.TestCase):\ns2 = '((((foo * bar) * baz) + (131 | 40)) == (((foo * bar) * baz) + 171))'\nv2 = symexp(s2)\nself.assertTrue(s2 == str(v2))\n- self.assertReduce(s2, '(((foo * bar) * baz) + 171) == (((foo * bar) * baz) + 171)')\n+ self.assertTrue(v2.reduce() == 1)\nself.assertTrue(v2.getWidth() == 4) # default width\n- s2 = '(((((foo - bar) + bar) + (131 | 40)) - 171) == foo)'\n- v2 = symexp(s2)\n- self.assertTrue(s2 == str(v2))\n- self.assertReduce(s2, 'foo == foo')\n- self.assertTrue(v2.getWidth() == 4) # default width\n+ s3 = '(((((foo - bar) + bar) + (131 | 40)) - 171) == foo)'\n+ v3 = symexp(s3)\n+ self.assertTrue(s3 == str(v3))\n+ self.assertTrue(v3.reduce() == 1)\n+ self.assertTrue(v3.getWidth() == 4) # default width\n+\n+ s4 = 'foo - (foo + 3 ** 4) == biz / bar + boo'\n+ v4 = symexp(s4)\n+ self.assertTrue(v4.reduce() != 0)\ndef test_rev(self):\nv1 = symexp('4 < 5')\n@@ -120,4 +129,11 @@ class TestConstraints(unittest.TestCase):\nemu = MockEmulator(MockVw())\nemu.setSymVariable('foo', Const(5, emu.__width__))\nv1 = v1.update(emu).reduce()\n- self.assertTrue(v1.value == 50)\n+ self.assertTrue(v1 == 50)\n+\n+ def test_layered(self):\n+ v1 = symexp('(1595 == 1595) == (47 == 2)')\n+ self.assertTrue(v1.reduce() == 0)\n+\n+ v1 = symexp('(foo == foo) == (bar == bar)')\n+ self.assertTrue(v1.reduce() == 1)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Be more aggressive about reduction for equality
|
718,765 |
03.04.2019 10:51:08
| 14,400 |
deaef8c2e73f5e1d352247a91d8b424c5412bf22
|
add more of the setcc instructions. TODO: figure out a good scheme for setting the PF bit
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -692,17 +692,110 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.effSetVariable('eflags_eq', eq(v1, v2)) # v1 - v2 == 0 :: v1 == v2\nself.setOperObj(op, 0, v1 - v2)\n- def i_setnz(self, op):\n- # FIXME\n- self.setOperObj(op, 0, Const(1, self._psize)) #cnot(Var('eflags_eq', self._psize)))\ndef i_cwde(self, op):\nv1 = o_sextend(self.getRegObj(e_i386.REG_AX), Const(self._psize, self._psize))\nself.effSetVariable('eax', v1)\n- def i_setz(self, op):\n+ def _carry_eq(self, x):\n+ return eq(Var('eflags_cf', self._psize), Const(x, self._psize))\n+\n+ def _zero_eq(self, x):\n+ return eq(Var('eflags_eq', self._psize), Const(x, self._psize))\n+\n+ def _overflow_eq(self, x):\n+ return eq(Var('eflags_eq', self._psize), Const(x, self._psize))\n+\n+ def _signed_eq(self, x):\n+ return eq(Var('eflags_eq', self._psize), Const(x, self._psize))\n+\n+ def _parity_eq(self, x):\n+ # TODO Somebody needs to set this\n+ return eq(Var('eflags_pf', self._psize), Const(x, self._psize))\n+\n+ def i_seta(self, op):\n+ self.setOperObj(op, 0, self._carry_eq(0) & self._zero_eq(0))\n+\n+ def i_setae(self, op):\n+ self.setOperObj(op, 0, self._carry_eq(0))\n+\n+ def i_setb(self, op):\n+ self.setOperObj(op, 0, self._carry_eq(1))\n+\n+ def i_setbe(self, op):\n+ self.setOperObj(op, 0, self._zero_eq(1) | self._carry_eq(1))\n+\n+ i_setc = i_setb\n+\n+ def i_sete(self, op):\n+ self.setOperObj(op, 0, self._zero_eq(1))\n+\n+ def i_setg(self, op):\n+ signed = eq(Var('eflags_sf', self._psize), Var('eflags_of', self._psize))\n+ self.setOperObj(op, 0, self._overflow_eq(0) & signed)\n+\n+ def i_setge(self, op):\n+ signed = eq(Var('eflags_sf', self._psize), Var('eflags_of', self._psize))\n+ self.setOperObj(op, 0, signed)\n+\n+ def i_setl(self, op):\n+ not_signed = ne(Var('eflags_sf', self._psize), Var('eflags_of', self._psize))\n+ self.setOperObj(op, 0, not_signed)\n+\n+ def i_setle(self, op):\n+ equal = eq(Var('eflags_eq', self._psize), Const(1, self._psize))\n+ not_signed = ne(Var('eflags_sf', self._psize), Var('eflags_of', self._psize))\n+ self.setOperObj(op, 0, self._zero_eq(1) | not_signed)\n+\n+ i_setna = i_setbe\n+\n+ def i_setnae(self, op):\n+ self.setOperObj(op, 0, self._carry_eq(1))\n+\n+ def i_setnb(self, op):\n+ self.setOperObj(op, 0, self._carry_eq(0))\n+\n+ i_setnbe = i_seta\n+ i_setnc = i_setnae\n+\n+ def i_setne(self, op):\n+ self.setOperObj(op, 0, self._zero_eq(0))\n+\n+ i_setng = i_setle\n+ i_setnge = i_setl\n+ i_setnl = i_setge\n+ i_setnle = i_setg\n+\n+ def i_setno(self, op):\n+ self.setOperObj(op, 0, self._overflow_eq(0))\n+\n+ def i_setnp(self, op):\n+ # FIXME\n+ self.setOperObj(op, 0, Const(0, self._psize))\n+\n+ def i_setns(self, op):\n+ self.setOperObj(op, 0, self._signed_eq(0))\n+\n+ i_setnz = i_setne\n+\n+ def i_seto(self, op):\n+ self.setOperObj(op, 0, self._overflow_eq(0))\n+\n+ def i_setp(self, op):\n+ # FIXME\n+ self.setOperObj(op, 0, Const(0, self._psize))\n+\n+ def i_setpe(self, op):\n+ # FIXME\n+ self.setOperObj(op, 0, Const(0, self._psize))\n+\n+ def i_setpo(self, op):\n# FIXME\n- self.setOperObj(op, 0, Const(0, self._psize)) #Var('eflags_eq', self._psize))\n+ self.setOperObj(op, 0, Const(0, self._psize))\n+\n+ def i_sets(self, op):\n+ self.setOperObj(op, 0, self._signed_eq(1))\n+ i_setz = i_sete\ndef i_shl(self, op):\nv1 = self.getOperObj(op, 0)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_constraints.py",
"new_path": "vivisect/symboliks/tests/test_constraints.py",
"diff": "@@ -137,3 +137,7 @@ class TestConstraints(unittest.TestCase):\nv1 = symexp('(foo == foo) == (bar == bar)')\nself.assertTrue(v1.reduce() == 1)\n+\n+ v2 = symexp('(foo == foo) & (bar == bar)')\n+ self.assertTrue(v2.reduce() == 1)\n+ self.assertTrue(v1.reduce() == v2.reduce())\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
add more of the setcc instructions. TODO: figure out a good scheme for setting the PF bit
|
718,765 |
03.04.2019 12:03:26
| 14,400 |
f1c73a3e22bd2a552fd75ab981aaaa2e5fc0bc6e
|
add link to what I think is the datasheet for h8 we're basing our disassembler off of (old link is dead)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/h8/__init__.py",
"new_path": "envi/archs/h8/__init__.py",
"diff": "@@ -46,7 +46,8 @@ class H8Module(envi.ArchitectureModule):\nimport envi.archs.h8.emu as h8_emu\nreturn h8_emu.H8Emulator()\n-\n+# https://www.renesas.com/us/en/doc/products/mpumcu/001/rej09b0403_h8s2472_2462hm.pdf?key=69aea339d84b503e86d4d19924e46b8c\n+# see page 1072 onwards for mem -> reg mappings\nmemreg_h8s = { # from rej06b0824_h8sap.pdf (h8s/2400). uncommented entries from IDA H9S/Advanced\n0xffff84: 'SBYCR', # Standby Control Register\n0xffff86: 'MSTPCRH',\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
add link to what I think is the datasheet for h8 we're basing our disassembler off of (old link is dead)
|
718,765 |
03.04.2019 22:01:05
| 14,400 |
4583b6774da89ce4f442be19d720dd0fb8ac69db
|
Fixes as per atlas
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/h8/__init__.py",
"new_path": "envi/archs/h8/__init__.py",
"diff": "@@ -61,7 +61,6 @@ memreg_h8s = { # from rej06b0824_h8sap.pdf (h8s/2400). uncommented entries fro\n0xffffa3: 'TDR_2',\n0xffffa4: 'SSR_2',\n0xffffa5: 'RDR_2',\n- # 0xffffa8: 'WDT_0', # XXX: Reaffirm this\n0xffffa8: 'TCNT_0', # Timer Counter_0(write) - 16bits\n0xffffa9: 'TCNT_0_byte1',\n0xffffaa: 'PAODR', # Port A Output Data Register\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/expression.py",
"new_path": "envi/expression.py",
"diff": "@@ -17,13 +17,13 @@ class ExpressionFail(Exception):\nreturn self.__repr__()\n-def evaluate(pycode, locs):\n+def evaluate(pycode, locvars):\ntry:\n- val = eval(pycode, {}, locs)\n+ val = eval(pycode, {}, locvars)\nexcept Exception:\ntry:\n# check through the keys for anything we might want to replace\n- keys = locs.keys()\n+ keys = locvars.keys()\n# sort the keys in reverse order so that longer matching strings take priority\nkeys.sort(reverse=True)\n@@ -31,10 +31,10 @@ def evaluate(pycode, locs):\n# replace the substrings with the string versions of the lookup value\nfor key in keys:\nif key in pycode:\n- pval = locs[key]\n+ pval = locvars[key]\npycode = pycode.replace(key, str(pval))\n- val = eval(pycode, {}, locs)\n+ val = eval(pycode, {}, locvars)\nexcept Exception as e:\nraise ExpressionFail(pycode, e)\n"
},
{
"change_type": "MODIFY",
"old_path": "requirements.txt",
"new_path": "requirements.txt",
"diff": "pyasn1=0.4.5\npyans1-modules=0.2.4\n-cxxfilter\n+cxxfilt\nmsgpack\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/notifiers.py",
"new_path": "vtrace/notifiers.py",
"diff": "@@ -42,9 +42,10 @@ class Notifier(object):\ndef notify(self, event, trace):\nprint(\"Got event: %d from pid %d\" % (event, trace.getPid()))\n+\nclass VerboseNotifier(Notifier):\ndef notify(self, event, trace):\n- print(\"PID %d - ThreadID (%d) got\" % (trace.getPid(), trace.getMeta(\"ThreadId\")))\n+ print \"PID %d - ThreadID (%d) got\" % (trace.getPid(), trace.getMeta(\"ThreadId\")),\nif event == vtrace.NOTIFY_ALL:\nprint(\"WTF, how did we get a vtrace.NOTIFY_ALL event?!?!\")\nelif event == vtrace.NOTIFY_SIGNAL:\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/linux.py",
"new_path": "vtrace/platforms/linux.py",
"diff": "@@ -254,7 +254,7 @@ class LinuxMixin(v_posix.PtraceMixin, v_posix.PosixMixin):\nA utility to open (if necessary) and seek the memfile\n\"\"\"\nif self.memfd is None:\n- self.memfd = libc.open(\"/proc/%d/mem\" % self.pid, O_RDWR | O_LARGEFILE, 755)\n+ self.memfd = libc.open(\"/proc/%d/mem\" % self.pid, O_RDWR | O_LARGEFILE, 0755)\nx = libc.lseek64(self.memfd, offset, 0)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Fixes as per atlas
|
718,765 |
05.04.2019 10:18:54
| 14,400 |
1e2e528dc9bc6cf913d04ab3175caa2e66118bb6
|
Comment out dead func
|
[
{
"change_type": "MODIFY",
"old_path": "vtrace/envitools.py",
"new_path": "vtrace/envitools.py",
"diff": "@@ -51,7 +51,7 @@ def lockStepEmulator(emu, trace):\ncmpRegs(emu, trace)\nexcept RegisterException, msg:\nprint \"Lockstep Error: %s: %s\" % (repr(op),msg)\n- setRegs(emu, trace)\n+ # setRegs(emu, trace)\nsys.stdin.readline()\nexcept Exception, msg:\ntraceback.print_exc()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Comment out dead func
|
718,770 |
10.04.2019 14:52:29
| 14,400 |
bb818f8617b74f1245de374f90f4096eb3e33fe6
|
start for adv_simd_ldst
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -2866,6 +2866,130 @@ adv_simd_2regs_misc = (\n('vcvt', INS_VCVT, ADV_SIMD_F32S32+1, 0,0, 0),\n)\n+\n+def adv_simd_ldst_32(val, va):\n+ u = (val>>24) & 1\n+ return _do_adv_simd_ldst_32(val, va, u)\n+\n+def _do_adv_simd_ldst_32(val, va, u):\n+ a = (val >> 23) & 1\n+ l = (val >> 21) & 1\n+\n+ optype = (val >> 8) & 0xf\n+\n+ d = (val >> 22) & 1\n+ rn = (val >> 16) & 0xf\n+ vd = (val >> 12) & 0xf\n+ rm = val & 0xf\n+ dd = vd | (d << 4)\n+\n+ sflag, size = ((IFS_8,1), (IFS_16,2), (IFS_32,4), (IFS_64,8))[(val >> 6) & 3]\n+ align = (1,8,16,32)[(val >> 4) & 3]\n+\n+ simdflags = sflag\n+ writeback = (rm != 15)\n+ pubwl = PUxWL_DFLT | (writeback<<1)\n+ iflags = (0, IF_W)[writeback]\n+ opers = ()\n+\n+ if l == 0:\n+ # store\n+ if a == 0:\n+ count = (1,2,4,2,3,3,3,1,1,1,2) [ optype ]\n+\n+ # multiple elements\n+ if optype in (0b0010, 0b0110, 0b0111, 0b1010):\n+ # vst1\n+ mnem = 'vst1'\n+ opers = (\n+ ArmExtRegListOper(dd, count, 1), # size in this context means use \"D#\" registers\n+ ArmImmOffsetOper(rn, 0, va, pubwl=pubwl, psize=size, tsize=size),\n+ )\n+\n+ elif optype in (0b0011, 0b1000, 0b1001):\n+ # vst2\n+ mnem = 'vst2'\n+ elif optype in (0b0100, 0b0101):\n+ # vst3\n+ mnem = 'vst3'\n+ inc = 1 + (optype&1)\n+ opers = (\n+ ArmExtRegListOper(dd, count, 1, inc),\n+ ArmImmOffsetOper(rn, 0, va, pubwl=pubwl, psize=size, tsize=size),\n+ )\n+\n+ elif optype in (0b0000, 0b0001):\n+ # vst4\n+ mnem = 'vst4'\n+\n+ else:\n+ # single elements\n+ index_align = (val >> 4) & 0xf\n+ size = (val >> 10) & 3\n+\n+ if optype in (0b0000, 0b0100, 0b1000):\n+ # vst1\n+ mnem = 'vst1'\n+ opers = (\n+ ArmExtRegListOper(dd, count, 1),\n+ ArmImmOffsetOper(rn, 0, va, pubwl=pubwl, psize=size, tsize=size),\n+ )\n+ elif optype in (0b0001, 0b0101, 0b1001):\n+ # vst2\n+ mnem = 'vst2'\n+ elif optype in (0b0010, 0b0110, 0b1010):\n+ # vst3\n+ mnem = 'vst3'\n+ elif optype in (0b0011, 0b0111, 0b1011):\n+ # vst4\n+ mnem = 'vst4'\n+\n+ else:\n+ # load\n+ if a:\n+ # multiple elements\n+ if optype in (0b0010, 0b0110, 0b0111, 0b1010):\n+ # vld1 multiple single element\n+ mnem = 'vld1'\n+ elif optype in (0b0011, 0b1000, 0b1001):\n+ # vld2 multiple 2-element structures\n+ mnem = 'vld2'\n+ elif optype in (0b0100, 0b0101):\n+ # vld3 multiple 3-element structures\n+ mnem = 'vld3'\n+ elif optype in (0b0000, 0b0001):\n+ # vld4 multiple 4-element structures\n+ mnem = 'vld4'\n+\n+ else:\n+ # single elements\n+ if optype in (0b0000, 0b0100, 0b1000):\n+ # vld1 single element to one lane\n+ mnem = 'vld1'\n+ elif optype == 0b1100:\n+ # vld1 single element to all lanes\n+ mnem = 'vld1'\n+ elif optype in (0b0001, 0b0101, 0b1001):\n+ # vld2 single 2-element structure to one lane\n+ mnem = 'vld2'\n+ elif optype == 0b1101:\n+ # vld2 single 2-element structure to all lanes\n+ mnem = 'vld2'\n+ elif optype in (0b0010, 0b0110, 0b1010):\n+ # vld3 single 3-element structure to one lane\n+ mnem = 'vld3'\n+ elif optype == 0b1110:\n+ # vld3 single 3-element structure to all lanes\n+ mnem = 'vld3'\n+ elif optype in (0b0011, 0b0111, 0b1011):\n+ # vld4 single 4-element structure to one lane\n+ mnem = 'vld4'\n+ elif optype == 0b1111:\n+ # vld4 single 4-element structure to all lanes\n+ mnem = 'vld4'\n+\n+ return opcode, mnem, opers, iflags, simdflags # no iflags, only simdflags for this one\n+\ndef adv_simd_32(val, va):\nu = (val>>24) & 1\nreturn _do_adv_simd_32(val, va, u)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
start for adv_simd_ldst
|
718,765 |
15.04.2019 15:01:50
| 14,400 |
d301637cddd722823344b430d1aa890f01d7aadd
|
Fix an issue with _div
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1801,8 +1801,8 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nat the specified location (or -1 if no terminator\nis found in the memory map)\n\"\"\"\n- offset,bytes = self.getByteDef(va)\n- foff = bytes.find('\\x00', offset)\n+ offset, bytez = self.getByteDef(va)\n+ foff = bytez.find('\\x00', offset)\nif foff == -1:\nreturn foff\nreturn (foff - offset) + 1\n@@ -1813,8 +1813,8 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nat the specified location (or -1 if no terminator\nis found in the memory map)\n\"\"\"\n- offset,bytes = self.getByteDef(va)\n- foff = bytes.find('\\x00\\x00', offset)\n+ offset, bytez = self.getByteDef(va)\n+ foff = bytez.find('\\x00\\x00', offset)\nif foff == -1:\nreturn foff\nreturn (foff - offset) + 2\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/analysis.py",
"new_path": "vivisect/symboliks/analysis.py",
"diff": "@@ -476,13 +476,13 @@ class SymbolikAnalysisContext:\nBegins first node by applying self.preeffects and self.preconstraints\n'''\n- if graph == None:\n+ if graph is None:\ngraph = self.getSymbolikGraph(fva)\n# our callback routine for code path walking\ndef codewalker(ppath, edge, path):\n# first, test for the \"entry\" case\n- if ppath == None and edge == None:\n+ if ppath is None and edge is None:\nemu = self.getFuncEmu(fva)\nfor fname, funccb in self.funccb.items():\nemu.addFunctionCallback(fname, funccb)\n@@ -682,7 +682,7 @@ class SymbolikAnalysisContext:\n'''\nemu = self.__emu__(self.vw, *args)\nemu._sym_resolve = self._sym_resolve\n- if fva != None:\n+ if fva is not None:\nemu.setupFunctionCall(fva, args=fargs)\nreturn emu\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/amd64.py",
"new_path": "vivisect/symboliks/archs/amd64.py",
"diff": "@@ -124,7 +124,7 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\nrdx = Var('rdx', self._psize)\nnum = (rdx << Const(64, self._psize)) + rax\ntemp = num / denom\n- if isInvalid(temp):\n+ if temp.isDiscrete() and isInvalid(temp):\n# TODO: make effect\nraise envi.DivideError('AMD64 i_div #DE')\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -334,7 +334,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\ndef _div(self, op, isInvalid=None):\noper = op.opers[0]\n- divbase = self.getOperObj(op, 1)\n+ divbase = self.getOperObj(op, 0)\nif isInvalid is None:\nlimit = (2 ** (oper.tsize * 8)) - 1\nisInvalid = lambda val: val > limit\n@@ -343,7 +343,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nax = self.getRegObj(e_i386.REG_AX)\nquot = ax / divbase\nrem = ax % divbase\n- if isInvalid(quot):\n+ if quot.isDiscrete() and isInvalid(quot):\nraise envi.DivideError('i386 #DE')\nself.effSetVariable('eax', (rem << 8) + quot)\n@@ -353,7 +353,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\ntot = (edx << Const(16, self._psize)) + eax\nquot = tot / divbase\nrem = tot % divbase\n- if isInvalid(quot):\n+ if quot.isDiscrete() and isInvalid(quot):\nraise envi.DivideError('i386 #DE')\nself.effSetVariable('eax', quot)\nself.effSetVariable('edx', rem)\n@@ -364,7 +364,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\ntot = (edx << Const(32, self._psize)) + eax\nquot = tot / divbase\nrem = tot % divbase\n- if isInvalid(quot):\n+ if quot.isDiscrete() and isInvalid(quot):\nraise envi.DivideError('i386 #DE')\nself.effSetVariable('eax', quot)\nself.effSetVariable('edx', rem)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Fix an issue with _div
|
718,770 |
16.04.2019 15:49:15
| 14,400 |
c7e01f61a3ebf6274be5a6383cb38013d7a42943
|
inc size for ArmExtRegListOper
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -4933,10 +4933,11 @@ class ArmExtRegListOper(ArmOperand):\n'''\nextended register list: Vector/FP registers\n'''\n- def __init__(self, firstreg, count, size):\n+ def __init__(self, firstreg, count, size, inc=1):\nself.firstreg = firstreg\nself.count = count\nself.size = size # 0 or 1, meaning 32bit or 64bit\n+ self.inc = inc\ndef __eq__(self, oper):\nif not isinstance(oper, self.__class__):\n@@ -4947,6 +4948,8 @@ class ArmExtRegListOper(ArmOperand):\nreturn False\nif self.size != oper.size:\nreturn False\n+ if self.inc != oper.inc:\n+ return False\nreturn True\ndef isDeref(self):\n@@ -4956,7 +4959,7 @@ class ArmExtRegListOper(ArmOperand):\nregbase = (\"s%d\", \"d%d\")[self.size]\nmcanv.addText('{')\ntop = self.count-1\n- for l in xrange(self.count):\n+ for l in xrange(0, self.count, self.inc):\nvreg = self.firstreg + l\nmcanv.addNameText(regbase % vreg, typename='registers')\nif l < top:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
inc size for ArmExtRegListOper
|
718,770 |
16.04.2019 15:49:37
| 14,400 |
ba09790b36cbdd461f4b68596e675d9499309a8a
|
start on adv_simd_ldst_32
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1779,12 +1779,19 @@ def coproc_simd_32(va, val1, val2):\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n-from envi.archs.arm.disasm import _do_adv_simd_32, _do_fp_dp\n+from envi.archs.arm.disasm import _do_adv_simd_32, _do_fp_dp, _do_adv_simd_ldst_32\ndef fp_dp(va, val1, val2):\nopcode, mnem, opers, iflags, simdflags = _do_fp_dp(va, val1, val2)\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n+def adv_simd_ldst_32(va, val1, val2):\n+ val = (val1 << 16) | val2\n+ u = (val1 >> 12) & 1\n+ opcode, mnem, opers, iflags, simdflags = _do_adv_simd_ldst_32(val, va, u)\n+ #print \"simdflags: %r\" % simdflags\n+ return COND_AL, opcode, mnem, opers, iflags, simdflags\n+\ndef adv_simd_32(va, val1, val2):\nval = (val1 << 16) | val2\nu = (val1 >> 12) & 1\n@@ -2006,6 +2013,9 @@ thumb_base = [\n('1011010', (INS_PUSH,'push', push_reglist, 0)), # PUSH <reglist>\n('10110110010', (INS_SETEND,'setend', sh4_imm1, 0)), # SETEND <endian_specifier>\n('10110110011', (INS_CPS,'cps', cps16,0)), # CPS<effect> <iflags>\n+ ('1011011000', (INS_PUSH,'push', push_reglist, 0)), # PUSH <reglist>\n+ ('101101101', (INS_PUSH,'push', push_reglist, 0)), # PUSH <reglist>\n+ ('10110111', (INS_PUSH,'push', push_reglist, 0)), # PUSH <reglist>\n('10110001', (INS_CBZ,'cbz', i_imm5_rn, envi.IF_COND | envi.IF_BRANCH)), # CBZ{<q>} <Rn>, <label> # label must be positive, even offset from PC\n('10111001', (INS_CBNZ,'cbnz', i_imm5_rn, envi.IF_COND | envi.IF_BRANCH)), # CBNZ{<q>} <Rn>, <label> # label must be positive, even offset from PC\n('10110011', (INS_CBZ,'cbz', i_imm5_rn, envi.IF_COND | envi.IF_BRANCH)), # CBZ{<q>} <Rn>, <label> # label must be positive, even offset from PC\n@@ -2141,6 +2151,14 @@ thumb2_extension = [\n('11101110', (IENC_COPROC_SIMD,'coproc simd', coproc_simd_32, IF_THUMB32)),\n('11101111', (IENC_ADVSIMD,'adv simd', adv_simd_32, IF_THUMB32)),\n('1111110', (IENC_COPROC_SIMD,'coproc simd', coproc_simd_32, IF_THUMB32)),\n+ ('111110010000', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110010010', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110010100', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110010110', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110011000', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110011010', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110011100', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n+ ('111110011110', (IENC_ADVSIMD,'adv simd ld/st', adv_simd_ldst_32, IF_THUMB32)),\n('11111110', (IENC_COPROC_SIMD,'coproc simd', coproc_simd_32, IF_THUMB32)),\n('11111111', (IENC_ADVSIMD,'adv simd', adv_simd_32, IF_THUMB32)),\n@@ -2219,6 +2237,7 @@ thumb2_extension = [\n('111110010001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n('111110011001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n('111110011011', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n+ # see adv simd as well\n# data-processing (register)\n('111110100', (None, 'shift_or_extend', shift_or_ext_32, IF_THUMB32)),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/armthumb_tests.py",
"new_path": "envi/tests/armthumb_tests.py",
"diff": "@@ -4496,4 +4496,5 @@ advsimdtests = (\\\n(REV_ALL_ARM, '323efcf3', 0x7fcc, 'vcvt.f32.u32 d19, d18, #0x04', 0, ()),\n(REV_ALL_ARM, '123ffcf3', 0x7fe4, 'vcvt.u32.f32 d19, d2, #0x04', 0, ()),\n(REV_ALL_ARM, '323ffcf3', 0x7fec, 'vcvt.u32.f32 d19, d18, #0x04', 0, ()),\n+ (REV_ALL_ARM, '42f98f0a', 0x7fe1, 'vst1.32 {d16, d17},[r2]!', 0, ()),\n)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
start on adv_simd_ldst_32
|
718,765 |
17.04.2019 12:33:44
| 14,400 |
d6d235a4008a6acbf7082a46dbecf56e8a582c95
|
little more py3 compat thanks to atlas
|
[
{
"change_type": "MODIFY",
"old_path": "vtrace/notifiers.py",
"new_path": "vtrace/notifiers.py",
"diff": "@@ -45,7 +45,7 @@ class Notifier(object):\nclass VerboseNotifier(Notifier):\ndef notify(self, event, trace):\n- print \"PID %d - ThreadID (%d) got\" % (trace.getPid(), trace.getMeta(\"ThreadId\")),\n+ print(\"PID %d - ThreadID (%d) got\" % (trace.getPid(), trace.getMeta(\"ThreadId\"))),\nif event == vtrace.NOTIFY_ALL:\nprint(\"WTF, how did we get a vtrace.NOTIFY_ALL event?!?!\")\nelif event == vtrace.NOTIFY_SIGNAL:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
little more py3 compat thanks to atlas
|
718,770 |
21.04.2019 22:30:18
| 14,400 |
e96e275783c7b790a233217b43945d6d19740ac6
|
BugFix: ASR/LSR disasm/emu updates
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -231,6 +231,9 @@ def p_dp_imm_shift(opval, va):\nif (ocode == INS_MOV) and ((shval != 0) or (shtype != S_LSL)):\nmnem, opcode = dp_shift_mnem[shtype]\nif shtype != S_RRX: #if not rrx\n+ if shtype in (S_ASR, S_LSR) and shval == 0:\n+ shval = 32\n+\nolist = (\nArmRegOper(Rd, va=va),\nArmRegOper(Rm, va=va),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1420,15 +1420,19 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\n- imm5 = self.getOperValue(op, 2)\n+ shval = self.getOperValue(op, 2) & 0xff\nelse:\nsrc = self.getOperValue(op, 0)\n- imm5 = self.getOperValue(op, 1)\n+ shval = self.getOperValue(op, 1) & 0xff\n+\n+ if shval:\n+ val = src >> shval\n+ carry = (src >> (shval-1)) & 1\n+ else:\n+ val = src\n+ carry = 0\n- shift = (32, imm5)[bool(imm5)]\n- val = src >> shift\n- carry = (src >> (shift-1)) & 1\nself.setOperValue(op, 0, val)\nSflag = op.iflags & IF_PSR_S\n@@ -1442,20 +1446,23 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\nsrclen = op.opers[1].tsize\n- imm5 = self.getOperValue(op, 2)\n+ shval = self.getOperValue(op, 2) & 0xff\nelse:\nsrc = self.getOperValue(op, 0)\nsrclen = op.opers[0].tsize\n- imm5 = self.getOperValue(op, 1)\n+ shval = self.getOperValue(op, 1) & 0xff\n- shift = (32, imm5)[bool(imm5)]\n+ if shval:\nif e_bits.is_signed(src, srclen):\n- val = (src >> shift) | top_bits_32[shift]\n+ val = (src >> shval) | top_bits_32[shval]\n+ else:\n+ val = (src >> shval)\n+ carry = (src >> (shval-1)) & 1\nelse:\n- val = (src >> shift)\n+ val = src\n+ carry = 0\n- carry = (src >> (shift-1)) & 1\nself.setOperValue(op, 0, val)\nSflag = op.iflags & IF_PSR_S\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -206,6 +206,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\ntry:\nself.emumon.prehook(self, op, starteip)\nexcept Exception, e:\n+ if not self.getMeta('silent'):\nprint(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon prehook)\" % (funcva, starteip, op, e))\nif self.emustop:\n@@ -221,6 +222,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\ntry:\nself.emumon.posthook(self, op, endeip)\nexcept Exception, e:\n+ if not self.getMeta('silent'):\nprint(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon posthook)\" % (funcva, starteip, op, e))\nif self.emustop:\nreturn\n@@ -259,7 +261,6 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nlogger.debug('runFunction continuing after unsupported instruction: 0x%08x %s', e.op.va, e.op.mnem)\nself.setProgramCounter(e.op.va+ e.op.size)\nexcept Exception, e:\n- #traceback.print_exc()\nif self.emumon != None:\nself.emumon.logAnomaly(self, starteip, str(e))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
BugFix: ASR/LSR disasm/emu updates
|
718,765 |
23.04.2019 10:16:01
| 14,400 |
ca94ba743811d134258897ecefa26435dbed1d09
|
Add more relocations types to PE files (need moar). Fix potential bug in reloc analysis pass (that thankfully never triggered b/c we never used that case. flake8 fixes. moar instructions for symboliks
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/vmcslookup.py",
"new_path": "envi/archs/amd64/vmcslookup.py",
"diff": "@@ -145,6 +145,4 @@ VMCS_NAMES = {\n0x6812: 'Host_IA32_SYSENTER_EIP',\n0x6814: 'Host_RSP',\n0x6816: 'Host_RIP',\n-\n-\n}\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opconst.py",
"new_path": "envi/archs/i386/opconst.py",
"diff": "@@ -52,11 +52,11 @@ OPTYPE_x = 0x11000000 # 2 always word\nOPTYPE_y = 0x12000000 # 4/8 dword or qword\nOPTYPE_z = 0x13000000 # 2/4 is this OPTYPE_z? word for 16-bit operand size or doubleword for 32 or 64-bit operand-size\n-OPTYPE_fs = 0x14000000 #\n-OPTYPE_fd = 0x15000000 #\n-OPTYPE_fe = 0x16000000 #\n-OPTYPE_fb = 0x17000000 #\n-OPTYPE_fv = 0x18000000 #\n+OPTYPE_fs = 0x14000000\n+OPTYPE_fd = 0x15000000\n+OPTYPE_fe = 0x16000000\n+OPTYPE_fb = 0x17000000\n+OPTYPE_fv = 0x18000000\n# FIXME this should probably be a list rather than a dictionary\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/relocations.py",
"new_path": "vivisect/analysis/generic/relocations.py",
"diff": "@@ -5,10 +5,11 @@ point to valid locations.\nimport vivisect\n+\ndef analyze(vw):\nfor fname, vaoff, rtype, data in vw.getRelocations():\n- if rtype == vivisect.RTYPE_BASERELOC and not vw.isLocation(va):\n- vw.makePointer(va, follow=True)\n+ if rtype == vivisect.RTYPE_BASERELOC and not vw.isLocation(vaoff):\n+ vw.makePointer(vaoff, follow=True)\nelif rtype == vivisect.RTYPE_BASEOFF:\nimgbase = vw.getFileMeta(fname, 'imagebase')\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "-\nimport os\nimport PE\nimport logging\n@@ -27,27 +26,32 @@ logger = logging.getLogger(__name__)\n# 0x166 MIPS R4000\n# 0x183 DEC Alpha AXP\n+\ndef parseFile(vw, filename, baseaddr=None):\npe = PE.PE(file(filename, \"rb\"))\nreturn loadPeIntoWorkspace(vw, pe, filename, baseaddr=baseaddr)\n+\ndef parseBytes(vw, bytes, baseaddr=None):\nfd = StringIO.StringIO(bytes)\nfd.seek(0)\npe = PE.PE(fd)\nreturn loadPeIntoWorkspace(vw, pe, filename=filename, baseaddr=baseaddr)\n+\ndef parseMemory(vw, memobj, base):\npe = PE.peFromMemoryObject(memobj, base)\nmapbase, mapsize, perms, fname = memobj.getMemoryMap(base)\n# FIXME does the PE's load address get fixedup on rebase?\nreturn loadPeIntoWorkspace(vw, pe, fname)\n+\ndef parseFd(vw, fd, filename=None, baseaddr=None):\nfd.seek(0)\npe = PE.PE(fd)\nreturn loadPeIntoWorkspace(vw, pe, filename=filename, baseaddr=baseaddr)\n+\narch_names = {\nPE.IMAGE_FILE_MACHINE_I386: 'i386',\nPE.IMAGE_FILE_MACHINE_AMD64: 'amd64',\n@@ -61,9 +65,12 @@ defcalls = {\n# map PE relocation types to vivisect types where possible\nrelmap = {\n+ PE.IMAGE_REL_BASED_ABSOLUTE: vivisect.RTYPE_BASERELOC,\nPE.IMAGE_REL_BASED_HIGHLOW: vivisect.RTYPE_BASEOFF,\n+ PE.IMAGE_REL_BASED_DIR64: vivisect.RTYPE_BASEOFF,\n}\n+\ndef loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nmach = pe.IMAGE_NT_HEADERS.FileHeader.Machine\n@@ -119,12 +126,12 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\n# Add file version info if VS_VERSIONINFO has it\ntry:\nvs = pe.getVS_VERSIONINFO()\n- except Exception, e:\n+ except Exception as e:\nvs = None\nvw.vprint('Failed to load version info resource due to %s' % (repr(e),))\n- if vs != None:\n+ if vs is not None:\nvsver = vs.getVersionValue('FileVersion')\n- if vsver != None and len(vsver):\n+ if vsver is not None and len(vsver):\n# add check to split seeing samples with spaces and nothing else..\nparts = vsver.split()\nif len(parts):\n@@ -150,9 +157,7 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\n# Add the first page mapped in from the PE header.\nheader = pe.readAtOffset(0, header_size)\n-\nsecalign = pe.IMAGE_NT_HEADERS.OptionalHeader.SectionAlignment\n-\nsubsys_majver = pe.IMAGE_NT_HEADERS.OptionalHeader.MajorSubsystemVersion\nsubsys_minver = pe.IMAGE_NT_HEADERS.OptionalHeader.MinorSubsystemVersion\n@@ -227,7 +232,6 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nif chars & PE.IMAGE_SCN_CNT_CODE:\nmapflags |= e_mem.MM_EXEC\n-\nsecrva = sec.VirtualAddress\nsecvsize = sec.VirtualSize\nsecfsize = sec.SizeOfRawData\n@@ -297,7 +301,7 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nif not (chars & PE.IMAGE_SCN_CNT_CODE) and not (chars & PE.IMAGE_SCN_MEM_EXECUTE) and not (chars & PE.IMAGE_SCN_MEM_WRITE):\nvw.markDeadData(secbase, secbase+len(secbytes))\n- except Exception, e:\n+ except Exception as e:\nprint(\"Error Loading Section (%s size:%d rva:%.8x offset: %d): %s\" % (secname,secfsize,secrva,secoff,e))\nvw.addExport(entry, EXP_FUNCTION, '__entry', fname)\n@@ -314,7 +318,7 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\n# map PE reloc to VIV reloc ( or dont... )\nvtype = relmap.get(rtype)\nif vtype is None:\n- logger.info('Skipping PE Relocation type: %d (no handler)', rtype)\n+ logger.info('Skipping PE Relocation type: %d at %d (no handler)', rtype, rva)\ncontinue\nmapoffset = vw.readMemoryPtr(rva + baseaddr) - baseaddr\n@@ -341,7 +345,7 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nvw.addExport(eva, EXP_UNTYPED, name, fname)\nif vw.probeMemory(eva, 1, e_mem.MM_EXEC):\nvw.addEntryPoint(eva)\n- except Exception, e:\n+ except Exception as e:\nvw.vprint('addExport Failed: %s.%s (0x%.8x): %s' % (fname, name, eva, e))\n# Save off the ordinals...\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/amd64.py",
"new_path": "vivisect/symboliks/archs/amd64.py",
"diff": "@@ -110,7 +110,7 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\ndef _div(self, op, isInvalid=None):\noper = op.opers[0]\n- denom = self.getOperObj(op, 1)\n+ denom = self.getOperObj(op, 0)\nif denom == 0:\n# TODO: make effect\nraise envi.DivideByZero('AMD64 Divide by zero')\n@@ -138,6 +138,10 @@ class Amd64SymbolikTranslator(vsym_i386.IntelSymbolikTranslator):\ndef i_div(self, op):\nreturn self._div(op)\n+ def i_cdq(self, op):\n+ v1 = o_sextend(self.getRegObj(e_amd64.REG_EAX), Const(self._psize, self._psize))\n+ self.effSetVariable('rax', v1)\n+\ndef i_jecxz(self, op):\nreturn vsym_i386.IntelSymbolikTranslator.i_jecxz(self, op)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -451,6 +451,29 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.effSetVariable('eflags_cf', f)\nself.effSetVariable('eflags_of', f)\n+ def i_mulsd(self, op):\n+ '''\n+ Also doesn't set flags?\n+ '''\n+ ocount = len(op.opers)\n+ if ocount == 2:\n+ dst = self.getOperObj(op, 0)\n+ src = self.getOperObj(op, 1)\n+ dsize = op.opers[0].tsize\n+ res = dst * src\n+ self.setOperObj(op, 0, res)\n+\n+ elif ocount == 3:\n+ dst = self.getOperObj(op, 0)\n+ src1 = self.getOperObj(op, 1)\n+ src2 = self.getOperObj(op, 2)\n+ res = src1 * src2\n+ self.setOperObj(op, 0, res)\n+\n+ else:\n+ raise Exception(\"WTFO? i_mul with no opers\")\n+\n+\ndef i_inc(self, op):\nv1 = self.getOperObj(op, 0)\nobj = o_add(v1, Const(1, self._psize), v1.getWidth())\n@@ -844,6 +867,15 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.effSetVariable('eflags_eq', eq(v1, v2)) # v1 - v2 == 0 :: v1 == v2\nself.setOperObj(op, 0, obj)\n+ def i_subsd(self, op):\n+ '''\n+ None of the ref docs say subsd affects any flags\n+ '''\n+ v1 = self.getOperObj(op, 0)\n+ v2 = self.getOperObj(op, 1)\n+ obj = o_sub(v1, v2, v1.getWidth())\n+ self.setOperObj(op, 0, obj)\n+\ndef i_test(self, op):\nv1 = self.getOperObj(op, 0)\nv2 = self.getOperObj(op, 1)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Add more relocations types to PE files (need moar). Fix potential bug in reloc analysis pass (that thankfully never triggered b/c we never used that case. flake8 fixes. moar instructions for symboliks
|
718,765 |
23.04.2019 13:03:07
| 14,400 |
463529d665555c44acb68ca6358165c6a034b6e3
|
No cdq for i386 right now. Need other plumbing. add xorp* insts
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/archs/i386.py",
"new_path": "vivisect/symboliks/archs/i386.py",
"diff": "@@ -586,6 +586,7 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\n# actual mathematical operation\ni_movnti = i_mov\ni_movq = i_mov\n+ i_movd = i_mov\ni_movaps = i_mov\ni_movapd = i_mov\ni_movups = i_mov\n@@ -720,6 +721,12 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nv1 = o_sextend(self.getRegObj(e_i386.REG_AX), Const(self._psize, self._psize))\nself.effSetVariable('eax', v1)\n+ #def i_cdq(self, op):\n+ # # TODO: So this sign extends things into edx, so we need to grab the sign bit in eax\n+ # # and then fill in all the bits of edx\n+ # v1 = o_sextend(self.getRegObj(e_i386.REG_EAX), Const(self._psize, self._psize))\n+ # self.effSetVariable('edx', v1)\n+\ndef _carry_eq(self, x):\nreturn eq(Var('eflags_cf', self._psize), Const(x, self._psize))\n@@ -909,6 +916,14 @@ class IntelSymbolikTranslator(vsym_trans.SymbolikTranslator):\nself.effSetVariable('eflags_eq', eq(obj, Const(0, self._psize))) # v1 & v2 == 0\nself.setOperObj(op, 0, obj)\n+ def i_xorpd(self, op):\n+ v1 = self.getOperObj(op, 0)\n+ v2 = self.getOperObj(op, 1)\n+ obj = o_xor(v1, v2, v1.getWidth())\n+ self.setOperObj(op, 0, obj)\n+\n+ i_xorps = i_xorpd\n+\ndef i_cmpxchg(self, op):\n# FIXME CATASTROPHIC THIS CONTAINS BRANCHING LOGIC STATE!\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/translator.py",
"new_path": "vivisect/symboliks/translator.py",
"diff": "@@ -46,7 +46,7 @@ class SymbolikTranslator:\nself._cur_va = op.va\nmeth = self._op_methods.get(op.mnem, None)\nif meth is None:\n- print('%s Needs: %s' % (self.__class__.__name__,repr(op)))\n+ # print('%s: %s Needs: %s' % (hex(op.va), self.__class__.__name__, repr(op)))\nself.effDebug(\"%s Needs %s\" % (self.__class__.__name__, repr(op)))\nreturn DebugEffect(op.va, \"%s Needs %s\" % (self.__class__.__name__, repr(op)))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
No cdq for i386 right now. Need other plumbing. add xorp* insts
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.