author
int64 658
755k
| date
stringlengths 19
19
| timezone
int64 -46,800
43.2k
| hash
stringlengths 40
40
| message
stringlengths 5
490
| mods
list | language
stringclasses 20
values | license
stringclasses 3
values | repo
stringlengths 5
68
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stringlengths 12
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718,770 |
28.03.2017 00:03:50
| 14,400 |
47fc710c01880306bbe6535995b4f6836e032c74
|
cleanup old ways of Opcode mnemonic modification for SIMD.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3848,80 +3848,6 @@ class ArmOpcode(envi.Opcode):\nmnem += 'id'\nif self.simdflags:\n- '''\n- if self.simdflags & IFS_S32_F64:\n- mnem += '.s32.f64'\n- elif self.simdflags & IFS_S32_F32:\n- mnem += '.s32.f32'\n- elif self.simdflags & IFS_U32_F64:\n- mnem += '.u32.f64'\n- elif self.simdflags & IFS_U32_F32:\n- mnem += '.u32.f32'\n- elif self.simdflags & IFS_F64_S32:\n- mnem += '.f64.s32'\n- elif self.simdflags & IFS_F64_U32:\n- mnem += '.f64.u32'\n- elif self.simdflags & IFS_F32_S32:\n- mnem += '.f32.s32'\n- elif self.simdflags & IFS_F32_U32:\n- mnem += '.f32.u32'\n- elif self.simdflags & IFS_F32_64:\n- mnem += '.f32.f64'\n- elif self.simdflags & IFS_F64_32:\n- mnem += '.f64.f32'\n- elif self.simdflags & IFS_F16_32:\n- mnem += '.f16.f32'\n- elif self.simdflags & IFS_F32_16:\n- mnem += '.f32.f16'\n- elif self.simdflags & IFS_F64:\n- mnem += '.f64'\n- elif self.simdflags & IFS_S64:\n- mnem += '.s64'\n- elif self.simdflags & IFS_U64:\n- mnem += '.u64'\n- elif self.simdflags & IFS_I64:\n- mnem += '.i64'\n- elif self.simdflags & IFS_F32:\n- mnem += '.f32'\n- elif self.simdflags & IFS_S32:\n- mnem += '.s32'\n- elif self.simdflags & IFS_U32:\n- mnem += '.u32'\n- elif self.simdflags & IFS_I32:\n- mnem += '.i32'\n- elif self.simdflags & IFS_F16:\n- mnem += '.f16'\n- elif self.simdflags & IFS_S16:\n- mnem += '.s16'\n- elif self.simdflags & IFS_U16:\n- mnem += '.u16'\n- elif self.simdflags & IFS_I16:\n- mnem += '.i16'\n- elif self.simdflags & IFS_F8:\n- mnem += '.f8'\n- elif self.simdflags & IFS_S8:\n- mnem += '.s8'\n- elif self.simdflags & IFS_U8:\n- mnem += '.u8'\n- elif self.simdflags & IFS_I8:\n- mnem += '.i8'\n- elif self.simdflags & IFS_P8:\n- mnem += '.p8'\n- elif self.simdflags & IFS_P16:\n- mnem += '.p16'\n- elif self.simdflags & IFS_P32:\n- mnem += '.p32'\n- elif self.simdflags & IFS_P64:\n- mnem += '.p64'\n- elif self.simdflags & IFS_8:\n- mnem += '.8'\n- elif self.simdflags & IFS_16:\n- mnem += '.16'\n- elif self.simdflags & IFS_32:\n- mnem += '.32'\n- elif self.simdflags & IFS_64:\n- mnem += '.64'\n- '''\nmnem += IFS[self.simdflags]\n#FIXME: Advanced SIMD modifiers (IF_V*)\n@@ -3969,80 +3895,6 @@ class ArmOpcode(envi.Opcode):\nmnem += 'id'\nif self.simdflags:\n- '''\n- if self.simdflags & IFS_S32_F64:\n- mnem += '.s32.f64'\n- elif self.simdflags & IFS_S32_F32:\n- mnem += '.s32.f32'\n- elif self.simdflags & IFS_U32_F64:\n- mnem += '.u32.f64'\n- elif self.simdflags & IFS_U32_F32:\n- mnem += '.u32.f32'\n- elif self.simdflags & IFS_F64_S32:\n- mnem += '.f64.s32'\n- elif self.simdflags & IFS_F64_U32:\n- mnem += '.f64.u32'\n- elif self.simdflags & IFS_F32_S32:\n- mnem += '.f32.s32'\n- elif self.simdflags & IFS_F32_U32:\n- mnem += '.f32.u32'\n- elif self.simdflags & IFS_F32_64:\n- mnem += '.f32.f64'\n- elif self.simdflags & IFS_F64_32:\n- mnem += '.f64.f32'\n- elif self.simdflags & IFS_F16_32:\n- mnem += '.f16.f32'\n- elif self.simdflags & IFS_F32_16:\n- mnem += '.f32.f16'\n- elif self.simdflags & IFS_F64:\n- mnem += '.f64'\n- elif self.simdflags & IFS_S64:\n- mnem += '.s64'\n- elif self.simdflags & IFS_U64:\n- mnem += '.u64'\n- elif self.simdflags & IFS_I64:\n- mnem += '.i64'\n- elif self.simdflags & IFS_F32:\n- mnem += '.f32'\n- elif self.simdflags & IFS_S32:\n- mnem += '.s32'\n- elif self.simdflags & IFS_U32:\n- mnem += '.u32'\n- elif self.simdflags & IFS_I32:\n- mnem += '.i32'\n- elif self.simdflags & IFS_F16:\n- mnem += '.f16'\n- elif self.simdflags & IFS_S16:\n- mnem += '.s16'\n- elif self.simdflags & IFS_U16:\n- mnem += '.u16'\n- elif self.simdflags & IFS_I16:\n- mnem += '.i16'\n- elif self.simdflags & IFS_F8:\n- mnem += '.f8'\n- elif self.simdflags & IFS_S8:\n- mnem += '.s8'\n- elif self.simdflags & IFS_U8:\n- mnem += '.u8'\n- elif self.simdflags & IFS_I8:\n- mnem += '.i8'\n- elif self.simdflags & IFS_P8:\n- mnem += '.p8'\n- elif self.simdflags & IFS_P16:\n- mnem += '.p16'\n- elif self.simdflags & IFS_P32:\n- mnem += '.p32'\n- elif self.simdflags & IFS_P64:\n- mnem += '.p64'\n- elif self.simdflags & IFS_8:\n- mnem += '.8'\n- elif self.simdflags & IFS_16:\n- mnem += '.16'\n- elif self.simdflags & IFS_32:\n- mnem += '.32'\n- elif self.simdflags & IFS_64:\n- mnem += '.64'\n- '''\nmnem += IFS[self.simdflags]\nif self.iflags & IF_THUMB32:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup old ways of Opcode mnemonic modification for SIMD.
|
718,770 |
28.03.2017 00:18:31
| 14,400 |
a7f96b3a0c43943e7fd1757794b7f238c536dd85
|
emulator bugfixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3795,7 +3795,7 @@ class ArmOpcode(envi.Opcode):\nif self.opcode in (INS_BLX, INS_BX):\nif operval & 3:\n- flags |= envi.ARCH_THUMB16\n+ flags |= envi.ARCH_THUMB\noperval &= -2\nelse:\nflags |= envi.ARCH_ARMV7\n@@ -3809,6 +3809,7 @@ class ArmOpcode(envi.Opcode):\nif self.iflags & envi.IF_CALL:\nflags |= envi.BR_PROC\nret.append((operval, flags))\n+ print \"getBranches: add 0x%x %x\"% (operval, flags)\nreturn ret\n@@ -4962,7 +4963,7 @@ class ArmCoprocOption(ArmImmOffsetOper):\nbasereg = arm_regs[self.base_reg][0]\nmcanv.addText('[')\nmcanv.addNameText(basereg, typename='registers')\n- mcanv.addVaText('], {%s}' % self.offset)\n+ mcanv.addText('], {%s}' % self.offset)\ndef repr(self, op):\nreturn '[%s], {%s}' % (arm_regs[self.base_reg][0],self.offset)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -706,8 +706,9 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, val)\ndef i_movt(self, op):\n+ base = self.getOperValue(op, 0) & 0xffff\nval = self.getOperValue(op, 1) << 16\n- self.setOperValue(op, 0, val)\n+ self.setOperValue(op, 0, base | val)\ndef i_movw(self, op):\nval = self.getOperValue(op, 1)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
emulator bugfixes
|
718,770 |
28.03.2017 10:14:30
| 14,400 |
c3f5e72e12fb023216080953f7aedf414672bcf1
|
disasm and emu of branches: bugfixes and consistency
|
[
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -295,8 +295,8 @@ class IMemory:\nExample: op = m.parseOpcode(0x7c773803)\n'''\n- b = self.readMemory(va, 16)\n- return self.imem_archs[ arch >> 16 ].archParseOpcode(b, 0, va)\n+ off, b = self.getByteDef(va)\n+ return self.imem_archs[ (arch & envi.ARCH_MASK) >> 16 ].archParseOpcode(b, off, va)\nclass MemoryCache(IMemory):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
disasm and emu of branches: bugfixes and consistency
|
718,770 |
28.03.2017 10:15:15
| 14,400 |
4359ff4e31cc94808100e487961b490852702544
|
disasm and emu of branches: bugfixes and consistency (reverted from commit 0b3b98487aeed40b38226de6fa45f090b8ade124)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -172,7 +172,7 @@ COND_PL = 0x5 # n==0 (plus/positive or zero)\nCOND_VS = 0x6 # v==1 (overflow)\nCOND_VC = 0x7 # v==0 (no overflow)\nCOND_HI = 0x8 # c==1 and z==0 (unsigned higher)\n-COND_LO = 0x9 # c==0 or z==1 (unsigned lower or same)\n+COND_LS = 0x9 # c==0 or z==1 (unsigned lower or same)\nCOND_GE = 0xA # n==v (signed greater than or equal) (n==1 and v==1) or (n==0 and v==0)\nCOND_LT = 0xB # n!=v (signed less than) (n==1 and v==0) or (n==0 and v==1)\nCOND_GT = 0xC # z==0 and n==v (signed greater than)\n@@ -190,7 +190,7 @@ COND_PL:\"pl\", # Plus/positive or zero N clear\nCOND_VS:\"vs\", # Overflow V set\nCOND_VC:\"vc\", # No overflow V clear\nCOND_HI:\"hi\", # Unsigned higher C set and Z clear\n-COND_LO:\"lo\", # Unsigned lower or same C clear or Z set\n+ COND_LS:\"ls\", # Unsigned lower or same C clear or Z set\nCOND_GE:\"ge\", # Signed greater than or equal N set and V set, or N clear and V clear (N == V)\nCOND_LT:\"lt\", # Signed less than N set and V clear, or N clear and V set (N!= V)\nCOND_GT:\"gt\", # Signed greater than Z clear, and either N set and V set, or N clear and V clear (Z == 0,N == V)\n@@ -208,7 +208,7 @@ COND_PL:5, # Plus/positive or zero N clear\nCOND_VS:6, # Overflow V set\nCOND_VC:7, # No overflow V clear\nCOND_HI:8, # Unsigned higher C set and Z clear\n-COND_LO:9, # Unsigned lower or same C clear or Z set\n+ COND_LS:9, # Unsigned lower or same C clear or Z set\nCOND_GE:10, # Signed greater than or equal N set and V set, or N clear and V clear (N == V)\nCOND_LT:11, # Signed less than N set and V clear, or N clear and V set (N!= V)\nCOND_GT:12, # Signed greater than Z clear, and either N set and V set, or N clear and V clear (Z == 0,N == V)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -201,6 +201,9 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nnote: differs from the IMemory interface by checking loclist\n'''\n+ if arch == envi.ARCH_DEFAULT:\n+ arch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[self.getFlag(PSR_T_bit)]\n+\noff, b = self.getByteDef(va)\nreturn self.imem_archs[ (arch & envi.ARCH_MASK) >> 16 ].archParseOpcode(b, off, va)\n@@ -655,11 +658,20 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# is the following necessary?\nnewpc = self.getRegister(REG_PC) # check whether pc has changed\nif pc != newpc:\n+ self.setThumbMode(newpc & 1)\nreturn newpc\ni_ldmia = i_ldm\ni_pop = i_ldmia\n+\n+ def setThumbMode(self, thumb=1):\n+ self.setFlag(PSR_T_bit, thumb)\n+\n+ def setArmMode(self, arm=1):\n+ self.setFlag(PSR_T_bit, not thumb)\n+\n+\n'''\ndef i_pop(self, op):\nsrcreg = op.opers[0].reg\n@@ -699,6 +711,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\nif op.opers[0].reg == REG_PC:\n+ self.setThumbMode(val & 1)\nreturn val\ndef i_mov(self, op):\n@@ -800,7 +813,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_b(self, op):\n'''\n- conditional branches (eg. bne) will be handled here\n+ conditional branches (eg. bne) will be handled here. they are all CONDITIONAL 'b'\n'''\nreturn self.getOperValue(op, 0)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -39,7 +39,7 @@ class simpleops:\noval = shmaskval(value, shval, mask)\noper = OperType[otype]((value >> shval) & mask, va=va)\nret.append( oper )\n- return (ret), None\n+ return COND_AL, (ret), None\n#imm5_rm_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 6, 0x1f))\nrm_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG, 6, 0x7))\n@@ -61,7 +61,7 @@ def d1_rm4_rd3(va, value):\nrdbit = shmaskval(value, 4, 0x8)\nrd = shmaskval(value, 0, 0x7) + rdbit\nrm = shmaskval(value, 3, 0xf)\n- return (ArmRegOper(rd, va=va),ArmRegOper(rm, va=va)), None\n+ return COND_AL,(ArmRegOper(rd, va=va),ArmRegOper(rm, va=va)), None\ndef rm_rn_rt(va, value):\nrt = shmaskval(value, 0, 0x7) # target\n@@ -69,7 +69,7 @@ def rm_rn_rt(va, value):\nrm = shmaskval(value, 6, 0x7) # offset\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmRegOffsetOper(rn, rm, va, pubwl=0x18)\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef imm54_rn_rt(va, value):\nimm = shmaskval(value, 4, 0x7c)\n@@ -77,7 +77,7 @@ def imm54_rn_rt(va, value):\nrt = shmaskval(value, 0, 0x7)\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmImmOffsetOper(rn, imm, (va&0xfffffffc)+4, pubwl=0x18)\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef imm55_rn_rt(va, value):\nimm = shmaskval(value, 5, 0x3e)\n@@ -85,7 +85,7 @@ def imm55_rn_rt(va, value):\nrt = shmaskval(value, 0, 0x7)\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmImmOffsetOper(rn, imm, (va&0xfffffffc)+4, pubwl=0x18)\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef imm56_rn_rt(va, value):\nimm = shmaskval(value, 6, 0x1f)\n@@ -93,7 +93,7 @@ def imm56_rn_rt(va, value):\nrt = shmaskval(value, 0, 0x7)\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmImmOffsetOper(rn, imm, (va&0xfffffffc)+4, pubwl=0x18)\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef rd_sp_imm8(va, value): # add\nrd = shmaskval(value, 8, 0x7)\n@@ -101,7 +101,7 @@ def rd_sp_imm8(va, value): # add\noper0 = ArmRegOper(rd, va=va)\n# pre-compute PC relative addr\noper1 = ArmImmOffsetOper(REG_SP, imm, (va&0xfffffffc)+4, pubwl=0x18)\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef rd_pc_imm8(va, value): # add\nrd = shmaskval(value, 8, 0x7)\n@@ -109,14 +109,14 @@ def rd_pc_imm8(va, value): # add\noper0 = ArmRegOper(rd, va=va)\n# pre-compute PC relative addr\noper1 = ArmImmOper((va&0xfffffffc) + 4 + imm)\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef rt_pc_imm8(va, value): # ldr\nrt = shmaskval(value, 8, 0x7)\nimm = e_bits.signed((value & 0xff), 1) << 2\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmImmOffsetOper(REG_PC, imm, (va&0xfffffffc))\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\nbanked_regs = (\n@@ -183,7 +183,7 @@ def branch_misc(va, val, val2): # bl and misc control\nif (op1 & 0b101 == 0):\nif not (op & 0b0111000) == 0b0111000: # T3 encoding - conditional\ncond = (val>>6) & 0xf\n- opcode, mnem, nflags = bcc_ops.get(cond)\n+ opcode, mnem, nflags, cond = bcc_ops.get(cond)\nflags = envi.IF_BRANCH | nflags\n# break down the components\n@@ -200,7 +200,7 @@ def branch_misc(va, val, val2): # bl and misc control\nimm |= 0xff100000\noper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va)\n- return opcode, mnem, (oper0, ), flags, 0\n+ return cond, opcode, 'b', (oper0, ), flags, 0\nif op & 0b111 == 0b011:\n# miscellaneous control instructions\n@@ -216,7 +216,7 @@ def branch_misc(va, val, val2): # bl and misc control\nelse:\nopers = ()\n- return opcode, mnem, opers, None, 0\n+ return COND_AL, opcode, mnem, opers, None, 0\nif imm8 & 0b100000: # xx1xxxxx\nif (op & 0b1111110) == 0b0111000: # MSR (banked)\n@@ -238,7 +238,7 @@ def branch_misc(va, val, val2): # bl and misc control\nArmRegOper(treg),\nArmRegOper(Rn),\n)\n- return None, 'msr', opers, None, 0\n+ return COND_AL ,None, 'msr', opers, None, 0\nelif (op & 0b1111110 == 0b0111110): # MRS (banked)\nR = (val >> 4) & 1\n@@ -259,7 +259,7 @@ def branch_misc(va, val, val2): # bl and misc control\nArmRegOper(Rn),\nArmRegOper(treg),\n)\n- return None, 'mrs', opers, None, 0\n+ return COND_AL, None, 'mrs', opers, None, 0\nraise InvalidInstruction(\nmesg=\"branch_misc subsection 2\",\n@@ -274,9 +274,9 @@ def branch_misc(va, val, val2): # bl and misc control\nArmRegOper(REG_LR),\nArmImmOper(imm8),\n)\n- return None, 'sub', opers, IF_PSR_S, 0\n+ return COND_AL, None, 'sub', opers, IF_PSR_S, 0\n- return None, 'eret', tuple(), envi.IF_RET | envi.IF_NOFALL, 0\n+ return COND_AL, None, 'eret', tuple(), envi.IF_RET | envi.IF_NOFALL, 0\nprint \"TEST ME: branch_misc subsection 3\"\n##### FIXME! THIS NEEDS TO ALSO HIT MSR BELOW....\n#raise InvalidInstruction(\n@@ -302,7 +302,7 @@ def branch_misc(va, val, val2): # bl and misc control\nArmPgmStatRegOper(R, mask),\nArmRegOper(Rn)\n)\n- return None, 'msr', opers, None, 0\n+ return COND_AL, None, 'msr', opers, None, 0\nelif op == 0b0111001:\n@@ -349,7 +349,7 @@ def branch_misc(va, val, val2): # bl and misc control\nopcode, mnem = cpsh_mnems.get(op2, (INS_DEBUGHINT, 'dbg'))\n#raise Exception(\"FIXME: Change processor state ad hints p A6-234\")\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\nelif op == 0b0111011:\nraise Exception(\"FIXME: Misc control instrs p A6-235\")\n@@ -364,7 +364,7 @@ def branch_misc(va, val, val2): # bl and misc control\nArmRegOper(REG_LR),\nArmImmOper(imm8),\n)\n- return None, 'sub', opers, IF_PSR_S, 0\n+ return COND_AL, None, 'sub', opers, IF_PSR_S, 0\nelif op == 0b0111110:\nRd = (val2 >> 8) & 0xf\n@@ -372,7 +372,7 @@ def branch_misc(va, val, val2): # bl and misc control\nArmRegOper(Rd),\nArmRegOper(REG_OFFSET_CPSR),\n)\n- return None, 'mrs', opers, None, 0\n+ return COND_AL, None, 'mrs', opers, None, 0\nelif op == 0b0111111:\nRd = (val2 >> 8) & 0xf\n@@ -383,14 +383,14 @@ def branch_misc(va, val, val2): # bl and misc control\n)\nraise Exception(\"FIXME: MRS(register) p B9-1962 - how is R used?\")\n- return None, 'mrs', opers, None, 0\n+ return COND_AL, None, 'mrs', opers, None, 0\nelif op == 0b1111110:\nif op1 == 0:\nimm4 = val & 0xf\nimm12 = val2 & 0xfff\noper0 = ArmImmOper((imm4<<12)|imm12)\n- return None, 'hvc', (oper0,), None, 0\n+ return COND_AL, None, 'hvc', (oper0,), None, 0\nraise InvalidInstruction(\nmesg=\"branch_misc subsection 1\",\n@@ -401,7 +401,7 @@ def branch_misc(va, val, val2): # bl and misc control\nif op1 == 0:\nimm4 = val & 0xf\noper0 = ArmImmOper(imm4)\n- return None, 'smc', (oper0,), None, 0\n+ return COND_AL, None, 'smc', (oper0,), None, 0\nraise InvalidInstruction(\nmesg=\"branch_misc subsection 1\",\n@@ -427,7 +427,7 @@ def branch_misc(va, val, val2): # bl and misc control\nimm |= 0xfff00000\noper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va)\n- return opcode, 'b', (oper0, ), flags, 0\n+ return COND_AL, opcode, 'b', (oper0, ), flags, 0\nelif op1 == 0b010:\nif op == 0b1111111:\n@@ -456,7 +456,7 @@ def branch_misc(va, val, val2): # bl and misc control\noper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va&0xfffffffc)\n- return opcode, mnem, (oper0, ), flags, 0\n+ return COND_AL, opcode, mnem, (oper0, ), flags, 0\n@@ -467,14 +467,16 @@ def branch_misc(va, val, val2): # bl and misc control\ndef pc_imm11(va, value): # b\n- imm = e_bits.signed(((value & 0x7ff)<<1), 3)\n+ imm = e_bits.bsign_extend(((value & 0x7ff)<<1), 12, 32)\n+ imm = e_bits.signed(imm, 4)\noper0 = ArmPcOffsetOper(imm, va=va)\n- return (oper0,), None\n+ return COND_AL,(oper0,), None\ndef pc_imm8(va, value): # b\nimm = e_bits.signed(shmaskval(value, 0, 0xff), 1) * 2\n+ cond = (value >> 8) & 0xf\noper0 = ArmPcOffsetOper(imm, va=va)\n- return (oper0,), None\n+ return cond,(oper0,), None\ndef ldmia(va, value):\nrd = shmaskval(value, 8, 0x7)\n@@ -482,14 +484,14 @@ def ldmia(va, value):\noper0 = ArmRegOper(rd, va=va)\noper1 = ArmRegListOper(reg_list)\noper0.oflags |= OF_W\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef sp_sp_imm7(va, value):\nimm = shmaskval(value, 0, 0x7f)\no0 = ArmRegOper(REG_SP)\no1 = ArmRegOper(REG_SP)\no2 = ArmImmOper(imm*4)\n- return (o0,o1,o2), None\n+ return COND_AL,(o0,o1,o2), None\ndef rm_reglist(va, value):\nrm = shmaskval(value, 8, 0x7)\n@@ -497,7 +499,7 @@ def rm_reglist(va, value):\noper0 = ArmRegOper(rm, va=va)\noper1 = ArmRegListOper(reglist)\noper0.oflags |= OF_W\n- return (oper0,oper1), None\n+ return COND_AL,(oper0,oper1), None\ndef pop_reglist(va, value):\nflags = 0\n@@ -506,12 +508,12 @@ def pop_reglist(va, value):\nif reglist & 0x8000:\nflags |= envi.IF_NOFALL | envi.IF_RET\n- return (oper0,), flags\n+ return COND_AL,(oper0,), flags\ndef push_reglist(va, value):\nreglist = (value & 0xff) | ((value & 0x100)<<6)\noper0 = ArmRegListOper(reglist)\n- return (oper0,), None\n+ return COND_AL,(oper0,), None\ndef imm5_rm_rd(va, value):\nrd = value & 0x7\n@@ -522,7 +524,7 @@ def imm5_rm_rd(va, value):\noper0 = ArmRegOper(rd, va)\noper1 = ArmRegShiftImmOper(rm, stype, imm5, va)\n- return (oper0, oper1,), None\n+ return COND_AL,(oper0, oper1,), None\ndef i_imm5_rn(va, value):\n@@ -530,7 +532,7 @@ def i_imm5_rn(va, value):\nrn = value & 0x7\noper0 = ArmRegOper(rn, va)\noper1 = ArmPcOffsetOper(imm5, va)\n- return (oper0, oper1,), None\n+ return COND_AL,(oper0, oper1,), None\ndef ldm16(va, value):\nraise Exception(\"32bit wrapping of 16bit instruction... and it's not implemented\")\n@@ -542,12 +544,12 @@ def cps16(va, value):\nopers = (\nArmCPSFlagsOper(aif),\n)\n- return opers, (IF_IE, IF_ID)[im]\n+ return COND_AL,opers, (IF_IE, IF_ID)[im]\ndef itblock(va, val):\nmask = val & 0xf\nfirstcond = (val>>4) & 0xf\n- return (ThumbITOper(mask, firstcond),), None\n+ return COND_AL,(ThumbITOper(mask, firstcond),), None\nclass ThumbITOper(ArmOperand):\ndef __init__(self, mask, firstcond):\n@@ -604,6 +606,7 @@ class ThumbITOper(ArmOperand):\ndef getOperValue(self, idx, emu=None):\nreturn None\n+'''\ndef thumb32_01(va, val, val2):\nop = (val2>>15)&1\nop2 = (val>>4) & 0x7f\n@@ -634,7 +637,7 @@ def thumb32_01(va, val, val2):\nraise InvalidInstruction(\nmesg=\"Thumb32 failure\",\nbytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va)\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndef thumb32_10(va, val, val2):\n@@ -656,7 +659,7 @@ def thumb32_10(va, val, val2):\nraise InvalidInstruction(\nmesg=\"Thumb32 failure\",\nbytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va)\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndef thumb32_11(va, val, val2):\nop = (val2>>15)&1\n@@ -687,7 +690,8 @@ def thumb32_11(va, val, val2):\nif (op2 & 0x40) == 0x40:\nraise Exception('# Coprocessor, Advanced SIMD, Floating Point instrs')\n- return ( opcode, mnem, olist, flags, 0 )\n+ return COND_AL, ( opcode, mnem, olist, flags, 0 )\n+'''\ndef ROR_C(imm, bitcount, shift):\nm = shift % bitcount\n@@ -760,13 +764,13 @@ def dp_mod_imm_32(va, val1, val2):\noper1 = ArmRegOper(Rn)\noper2 = ArmImmOper(const)\nopers = (oper1, oper2)\n- return 0, mnem, opers, flags, 0\n+ return COND_AL, None, mnem, opers, flags, 0\noper0 = ArmRegOper(Rd)\noper1 = ArmRegOper(Rn)\noper2 = ArmImmOper(const)\nopers = (oper0, oper1, oper2)\n- return None, None, opers, flags, 0\n+ return COND_AL, None, None, opers, flags, 0\nsxt_mnem = (\n(INS_SXTAH, 'sxtah',),\n@@ -849,7 +853,7 @@ def shift_or_ext_32(va, val1, val2):\nif (op1 & 1):\nflags |= IF_PSR_S\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\n@@ -858,7 +862,7 @@ def pdp_32(va, val1, val2):\nraise Exception(\"Implement Me: pdp32: Saturated Instrs\")\npass\n- return None, None, None, None, None\n+ return COND_AL, None, None, None, None, None\ndef ubfx_32(va, val1, val2):\nrd = (val2>>8) & 0xf\n@@ -874,7 +878,7 @@ def ubfx_32(va, val1, val2):\nArmImmOper(lsbit),\nArmImmOper(widthm1 + 1),\n)\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\ndef dp_bin_imm_32(va, val1, val2): # p232\nflags = IF_THUMB32\n@@ -896,17 +900,17 @@ def dp_bin_imm_32(va, val1, val2): # p232\nopers = [oper0, oper2]\nif op in (0b00100, 0b01100): # movw, movt\n- return None, None, opers, 0, 0\n+ return COND_AL, None, None, opers, 0, 0\nRn = val1 & 0xf\nif Rn==15 and op in (0,0b1010): # add/sub\n# adr\n- return None, 'adr', opers, None, 0\n+ return COND_AL, None, 'adr', opers, None, 0\noper1 = ArmRegOper(Rn)\nopers.insert(1, oper1)\n- return None, None, opers, flags, 0\n+ return COND_AL, None, None, opers, flags, 0\ndef ldm_reg_mode_32(va, val1, val2):\n@@ -919,7 +923,7 @@ def ldm_reg_mode_32(va, val1, val2):\noper0.oflags = OF_W\noper1 = ArmModeOper(mode, wback)\nopers = (oper0, oper1)\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\ndef ldm_reg_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -929,7 +933,7 @@ def ldm_reg_32(va, val1, val2):\nif wback:\noper0.oflags = OF_W\nopers = (oper0,)\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\ndef ldm_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -944,7 +948,7 @@ def ldm_32(va, val1, val2):\noper0.oflags = OF_W\nopers = (oper0, oper1)\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\ndef pop_32(va, val1, val2):\nif val2 & 0x2000:\n@@ -956,7 +960,7 @@ def pop_32(va, val1, val2):\nif val2 & 0x8000:\nflags |= envi.IF_NOFALL | envi.IF_RET\n- return None, None, opers, flags, 0\n+ return COND_AL, None, None, opers, flags, 0\ndef push_32(va, val1, val2):\nif val2 & 0x2000:\n@@ -964,7 +968,7 @@ def push_32(va, val1, val2):\n# PC not ok on some instructions...\noper0 = ArmRegListOper(val2)\nopers = (oper0, )\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\ndef strex_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -978,7 +982,7 @@ def strex_32(va, val1, val2):\nopers = (oper0, oper1, oper2)\nflags = 0\n- return None, None, opers, flags, 0\n+ return COND_AL, None, None, opers, flags, 0\ndef ldr_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -989,7 +993,7 @@ def ldr_32(va, val1, val2):\noper1 = ArmImmOffsetOper(rn, imm12, va=va)\nopers = (oper0, oper1)\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\nldrb_instrs = (\n(INS_LDR, 'ldr', IF_B|IF_THUMB32),\n@@ -1062,7 +1066,7 @@ def ldrb_memhints_32(va, val1, val2):\nmesg=\"ldrb_memhints_32: fall 1\", va=va)\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndef ldr_puw_32(va, val1, val2):\n@@ -1081,7 +1085,7 @@ def ldr_puw_32(va, val1, val2):\noper1 = ArmImmOffsetOper(rn, imm8, va=va, pubwl=pubwl)\nopers = (oper0, oper1)\n- return None, None, opers, None, 0\n+ return COND_AL, None, None, opers, None, 0\ndef ldrex_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -1093,7 +1097,7 @@ def ldrex_32(va, val1, val2):\nopers = (oper0, oper1)\nflags = 0\n- return None, None, opers, flags, 0\n+ return COND_AL, None, None, opers, flags, 0\ndef ldrd_imm_32(va, val1, val2):\npubwl = (val1 >> 4) & 0x1f\n@@ -1108,7 +1112,7 @@ def ldrd_imm_32(va, val1, val2):\nopers = (oper0, oper1, oper2)\nflags = 0\n- return None, None, opers, flags, 0\n+ return COND_AL, None, None, opers, flags, 0\ndef strexn_32(va, val1, val2):\nop3 = (val1 >> 4) & 0xf\n@@ -1128,7 +1132,7 @@ def strexn_32(va, val1, val2):\nolist = (oper0, oper1, oper2)\nflags = 0\n- return 0, mnem, opers, flags, 0\n+ return COND_AL, None, mnem, opers, flags, 0\ndef mla_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -1146,7 +1150,7 @@ def mla_32(va, val1, val2):\nArmRegOper(ra, va=va),\n)\n- return None, mnem, opers, None, 0\n+ return COND_AL, None, mnem, opers, None, 0\ndef smul_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -1161,7 +1165,7 @@ def smul_32(va, val1, val2):\nArmRegOper(rn, va=va),\nArmRegOper(rm, va=va),\n)\n- return None, mnem, opers, None, 0\n+ return COND_AL, None, mnem, opers, None, 0\ndef tb_ldrex_32(va, val1, val2):\nop3 = (val2 >> 4) & 0xf\n@@ -1187,7 +1191,7 @@ def tb_ldrex_32(va, val1, val2):\noper0 = ArmScaledOffsetOper(rn, rm, S_LSL, isH, va, pubwl=0x18)\nopers = (oper0,)\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\nmov_ris_ops = (\n@@ -1223,7 +1227,7 @@ def mov_reg_imm_shift_32(va, val1, val2):\noper2 = ArmImmOper(imm)\nopers = (oper0, oper1, oper2)[:opcnt]\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndp_shift_ops = ((INS_AND, 'and', 3),\n@@ -1313,7 +1317,7 @@ def dp_shift_32(va, val1, val2):\nif s:\nflags = IF_PSR_S\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndef dp_mod_imm_32_deprecated(va, val1, val2):\nop = (val1 >> 5) & 0xf\n@@ -1353,7 +1357,7 @@ def dp_mod_imm_32_deprecated(va, val1, val2):\nelse:\nflags = 0\n- return opcode, mnem, opers, flags, 0\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndef coproc_simd_32(va, val1, val2):\n# p249 of ARMv7-A and ARMv7-R arch ref manual, parts 2 and 3 (not top section)\n@@ -1567,17 +1571,19 @@ def coproc_simd_32(va, val1, val2):\nmnem = 'UNIMPL: adv simd' # FIXME\nreturn adv_simd_32(va, val1, val2)\n- return (opcode, mnem, opers, iflags, simdflags)\n+ return COND_AL, opcode, mnem, opers, iflags, simdflags\nfrom envi.archs.arm.disasm import _do_adv_simd_32, _do_fp_dp\ndef fp_dp(va, val1, val2):\n- return _do_fp_dp(va, val1, val2)\n+ opcode, mnem, opers, iflags, simdflags = _do_fp_dp(va, val1, val2)\n+ return COND_AL, opcode, mnem, opers, iflags, simdflags\ndef adv_simd_32(va, val1, val2):\nval = (val1 << 16) | val2\nu = (val1 >> 12) & 1\n- return _do_adv_simd_32(val, va, u)\n+ opcode, mnem, opers, iflags, simdflags = _do_adv_simd_32(val, va, u)\n+ return COND_AL, opcode, mnem, opers, iflags, simdflags\ndef _adv_simd_32(va, val1, val2):\n# aside from u and the first 8 bits, ARM and Thumb2 decode identically (A7-259)\n@@ -1627,27 +1633,27 @@ def _adv_simd_32(va, val1, val2):\nif nopers != None:\nopers = nopers\n- return opcode, mnem, opers, 0, simdflags\n+ return COND_AL, opcode, mnem, opers, 0, simdflags\nbcc_ops = {\n- 0b0000: (INS_BCC,'beq', envi.IF_COND),\n- 0b0001: (INS_BCC,'bn', envi.IF_COND),\n- 0b0010: (INS_BCC,'bhs', envi.IF_COND),\n- 0b0011: (INS_BCC,'blo', envi.IF_COND),\n- 0b0100: (INS_BCC,'bmi', envi.IF_COND),\n- 0b0101: (INS_BCC,'bpl', envi.IF_COND),\n- 0b0110: (INS_BCC,'bvs', envi.IF_COND),\n- 0b0111: (INS_BCC,'bvc', envi.IF_COND),\n- 0b1000: (INS_BCC,'bhi', envi.IF_COND),\n- 0b1001: (INS_BCC,'bls', envi.IF_COND),\n- 0b1010: (INS_BCC,'bge', envi.IF_COND),\n- 0b1011: (INS_BCC,'blt', envi.IF_COND),\n- 0b1100: (INS_BCC,'bgt', envi.IF_COND),\n- 0b1101: (INS_BCC,'ble', envi.IF_COND),\n- 0b1110: (INS_B,'b', envi.IF_NOFALL),\n+ 0b0000: (INS_BCC,'beq', envi.IF_COND, COND_EQ),\n+ 0b0001: (INS_BCC,'bne', envi.IF_COND, COND_NE),\n+ 0b0010: (INS_BCC,'bcs', envi.IF_COND, COND_CS),\n+ 0b0011: (INS_BCC,'bcc', envi.IF_COND, COND_CC),\n+ 0b0100: (INS_BCC,'bmi', envi.IF_COND, COND_MI),\n+ 0b0101: (INS_BCC,'bpl', envi.IF_COND, COND_PL),\n+ 0b0110: (INS_BCC,'bvs', envi.IF_COND, COND_VS),\n+ 0b0111: (INS_BCC,'bvc', envi.IF_COND, COND_VC),\n+ 0b1000: (INS_BCC,'bhi', envi.IF_COND, COND_HI),\n+ 0b1001: (INS_BCC,'bls', envi.IF_COND, COND_LS),\n+ 0b1010: (INS_BCC,'bge', envi.IF_COND, COND_GE),\n+ 0b1011: (INS_BCC,'blt', envi.IF_COND, COND_LT),\n+ 0b1100: (INS_BCC,'bgt', envi.IF_COND, COND_GT),\n+ 0b1101: (INS_BCC,'ble', envi.IF_COND, COND_LE),\n+ 0b1110: (INS_B,'b', envi.IF_NOFALL, COND_AL),\n}\n@@ -1741,20 +1747,20 @@ thumb_base = [\n('11000', (68,'stm', rm_reglist, IF_IA|IF_W)), # LDMIA Rd!, reg_list\n('11001', (69,'ldm', rm_reglist, IF_IA|IF_W)), # STMIA Rd!, reg_list\n# Conditional Bran6hes\n- ('11010000', (INS_BCC,'beq', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010001', (INS_BCC,'bn', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010010', (INS_BCC,'bhs', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010011', (INS_BCC,'blo', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010100', (INS_BCC,'bmi', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010101', (INS_BCC,'bpl', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010110', (INS_BCC,'bvs', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11010111', (INS_BCC,'bvc', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11011000', (INS_BCC,'bhi', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11011001', (INS_BCC,'bls', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11011010', (INS_BCC,'bge', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11011011', (INS_BCC,'blt', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11011100', (INS_BCC,'bgt', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n- ('11011101', (INS_BCC,'ble', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010000', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010001', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010010', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010011', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010100', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010101', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010110', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11010111', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11011000', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11011001', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11011010', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11011011', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11011100', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n+ ('11011101', (INS_BCC,'b', pc_imm8, envi.IF_BRANCH|envi.IF_COND)),\n('11011110', (INS_B,'b', pc_imm8, envi.IF_BRANCH|envi.IF_NOFALL)),\n('11011111', (INS_BCC,'bfukt', pc_imm8, envi.IF_BRANCH|0)),\n# Software Interrupt\n@@ -2042,7 +2048,7 @@ class ThumbDisasm:\n#print \"FLAGS: \", hex(va),hex(flags)\nif flags & IF_THUMB32:\nval2, = struct.unpack_from(self.hfmt, bytez, offset+2)\n- nopcode, nmnem, olist, nflags, simdflags = opermkr(va+4, val, val2)\n+ cond, nopcode, nmnem, olist, nflags, simdflags = opermkr(va+4, val, val2)\nif nmnem != None: # allow opermkr to set the mnem\nmnem = nmnem\n@@ -2054,7 +2060,7 @@ class ThumbDisasm:\n# print \"OPLEN: \", oplen\nelse:\n- olist, nflags = opermkr(va+4, val)\n+ cond, olist, nflags = opermkr(va+4, val)\nif nflags != None:\nflags = nflags\n#print \"FLAGS: \", repr(olist), repr(flags)\n@@ -2079,7 +2085,7 @@ class ThumbDisasm:\nif mnem == None or type(mnem) == int:\nraise Exception(\"mnem == %r! 0x%xi (thumb)\" % (mnem, opval))\n- op = ThumbOpcode(va, opcode, mnem, 0xe, oplen, olist, flags, simdflags)\n+ op = ThumbOpcode(va, opcode, mnem, cond, oplen, olist, flags, simdflags)\n#print hex(va), oplen, len(op), op.size, hex(op.iflags)\nreturn op\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
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disasm and emu of branches: bugfixes and consistency (reverted from commit 0b3b98487aeed40b38226de6fa45f090b8ade124)
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718,770 |
28.03.2017 10:18:49
| 14,400 |
4461b563874f7533db7b6c3e278d520dd7025495
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continued improvement: arm emulation
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -14,6 +14,21 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nv_i_emulator.WorkspaceEmulator.__init__(self, vw, logwrite=logwrite, logread=logread)\nself.setMemArchitecture(envi.ARCH_ARMV7)\n+ def parseOpcode(self, va, arch=envi.ARCH_DEFAULT):\n+ '''\n+ Caching version.\n+\n+ We can make an opcode *faster* with the workspace because of\n+ getByteDef etc... use it.\n+\n+ Made for ARM, because envi.Emulator doesn't understand the Thumb flag\n+ '''\n+ op = self.opcache.get(va)\n+ if op == None:\n+ op = envi.archs.arm.emu.ArmEmulator.parseOpcode(self, va, arch=arch)\n+ self.opcache[va] = op\n+ return op\n+\ndef stepi(self):\n# NOTE: when we step, we *always* want to be stepping over calls\n# (and possibly import emulate them)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
continued improvement: arm emulation
|
718,770 |
28.03.2017 11:01:25
| 14,400 |
474684a53f6e588395ce1a082c30590970d24267
|
debugging changes. remove me.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3809,7 +3809,7 @@ class ArmOpcode(envi.Opcode):\nif self.iflags & envi.IF_CALL:\nflags |= envi.BR_PROC\nret.append((operval, flags))\n- print \"getBranches: add 0x%x %x\"% (operval, flags)\n+ print \"getBranches: (0x%x) add 0x%x %x\"% (self.va, operval, flags)\nreturn ret\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
debugging changes. remove me.
|
718,770 |
06.04.2017 23:26:19
| 14,400 |
0cc7b6007674129d85d2c90a1a51c58be536be46
|
envi and vivisect main mods.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -78,7 +78,7 @@ class ArchitectureModule:\nself._arch_id = getArchByName(archname)\nself._arch_name = archname\nself._arch_maxinst = maxinst\n- self._arch_badopbytes = ['\\x00\\x00\\x00\\x00\\x00']\n+ self._arch_badopbytes = ['\\x00\\x00\\x00\\x00\\x00', '\\xff\\xff\\xff\\xff\\xff']\nself.setEndian(endian)\ndef getArchId(self):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
envi and vivisect main mods.
|
718,770 |
21.05.2017 14:55:49
| 14,400 |
5476289c3766dde6f2a6f3ac23b077c68a210a02
|
updates to arm emu
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -749,6 +749,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = self.getOperValue(op, 0)\nself.setOperValue(op, 1, val)\n+ i_strh = i_str\n+\ndef i_add(self, op):\nif len(op.opers) == 3:\nsrc1 = self.getOperValue(op, 1)\n@@ -832,6 +834,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setFlag(PSR_T_bit, target & 1)\nreturn target\n+ def i_svc(self, op):\n+ svc = self.getOperValue(op, 0)\n+ print(\"Service 0x%x called at 0x%x\" % (svc, op.va))\n+\ndef i_tst(self, op):\nsrc1 = self.getOperValue(op, 0)\nsrc2 = self.getOperValue(op, 1)\n@@ -1298,6 +1304,16 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_dsb = i_nop\ni_isb = i_nop\n+ def i_vmrs(self, op):\n+ src = self.getRegister(REG_FPSCR)\n+ if op.opers[0].reg != 15:\n+ self.setOperValue(op, 0, src)\n+ else:\n+ apsr = self.getCPSR() & 0x0fffffff\n+ apsr |= (src | 0xf0000000)\n+ self.setOperValue(op, 0, apsr)\n+\n+\nopcode_dist = \\\n[('and', 4083),#\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updates to arm emu
|
718,770 |
26.05.2017 10:41:46
| 14,400 |
b51f8c2ad2e823f8b297cbcb4339a4897cd47fcc
|
default calls plumbed through parsers
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/blob.py",
"new_path": "vivisect/parsers/blob.py",
"diff": "@@ -3,6 +3,13 @@ import vivisect\nimport vivisect.parsers as v_parsers\nfrom vivisect.const import *\n+\n+archcalls = {\n+ 'i386':'cdecl',\n+ 'amd64':'sysvamd64call',\n+ 'arm':'armcall',\n+ }\n+\ndef parseFd(vw, fd, filename=None):\nfd.seek(0)\narch = vw.config.viv.parsers.blob.arch\n@@ -18,6 +25,7 @@ def parseFd(vw, fd, filename=None):\nvw.setMeta('Format','blob')\nvw.setMeta('bigend', bigend)\n+ vw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\nbytez = fd.read()\nvw.addMemoryMap(baseaddr, 7, filename, bytez)\n@@ -40,6 +48,7 @@ def parseFile(vw, filename):\nvw.setMeta('Format','blob')\nvw.setMeta('bigend', bigend)\n+ vw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\nfname = vw.addFile(filename, baseaddr, v_parsers.md5File(filename))\nbytez = file(filename, \"rb\").read()\n@@ -54,4 +63,5 @@ def parseMemory(vw, memobj, baseaddr):\nbytes = memobj.readMemory(va, size)\nfname = vw.addFile(fname, baseaddr, v_parsers.md5Bytes(bytes))\nvw.addMemoryMap(va, perms, fname, bytes)\n+ vw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -82,6 +82,7 @@ arch_names = {\narchcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n+ 'arm':'armcall',\n}\ndef loadElfIntoWorkspace(vw, elf, filename=None):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/ihex.py",
"new_path": "vivisect/parsers/ihex.py",
"diff": "@@ -5,6 +5,12 @@ import vivisect.parsers as v_parsers\nfrom vivisect.const import *\n+archcalls = {\n+ 'i386':'cdecl',\n+ 'amd64':'sysvamd64call',\n+ 'arm':'armcall',\n+}\n+\ndef parseFile(vw, filename):\narch = vw.config.viv.parsers.ihex.arch\n@@ -17,6 +23,8 @@ def parseFile(vw, filename):\nvw.setMeta('Platform','Unknown')\nvw.setMeta('Format','ihex')\n+ vw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\n+\nfname = vw.addFile(filename, 0, v_parsers.md5File(filename))\nihex = v_ihex.IHexFile()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/macho.py",
"new_path": "vivisect/parsers/macho.py",
"diff": "@@ -11,6 +11,12 @@ def parseFile(vw, filename):\ndef parseBytes(vw, filebytes):\nreturn _loadMacho(vw, filebytes)\n+archcalls = {\n+ 'i386':'cdecl',\n+ 'amd64':'sysvamd64call',\n+ 'arm':'armcall',\n+}\n+\ndef _loadMacho(vw, filebytes, filename=None):\n# We fake them to *much* higher than norm so pointer tests do better...\n@@ -61,8 +67,7 @@ def _loadMacho(vw, filebytes, filename=None):\nvw.setMeta(\"Platform\", \"Darwin\")\nvw.setMeta(\"Format\", \"macho\")\n- # FIXME 64bit!\n- vw.setMeta(\"DefaultCall\", \"cdecl\")\n+ vw.setMeta('DefaultCall', archcalls.get(arch,'unknown'))\n# Add the file entry\nhash = \"unknown hash\"\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -53,6 +53,7 @@ arch_names = {\ndefcalls = {\n'i386':'cdecl',\n'amd64':'msx64call',\n+ 'arm':'armcall',\n}\n# map PE relocation types to vivisect types where possible\n@@ -80,9 +81,7 @@ def loadPeIntoWorkspace(vw, pe, filename=None):\nvw.setMeta('Platform', platform)\n- defcall = defcalls.get(arch)\n- if defcall:\n- vw.setMeta(\"DefaultCall\", defcall)\n+ vw.setMeta('DefaultCall', defcalls.get(arch,'unknown'))\n# Set ourselvs up for extended windows binary analysis\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
default calls plumbed through parsers
|
718,770 |
26.05.2017 10:53:07
| 14,400 |
58595381465d24dd2b695b721f1854ea7e38361f
|
make armcall the right answer.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -133,7 +133,7 @@ class ArmEmulator(ArmModule, ArmRegisterContext, envi.Emulator):\nArmRegisterContext.__init__(self)\n- self.addCallingConvention(\"Arm Arch Procedure Call\", aapcs)\n+ self.addCallingConvention(\"armcall\", aapcs)\ndef undefFlags(self):\n\"\"\"\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
make armcall the right answer.
|
718,770 |
26.05.2017 11:28:01
| 14,400 |
e5459264364abe0e2933f34e6805429b955f902f
|
clean up. this is remnant from an earlier commit. this was replaced by implementing in MemoryObject (per other branch/PR)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -295,8 +295,8 @@ class IMemory:\nExample: op = m.parseOpcode(0x7c773803)\n'''\n- off, b = self.getByteDef(va)\n- return self.imem_archs[ (arch & envi.ARCH_MASK) >> 16 ].archParseOpcode(b, off, va)\n+ b = self.readMemory(va, 16)\n+ return self.imem_archs[ arch >> 16 ].archParseOpcode(b, 0, va)\nclass MemoryCache(IMemory):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
clean up. this is remnant from an earlier commit. this was replaced by implementing in MemoryObject (per other branch/PR)
|
718,770 |
26.05.2017 11:31:11
| 14,400 |
55b817c763653591140ac4331feedba56576947a
|
codeflow needs to hand flags/arch information around to correctly handle switches in architecture (like ARM/THUMB, etc...)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -224,9 +224,9 @@ class CodeFlowContext(object):\n# the function that we want to make prodcedural\n# called us so we can't call to make it procedural\n# until its done\n- cf_eps.add(bva)\n+ cf_eps.add((bva, bflags))\nelse:\n- self.addEntryPoint( bva )\n+ self.addEntryPoint( bva, arch=bflags )\nif self._cf_noret.get( bva ):\n# then our next va is noflow!\n@@ -246,7 +246,7 @@ class CodeFlowContext(object):\n# remove our local blocks from global block stack\nself._cf_blocks.pop()\nwhile cf_eps:\n- fva = cf_eps.pop()\n+ fva, arch = cf_eps.pop()\nif not self._mem.isFunction(fva):\nself.addEntryPoint(fva, arch=arch)\n@@ -272,6 +272,7 @@ class CodeFlowContext(object):\n# Finally, notify the callback of a new function\nself._cb_function(va, {'CallsFrom':calls_from})\n+\ndef addDynamicBranchHandler(self, cb):\n'''\nAdd a callback handler for dynamic branches the code-flow resolver\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
codeflow needs to hand flags/arch information around to correctly handle switches in architecture (like ARM/THUMB, etc...)
|
718,770 |
26.05.2017 12:03:30
| 14,400 |
56ade94f4a9002914c9714df78f7276568dce66e
|
allow architectures to modify Xref and Function parameters *before* Xrefs and Functions are created.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -156,6 +156,26 @@ class ArchitectureModule:\nallr = [rname for rname in regctx.getRegisterNames()]\nreturn [ ('all', allr), ]\n+ def archModifyFuncAddr(self, va, arch):\n+ '''\n+ Returns a potentially modified set of (va, arch).\n+ Default: return the same va, arch\n+\n+ This hook allows an architecture to correct VA and Architecture, such\n+ as is necessary for ARM/Thumb.\n+ '''\n+ return va, arch\n+\n+ def archModifyXrefAddr(self, tova, reftype, rflags):\n+ '''\n+ Returns a potentially modified set of (tova, reftype, rflags).\n+ Default: return the same tova, reftype, rflags\n+\n+ This hook allows an architecture to modify an Xref before it's set,\n+ which can be helpful for ARM/Thumb.\n+ '''\n+ return tova, reftype, rflags\n+\ndef archGetBadOps(self, byteslist=None):\n'''\nReturns a list of opcodes which are indicators of wrong disassembly.\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -261,6 +261,9 @@ class CodeFlowContext(object):\ncf.addEntryPoint( 0x77c70308 )\n... callbacks flow along ...\n'''\n+ # Architecture gets to decide on actual final VA and Architecture (ARM/THUMB/etc...)\n+ va, arch = self._mem.arch.archModifyFuncAddr(va, arch)\n+\n# Check if this is already a known function.\nif self._funcs.get(va) != None:\nreturn\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1475,6 +1475,9 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n(see REF_ macros). This will *not* trigger any analysis.\nCallers are expected to do their own xref analysis (ie, makeCode() etc)\n\"\"\"\n+ # Architecture gets to decide on actual final VA (ARM/THUMB/etc...)\n+ va, reftype, rflags = self.arch.archModifyXrefAddr(tova, reftype, rflags)\n+\nref = (fromva, tova, reftype, rflags)\nif ref in self.getXrefsFrom(fromva):\nreturn\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
allow architectures to modify Xref and Function parameters *before* Xrefs and Functions are created.
|
718,770 |
26.05.2017 12:10:38
| 14,400 |
175f7066b485cf42e36041b160d7de550fa87a5a
|
moving to using envi.codeflow version
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -706,6 +706,7 @@ class VivCodeFlowContext(e_codeflow.CodeFlowContext):\nreturn True\n+ \"\"\"\ndef addEntryPoint(self, va, arch=envi.ARCH_DEFAULT):\n'''\nAnalyze the given procedure entry point and flow downward\n@@ -733,4 +734,4 @@ class VivCodeFlowContext(e_codeflow.CodeFlowContext):\n# Finally, notify the callback of a new function\nself._cb_function(va, {'CallsFrom':calls_from})\n-\n+ \"\"\"\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
moving to using envi.codeflow version
|
718,770 |
26.05.2017 12:12:39
| 14,400 |
73044ae98a95b5d82f7f72779884fbeb6ec0c00b
|
why mess with a good thing.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/bits.py",
"new_path": "envi/bits.py",
"diff": "@@ -140,11 +140,16 @@ def is_aux_carry_sub(src, dst):\n# set of format lists which make size, endianness, and signedness fast and easy\nle_fmt_chars = (None,\"B\",\"<H\",None,\"<I\",None,None,None,\"<Q\")\nbe_fmt_chars = (None,\"B\",\">H\",None,\">I\",None,None,None,\">Q\")\n-\nfmt_chars = (le_fmt_chars, be_fmt_chars)\nle_fmt_schars = (None,\"b\",\"<h\",None,\"<i\",None,None,None,\"<q\")\nbe_fmt_schars = (None,\"b\",\">h\",None,\">i\",None,None,None,\">q\")\n+fmt_schars = (le_fmt_schars, be_fmt_schars)\n+\n+master_fmts = (fmt_chars, fmt_schars)\n+\n+fmt_sizes = (None,1,2,4,4,8,8,8,8)\n+\nfmt_schars = (le_fmt_schars, be_fmt_schars)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
why mess with a good thing.
|
718,770 |
26.05.2017 12:18:48
| 14,400 |
e31e73359e507e2ad896465f0e59bcb83d7089f4
|
writeMemValue() should truncate the value to fit within the specified size.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -781,7 +781,8 @@ class Emulator(e_reg.RegisterContext, e_mem.MemoryObject):\ndef writeMemValue(self, addr, value, size):\n#FIXME change this (and all uses of it) to passing in format...\n#FIXME: Remove byte check and possibly half-word check. (possibly all but word?)\n- bytes = e_bits.buildbytes(value, size, self.getEndian())\n+ mask = e_bits.u_maxes[size]\n+ bytes = e_bits.buildbytes(value & mask, size, self.getEndian())\nself.writeMemory(addr, bytes)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
writeMemValue() should truncate the value to fit within the specified size.
|
718,770 |
26.05.2017 12:27:08
| 14,400 |
af722b4e08f7d0ba588e3f62c25d0fe604e9a4a9
|
graphcore gets delEdgeProps()
|
[
{
"change_type": "MODIFY",
"old_path": "visgraph/graphcore.py",
"new_path": "visgraph/graphcore.py",
"diff": "@@ -452,6 +452,17 @@ class Graph:\nself.edgeprops[prop].pop(v,None)\nreturn v\n+ def delEdgesProps(self, props):\n+ '''\n+ Delete all listed properties from all edges in the graph.\n+\n+ Example:\n+ g.delEdgesProps(('foo', 'bar'))\n+ '''\n+ for prop in props:\n+ for edge in self.getEdgesByProp(prop):\n+ self.delEdgeProp(edge, prop)\n+\ndef getRefsFrom(self, node):\n'''\nReturn a list of edges which originate with us.\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
graphcore gets delEdgeProps()
|
718,770 |
26.05.2017 12:39:41
| 14,400 |
291103aed71ed04c4ebd2b864d38ee9a0ad3f111
|
watchdog reuses the same thread instead of creating a new thread every time watchdog() is called.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -691,6 +691,7 @@ class PathGenerator:\n__steplock = threading.Lock()\ndef __init__(self, graph):\n+ self.wdt = None\nself.graph = graph\ndef stop(self):\n@@ -700,31 +701,36 @@ class PathGenerator:\nself.__go__ = False\ndef watchdog(self, time):\n- # FIXME: make this use one thread, not N\n'''\nset a watchdog timer for path generation (if it takes too long to get another path)\n'''\n- self.wdt = threading.Thread(target=self.__wd, args=[time])\n+ self._wd_maxsec = time\n+ self._wd_count = 0\n+ if self.wdt == None:\n+ self.wdt = threading.Thread(target=self.__wd)\nself.wdt.setDaemon = True\nself.wdt.start()\n- def __wd(self, maxsec):\n- # FIXME: make this use one thread, not N\n- maxsec *=10\n- count = 0\n+ def __wd(self):\n+ while True:\n+ try:\nwhile self.__go__:\ntime.sleep(.1)\nself.__steplock.acquire()\ntry:\nif not self.__update:\n- count += 1\n- if count > maxsec:\n+ self._wd_count += 1\n+ if self._wd_count > (self._wd_maxsec * 10):\nself.stop()\nbreak\nfinally:\nself.__steplock.release()\nself.__update = False\n+ except:\n+ sys.excepthook(*sys.exc_info())\n+\n+ time.sleep(1)\ndef getFuncCbRoutedPaths_genback(self, fromva, tova, loopcnt=0, maxpath=None, maxsec=None):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
watchdog reuses the same thread instead of creating a new thread every time watchdog() is called.
|
718,770 |
26.05.2017 14:27:25
| 14,400 |
080f0a1b16f5d39e54263b503d4e3f753888537c
|
make walkSymbolikPaths also allow for loops.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/analysis.py",
"new_path": "vivisect/symboliks/analysis.py",
"diff": "@@ -467,7 +467,7 @@ class SymbolikAnalysisContext:\neffs.extend(emu.applyEffects(seffs[:idx+1]))\nyield emu,effs\n- def walkSymbolikPaths(self, fva, graph=None, maxpath=1000):\n+ def walkSymbolikPaths(self, fva, graph=None, maxpath=1000, loopcnt=0):\n'''\nwalkSymbolikPaths is a function-focused symbolik path generator, using the\nwalkCodePaths generator foundation. Symbolik effects are dragged through\n@@ -542,7 +542,7 @@ class SymbolikAnalysisContext:\npatheffs.extend(neweffs)\nreturn True\n- for pathnode in viv_graph.walkCodePaths(graph, codewalker, maxpath=maxpath):\n+ for pathnode in viv_graph.walkCodePaths(graph, codewalker, loopcnt=loopcnt, maxpath=maxpath):\nemu = vg_pathcore.getNodeProp(pathnode, 'pathemu')\npatheffs = vg_pathcore.getNodeProp(pathnode, 'patheffs')\nyield emu, patheffs\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
make walkSymbolikPaths also allow for loops.
|
718,770 |
26.05.2017 14:28:52
| 14,400 |
ef0cbc696b0b07887ec9dbd46c7cdeeb8fc0bfb4
|
atlas, put that api down, you're going to break it. good boy.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -330,7 +330,7 @@ def getCodePaths(fgraph, loopcnt=0, maxpath=None):\ntonode = fgraph.getNode(toid)\ntodo.append((tonode,npath))\n-def walkCodePaths(fgraph, callback, maxpath=None, loopcnt=0):\n+def walkCodePaths(fgraph, callback, loopcnt=0, maxpath=None):\n'''\nwalkCodePaths is a path generator which uses a callback function to determine the\nviability of each particular path. This approach allows the calling function\n@@ -731,7 +731,7 @@ class PathGenerator:\n'''\nset a watchdog timer for path generation (if it takes too long to get another path)\n'''\n- self._wd_maxsec = time * 10\n+ self._wd_maxsec = time\nself._wd_count = 0\nif self.wdt == None:\nself.wdt = threading.Thread(target=self.__wd)\n@@ -747,7 +747,7 @@ class PathGenerator:\ntry:\nif not self.__update:\nself._wd_count += 1\n- if self._wd_count > self._wd_maxsec:\n+ if self._wd_count > (self._wd_maxsec * 10):\nself.stop()\nbreak\nfinally:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
atlas, put that api down, you're going to break it. good boy.
|
718,770 |
26.05.2017 15:01:59
| 14,400 |
2239ca3b128f189ac2a395e428ac6a5315648489
|
enhancements for routed graph pathing
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -341,6 +341,7 @@ def walkCodePaths(fgraph, callback, loopcnt=0, maxpath=None):\nFor root nodes, the current path and edge will be None types.\n'''\npathcnt = 0\n+ routed = fgraph.getMeta('Routed', False)\nfor root in fgraph.getHierRootNodes():\nproot = vg_pathcore.newPathNode(nid=root[0], eid=None)\n@@ -370,6 +371,9 @@ def walkCodePaths(fgraph, callback, loopcnt=0, maxpath=None):\nreturn\nfor eid, fromid, toid, einfo in refsfrom:\n+ # skip edges which are not marked \"follow\"\n+ if routed and not einfo.get('follow', False):\n+ continue\n# Skip loops if they are \"deeper\" than we are allowed\nif vg_pathcore.getPathLoopCount(cpath, 'nid', toid) > loopcnt:\ncontinue\n@@ -589,19 +593,36 @@ def findRemergeDown(graph, va):\nbreak\n# path routing through a graph. reduces aimless wandering when we know where we want to be\n-def preRouteGraph(graph, fromva, tova):\n+def preRouteGraph(graph, fromva, tova, clearFirst=True):\n'''\nPackage it all together\n'''\n- graph.delNodesProps(('up','down'))\n+ if clearFirst:\n+ clearRouting(graph)\n+\npreRouteGraphUp(graph, tova)\npreRouteGraphDown(graph, fromva)\n+ preRouteGraphEdges(graph)\n+\n+def preRouteGraphEdges(graph):\n+ '''\n+ Mark edges as 'follow' if from-node is marked 'up' and to-node id marked 'down'\n+ Note: unlike the other preRoute functions, this is not flexible on naming.\n+ '''\n+ for edge in graph.getEdges():\n+ eid, frnid, tonid, einfo = edge\n+ if not graph.getNodeProps(frnid).get('up'):\n+ continue\n+ if not graph.getNodeProps(tonid).get('down'):\n+ continue\n+\n+ graph.setEdgeProp(edge, 'follow', True)\ndef preRouteGraphUp(graph, tova, loop=True, mark='down'):\n'''\npaint a route from our destination, 'up' the graph\n'''\n-\n+ graph.setMeta('Routed', True)\ntonid = getGraphNodeByVa(graph, tova)\nif tonid == None:\nraise Exception(\"tova not in graph 0x%x\" % tova)\n@@ -624,6 +645,7 @@ def preRouteGraphDown(graph, fromva, loop=False, mark='up'):\n'''\npaint a route from our starting point, 'down' the graph\n'''\n+ graph.setMeta('Routed', True)\nfromnode = getGraphNodeByVa(graph, fromva)\nif fromnode == None:\nraise Exception(\"fromva not in graph 0x%x\" % fromva)\n@@ -668,6 +690,11 @@ def clearMarkDown(graph, fromva, loop=False, mark='up'):\ntodo.append(graph.getNode(to))\n+def clearRouting(graph, nmarks=('up','down'), emarks=('follow',)):\n+ graph.delNodesProps(nmarks)\n+ graph.delEdgesProps(emarks)\n+ graph.setMeta('Routed', False)\n+\ndef reduceGraph(graph, props=('up','down')):\n'''\ntrims all nodes that don't have all the props in the props list\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
enhancements for routed graph pathing
|
718,770 |
02.06.2017 10:56:47
| 14,400 |
b6760894aa15bf91f319b0ebc84be014cf6b0fe2
|
updated locking mechanisms and added a killswitch to PathGenerator
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -687,12 +687,14 @@ class PathForceQuitException(Exception):\neventually, routing will include the ability to 'source-route', picking N specific points a path must go through\n'''\nclass PathGenerator:\n- __go__ = None\n- __steplock = threading.Lock()\ndef __init__(self, graph):\nself.wdt = None\nself.graph = graph\n+ self._wd_maxdsec = 0\n+\n+ self.__go__ = False\n+ self.__steplock = threading.Lock()\ndef stop(self):\n'''\n@@ -700,37 +702,46 @@ class PathGenerator:\n'''\nself.__go__ = False\n- def watchdog(self, time):\n+ def watchdog(self, maxsec=20):\n'''\nset a watchdog timer for path generation (if it takes too long to get another path)\n+ maxsec is in seconds, and accepts floats, but only has granularity up to the 1/10th second.\n'''\n- self._wd_maxsec = time\n+ self._wd_maxdsec = maxsec * 10\nself._wd_count = 0\n+ self.__active__ = True\n+\nif self.wdt == None:\nself.wdt = threading.Thread(target=self.__wd)\n- self.wdt.setDaemon = True\n+ self.wdt.setDaemon(True)\nself.wdt.start()\n+ def kill(self):\n+ '''\n+ PathGenerator spins up a thread, and uses it until kill() is called\n+ kill() tells the thread that we're done\n+ '''\n+ self.__go__ = False\n+ self.__active__ = False\n+ self.wdt.join()\n+\ndef __wd(self):\n- while True:\n+ while self.__active__:\ntry:\nwhile self.__go__:\ntime.sleep(.1)\n- self.__steplock.acquire()\n- try:\n+ with self.__steplock:\nif not self.__update:\nself._wd_count += 1\n- if self._wd_count > (self._wd_maxsec * 10):\n+ if self._wd_count > (self._wd_maxdsec * 10):\nself.stop()\nbreak\n- finally:\n- self.__steplock.release()\nself.__update = False\nexcept:\nsys.excepthook(*sys.exc_info())\n- time.sleep(1)\n+ time.sleep(.4)\ndef getFuncCbRoutedPaths_genback(self, fromva, tova, loopcnt=0, maxpath=None, maxsec=None):\n@@ -797,6 +808,8 @@ class PathGenerator:\nnpath = vg_pathcore.newPathNode(parent=cpath, nid=fromid, eid=None)\ntodo.append((fromid,npath))\n+ self.__go__ = False\n+\ndef getFuncCbRoutedPaths(self, fromva, tova, loopcnt=0, maxpath=None, maxsec=None):\n'''\nYields all the paths through the hierarchical graph starting at the\n@@ -864,3 +877,5 @@ class PathGenerator:\ntodo.append((toid,npath))\nvg_pathcore.trimPath(cpath)\n+\n+ self.__go__ = False\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updated locking mechanisms and added a killswitch to PathGenerator
|
718,770 |
02.06.2017 11:22:39
| 14,400 |
b54fdc866ab1b7502f6f46cdff298dc927057f01
|
enhance api to allow dictionary instead of arch to be handed along.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -156,15 +156,15 @@ class ArchitectureModule:\nallr = [rname for rname in regctx.getRegisterNames()]\nreturn [ ('all', allr), ]\n- def archModifyFuncAddr(self, va, arch):\n+ def archModifyFuncAddr(self, va, info):\n'''\n- Returns a potentially modified set of (va, arch).\n- Default: return the same va, arch\n+ Can modify the VA and context based on architecture-specific info.\n+ Default: return the same va, info\nThis hook allows an architecture to correct VA and Architecture, such\nas is necessary for ARM/Thumb.\n'''\n- return va, arch\n+ return va, info\ndef archModifyXrefAddr(self, tova, reftype, rflags):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -52,6 +52,18 @@ class ArmModule(envi.ArchitectureModule):\nself._arch_dis.setEndian(endian)\nself._arch_thumb_dis.setEndian(endian)\n+ def archModifyFuncAddr(self, va, info):\n+ if va & 1:\n+ info['arch'] = envi.ARCH_THUMB\n+ return va & -2, info\n+ return va, info\n+\n+ def archModifyXrefAddr(self, tova, reftype, rflags):\n+ if tova & 1:\n+ return tova & -2, reftype, rflags\n+ return tova, reftype, rflags\n+\n+\nfrom envi.archs.arm.emu import *\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -262,7 +262,8 @@ class CodeFlowContext(object):\n... callbacks flow along ...\n'''\n# Architecture gets to decide on actual final VA and Architecture (ARM/THUMB/etc...)\n- va, arch = self._mem.arch.archModifyFuncAddr(va, arch)\n+ info = { 'arch' : arch }\n+ va, arch = self._mem.arch.archModifyFuncAddr(va, info)\n# Check if this is already a known function.\nif self._funcs.get(va) != None:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
enhance api to allow dictionary instead of arch to be handed along.
|
718,770 |
02.06.2017 11:41:08
| 14,400 |
f1e60f766aa7d3468a3b21e6bfd8fbd11391c437
|
and then we test it.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -54,7 +54,7 @@ class ArmModule(envi.ArchitectureModule):\ndef archModifyFuncAddr(self, va, info):\nif va & 1:\n- info['arch'] = envi.ARCH_THUMB\n+ info['arch'] = envi.ARCH_THUMB2\nreturn va & -2, info\nreturn va, info\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -263,7 +263,8 @@ class CodeFlowContext(object):\n'''\n# Architecture gets to decide on actual final VA and Architecture (ARM/THUMB/etc...)\ninfo = { 'arch' : arch }\n- va, arch = self._mem.arch.archModifyFuncAddr(va, info)\n+ va, info = self._mem.arch.archModifyFuncAddr(va, info)\n+ arch = info.get('arch', envi.ARCH_DEFAULT)\n# Check if this is already a known function.\nif self._funcs.get(va) != None:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
and then we test it.
|
718,770 |
02.06.2017 14:52:25
| 14,400 |
7cbd24249b22385e280da7e077cfdcb0453dd045
|
remove threading/locking from PathGenerator. simply have the timeout be counted within the path generators.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -689,60 +689,15 @@ eventually, routing will include the ability to 'source-route', picking N specif\nclass PathGenerator:\ndef __init__(self, graph):\n- self.wdt = None\nself.graph = graph\nself._wd_maxdsec = 0\n-\nself.__go__ = False\n- self.__steplock = threading.Lock()\ndef stop(self):\n'''\n- stops path generation. used by watchdog, but could be used by path processing code\n- '''\n- self.__go__ = False\n-\n- def watchdog(self, maxsec=20):\n- '''\n- set a watchdog timer for path generation (if it takes too long to get another path)\n- maxsec is in seconds, and accepts floats, but only has granularity up to the 1/10th second.\n- '''\n- self._wd_maxdsec = maxsec * 10\n- self._wd_count = 0\n- self.__active__ = True\n-\n- if self.wdt == None:\n- self.wdt = threading.Thread(target=self.__wd)\n- self.wdt.setDaemon(True)\n- self.wdt.start()\n-\n- def kill(self):\n- '''\n- PathGenerator spins up a thread, and uses it until kill() is called\n- kill() tells the thread that we're done\n+ stops path generation.\n'''\nself.__go__ = False\n- self.__active__ = False\n- self.wdt.join()\n-\n- def __wd(self):\n- while self.__active__:\n- try:\n- while self.__go__:\n- time.sleep(.1)\n- with self.__steplock:\n- if not self.__update:\n- self._wd_count += 1\n- if self._wd_count > (self._wd_maxdsec * 10):\n- self.stop()\n- break\n-\n- self.__update = False\n- except:\n- sys.excepthook(*sys.exc_info())\n-\n- time.sleep(.4)\n-\ndef getFuncCbRoutedPaths_genback(self, fromva, tova, loopcnt=0, maxpath=None, maxsec=None):\n'''\n@@ -768,10 +723,11 @@ class PathGenerator:\ntodo = [(tocbva,pnode), ]\n- if maxsec:\n- self.watchdog(maxsec)\n-\n+ starttime = time.time()\nwhile todo:\n+ if maxsec and (time.time() - starttime > maxsec):\n+ raise PathForceQuitException()\n+\nif not self.__go__:\nraise PathForceQuitException()\n@@ -834,10 +790,11 @@ class PathGenerator:\ntodo = [(frcbva, pnode), ]\n- if maxsec:\n- self.watchdog(maxsec)\n-\n+ starttime = time.time()\nwhile todo:\n+ if maxsec and (time.time() - starttime > maxsec):\n+ raise PathForceQuitException()\n+\nif not self.__go__:\nraise PathForceQuitException()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
remove threading/locking from PathGenerator. simply have the timeout be counted within the path generators.
|
718,770 |
08.06.2017 13:30:57
| 14,400 |
699ba72e4cf269ced1f55c938f196ef3695aa6e4
|
create copy of info dict if changes are made. otherwise, pass through.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -54,8 +54,9 @@ class ArmModule(envi.ArchitectureModule):\ndef archModifyFuncAddr(self, va, info):\nif va & 1:\n- info['arch'] = envi.ARCH_THUMB2\n- return va & -2, info\n+ retval = dict(info)\n+ retval['arch'] = envi.ARCH_THUMB2\n+ return va & -2, retval\nreturn va, info\ndef archModifyXrefAddr(self, tova, reftype, rflags):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
create copy of info dict if changes are made. otherwise, pass through.
|
718,770 |
08.06.2017 13:43:50
| 14,400 |
2a13b7452f65578675c91bf5a2f3a26ab308d9c7
|
renaming and reworking to reduce tight-loop math.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -698,7 +698,7 @@ class PathGenerator:\n'''\nself.__go__ = False\n- def getFuncCbRoutedPaths_genback(self, fromva, tova, loopcnt=0, maxpath=None, maxsec=None):\n+ def getFuncCbRoutedPaths_genback(self, fromva, tova, loopcnt=0, maxpath=None, timeout=None):\n'''\nYields all the paths through the hierarchical graph starting at the\n\"root nodes\" and ending at tocbva. Specify a loopcnt to allow loop\n@@ -722,9 +722,12 @@ class PathGenerator:\ntodo = [(tocbva,pnode), ]\n- starttime = time.time()\n+ maxtime = None\n+ if timeout:\n+ maxtime = time.time() + timeout\n+\nwhile todo:\n- if maxsec and (time.time() - starttime > maxsec):\n+ if maxtime and time.time() > maxtime:\nraise PathForceQuitException()\nif not self.__go__:\n@@ -765,7 +768,7 @@ class PathGenerator:\nself.__go__ = False\n- def getFuncCbRoutedPaths(self, fromva, tova, loopcnt=0, maxpath=None, maxsec=None):\n+ def getFuncCbRoutedPaths(self, fromva, tova, loopcnt=0, maxpath=None, timeout=None):\n'''\nYields all the paths through the hierarchical graph starting at the\n\"root nodes\" and ending at tocbva. Specify a loopcnt to allow loop\n@@ -789,9 +792,12 @@ class PathGenerator:\ntodo = [(frcbva, pnode), ]\n- starttime = time.time()\n+ maxtime = None\n+ if timeout:\n+ maxtime = time.time() + timeout\n+\nwhile todo:\n- if maxsec and (time.time() - starttime > maxsec):\n+ if maxtime and time.time() > maxtime:\nraise PathForceQuitException()\nif not self.__go__:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
renaming and reworking to reduce tight-loop math.
|
718,770 |
08.06.2017 14:04:32
| 14,400 |
26613fac2dbacaf2ae2e021f190a750befeb5ace
|
archModifyFuncAddr() now returns (va, {}) by default
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -164,7 +164,7 @@ class ArchitectureModule:\nThis hook allows an architecture to correct VA and Architecture, such\nas is necessary for ARM/Thumb.\n'''\n- return va, info\n+ return va, {}\ndef archModifyXrefAddr(self, tova, reftype, rflags):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
archModifyFuncAddr() now returns (va, {}) by default
|
718,770 |
08.06.2017 14:17:40
| 14,400 |
ec20b6a52371022aab75d23f0f1726dacb678976
|
archModifyFuncAddr() now returns (va, {}) by default (ARM as well)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -54,10 +54,8 @@ class ArmModule(envi.ArchitectureModule):\ndef archModifyFuncAddr(self, va, info):\nif va & 1:\n- retval = dict(info)\n- retval['arch'] = envi.ARCH_THUMB2\n- return va & -2, retval\n- return va, info\n+ return va & -2, {'arch' : envi.ARCH_THUMB2}\n+ return va, {}\ndef archModifyXrefAddr(self, tova, reftype, rflags):\nif tova & 1:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
archModifyFuncAddr() now returns (va, {}) by default (ARM as well)
|
718,770 |
08.06.2017 15:04:00
| 14,400 |
1ec886e66835bf2d9e2950f4b9a42902441637ba
|
a little bit of docs.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -687,6 +687,15 @@ class PathForceQuitException(Exception):\neventually, routing will include the ability to 'source-route', picking N specific points a path must go through\n'''\nclass PathGenerator:\n+ '''\n+ PathGenerator provides routed paths using yield generators, with some external\n+ control. Because these generators are typically layered with other API's\n+ (ie. Symboliks subsystem calls) on top, PathGenerator provides a timeout and\n+ some external control.\n+\n+ PathGenerator should be used one per thread, not shared between threads. The stop()\n+ method is good for use by a single management thread.\n+ '''\ndef __init__(self, graph):\nself.graph = graph\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
a little bit of docs.
|
718,770 |
08.06.2017 23:00:51
| 14,400 |
2a198b3bcb0294924de1f1c38ba8e1df24b42e29
|
unit test minor updates
|
[
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -1968,6 +1968,7 @@ def genTestsObjdump(abytez, tbytez):\nimport subprocess\nfrom subprocess import PIPE\n+ if len(abytes:\nfile('/tmp/armbytez', 'wb').write(''.join(abytez))\nproc = subprocess.Popen(['/usr/bin/arm-linux-gnueabi-objdump', '-D','/tmp/armbytez', '-b', 'binary', '-m', 'arm'], stdin=PIPE, stdout=PIPE, stderr=PIPE)\ndata = proc.stdout.readlines()\n@@ -1983,6 +1984,7 @@ def genTestsObjdump(abytez, tbytez):\nyield (\" (REV_ALL_ARM, '%s', 0x%s, '%s %s', 0, ()),\" % (bytez, ova, op, opers))\n+ if len(tbytes):\nfile('/tmp/thmbytez', 'wb').write(''.join(tbytez))\nproc = subprocess.Popen(['/usr/bin/arm-linux-gnueabi-objdump', '-D','/tmp/thmbytez', '-b', 'binary', '-m', 'arm', '-M', 'force-thumb'], stdin=PIPE, stdout=PIPE, stderr=PIPE)\ndata = proc.stdout.readlines()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
unit test minor updates
|
718,770 |
08.06.2017 23:12:14
| 14,400 |
fdf5794700ded0242ac9f75f5219a7219626cb31
|
FPSCR register
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/regs.py",
"new_path": "envi/archs/arm/regs.py",
"diff": "@@ -94,6 +94,8 @@ for simdreg in range(VFP_QWORD_REG_COUNT):\narm_metas.append((\"d%d\" % (d), simd_idx, 0, 64))\narm_metas.append((\"d%d\" % (d+1), simd_idx, 32, 64))\n+REG_FPSCR = len(reg_data)\n+reg_data.append(('fpscr', 32))\nl = locals()\ne_reg.addLocalEnums(l, arm_regs)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
FPSCR register
|
718,770 |
20.06.2017 14:20:03
| 14,400 |
aebb498b767b68fdee2afd0bcad937ff33f2609a
|
update to permit ELF loading of AARCH64 binaries.
|
[
{
"change_type": "MODIFY",
"old_path": "Elf/elf_lookup.py",
"new_path": "Elf/elf_lookup.py",
"diff": "@@ -75,6 +75,7 @@ EM_ARC_A5 = 93\nEM_XTENSA = 94\nEM_NUM = 95\nEM_MSP430 = 105\n+EM_ARM_AARCH64 = 183\nEM_ALPHA = 0x9026\n# There are plenty more of these to\n@@ -88,7 +89,8 @@ e_machine_32 = (\ne_machine_64 = (\nEM_PPC64,\nEM_SPARCV9,\n- EM_X86_64\n+ EM_X86_64,\n+ EM_ARM_AARCH64,\n)\nELFCLASSNONE = 0\n@@ -175,6 +177,7 @@ EM_OPENRISC:\"OpenRISC 32-bit embedded processor\",\nEM_ARC_A5:\"ARC Cores Tangent-A5\",\nEM_XTENSA:\"Tensilica Xtensa Architecture\",\nEM_NUM:\"\",\n+EM_ARM_AARCH64:\"ARM aarch64\",\nEM_ALPHA:\"\",\n}\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -77,6 +77,7 @@ arch_names = {\nElf.EM_386:'i386',\nElf.EM_X86_64:'amd64',\nElf.EM_MSP430:'msp430',\n+ Elf.EM_ARM_AARCH64:'aarch64',\n}\narchcalls = {\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
update to permit ELF loading of AARCH64 binaries.
|
718,770 |
22.08.2017 13:36:45
| 14,400 |
8624c9dc69041261f78eef940a11f6e9e1fa36ba
|
bugfix: mov pc, lr wasn't being flagged as a RETURN
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -220,6 +220,8 @@ def p_dp_imm_shift(opval, va):\nif (shtype==3) & (shval ==0): # is it an rrx?\nshtype = 4\nmnem, opcode = dp_mnem[ocode]\n+\n+ iflags = 0\nif ocode in dp_noRn:# FIXME: FUGLY (and slow...)\n#is it a mov? Only if shval is a 0, type is lsl, and ocode = 13\nif (ocode == 13) and ((shval != 0) or (shtype != 0)):\n@@ -235,12 +237,15 @@ def p_dp_imm_shift(opval, va):\nArmRegOper(Rd, va=va),\nArmRegOper(Rm, va=va),\n)\n-\nelse:\nolist = (\nArmRegOper(Rd, va=va),\nArmRegShiftImmOper(Rm, shtype, shval, va),\n)\n+ # case: mov pc, lr\n+ if Rd == REG_PC and Rm == REG_LR:\n+ iflags |= envi.IF_RET\n+\nelif ocode in dp_noRd:\nolist = (\nArmRegOper(Rn, va=va),\n@@ -256,11 +261,10 @@ def p_dp_imm_shift(opval, va):\nif sflag > 0:\n# IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\nif ocode in dp_silS:\n- iflags = IF_PSR_S | IF_PSR_S_SIL\n+ iflags |= IF_PSR_S | IF_PSR_S_SIL\nelse:\n- iflags = IF_PSR_S\n- else:\n- iflags = 0\n+ iflags |= IF_PSR_S\n+\nreturn (opcode, mnem, olist, iflags, 0)\n# specialized mnemonics for p_misc\n@@ -4870,6 +4874,7 @@ class ArmPSRFlagsOper(ArmOperand):\ndef repr(self, op):\nreturn aif_flags[self.flags]\n+ #FIXME: render?\nclass ArmCoprocOpcodeOper(ArmOperand):\ndef __init__(self, val):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: mov pc, lr wasn't being flagged as a RETURN
|
718,770 |
23.08.2017 18:26:14
| 14,400 |
2f90c1eb8604158860e1d7ad388c9552f9805821
|
ARM emu bug fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -460,7 +460,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nres = src1 & src2\n- if op.iflags & IF_S:\n+ if op.iflags & IF_PSR_S:\nself.setFlag(PSR_N_bit, 0)\nself.setFlag(PSR_Z_bit, not res)\nself.setFlag(PSR_C_bit, 0)\n@@ -492,7 +492,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = val1 | val2\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_PSR_S # FIXME: IF_PSR_S???\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -712,12 +712,26 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, val)\nif op.opers[0].reg == REG_PC:\nself.setThumbMode(val & 1)\n- return val\n+ return val & -2\ndef i_mov(self, op):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n+ if op.iflags & IF_PSR_S:\n+ dsize = op.opers[0].tsize\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\n+ self.setFlag(PSR_Z_bit, not val)\n+\n+ if op.iflags & envi.IF_RET:\n+ self.setThumbMode(val & 1)\n+ return val & -2\n+\n+ dest = op.opers[0]\n+ if isinstance(dest, ArmRegOper) and dest.reg == REG_PC:\n+ self.setThumbMode(val & 1)\n+ return val & -2\n+\ndef i_movt(self, op):\nbase = self.getOperValue(op, 0) & 0xffff\nval = self.getOperValue(op, 1) << 16\n@@ -780,7 +794,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, ures)\ncurmode = self.getProcMode()\n- if op.iflags & IF_S:\n+ if op.iflags & IF_PSR_S:\nif op.opers[0].reg == 15 and (curmode != PM_sys and curmode != PM_usr):\nself.setCPSR(self.getSPSR(curmode))\nelse:\n@@ -887,7 +901,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, ures)\ncurmode = self.getProcMode()\n- if op.iflags & IF_S:\n+ if op.iflags & IF_PSR_S:\nif op.opers[0].reg == 15:\nif (curmode != PM_sys and curmode != PM_usr):\nself.setCPSR(self.getSPSR(curmode))\n@@ -970,7 +984,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, ures)\ncurmode = self.getProcMode()\n- if op.iflags & IF_S:\n+ if op.iflags & IF_PSR_S:\nif op.opers[0].reg == 15:\nif (curmode != PM_sys and curmode != PM_usr):\nself.setCPSR(self.getSPSR(curmode))\n@@ -1027,7 +1041,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval &= ~const\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S # FIXME: IF_PSR_S???\n+ Sflag = op.iflags & IF_PSR_S # FIXME: IF_PSR_S???\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1047,7 +1061,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = Rn * Rm\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1067,7 +1081,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncarry = (val >> 32) & 1\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1087,7 +1101,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncarry = (src >> (imm5-1)) & 1\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1113,7 +1127,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncarry = (src >> (imm5-1)) & 1\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1133,7 +1147,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncarry = (val >> 31) & 1\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1155,7 +1169,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncarry = src & 1\nself.setOperValue(op, 0, val)\n- Sflag = op.iflags & IF_S\n+ Sflag = op.iflags & IF_PSR_S\nif Sflag:\nself.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\nself.setFlag(PSR_Z_bit, not val)\n@@ -1313,6 +1327,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\napsr |= (src | 0xf0000000)\nself.setOperValue(op, 0, apsr)\n+#TODO: IT EQ\nopcode_dist = \\\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
ARM emu bug fixes
|
718,770 |
23.08.2017 18:35:13
| 14,400 |
5854429130e3e7899eacbfecf700c549df67579d
|
performance improvement for DP with S flags.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -187,7 +187,12 @@ dp_shift_mnem = (\n# FIXME: THIS IS FUGLY but sadly it works\ndp_noRn = (13,15)\ndp_noRd = (8,9,10,11)\n-dp_silS = (8,9,10,11)\n+dp_silS = dp_noRd\n+\n+# IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\n+DP_PSR_S = [IF_PSR_S for x in range(17)]\n+for x in dp_silS:\n+ DP_PSR_S[x] |= IF_PSR_S_SIL\n# FIXME: dp_MOV was supposed to be a tuple of opcodes that could be converted to MOV's if offset from PC.\n# somehow this list has vanished into the ether. add seems like the right one here.\n@@ -259,11 +264,7 @@ def p_dp_imm_shift(opval, va):\n)\nif sflag > 0:\n- # IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\n- if ocode in dp_silS:\n- iflags |= IF_PSR_S | IF_PSR_S_SIL\n- else:\n- iflags |= IF_PSR_S\n+ iflags |= DP_PSR_S[ocode]\nreturn (opcode, mnem, olist, iflags, 0)\n@@ -667,10 +668,8 @@ def p_dp_reg_shift(opval, va):\nif sflag > 0:\n# IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\n- if ocode in dp_silS:\n- iflags = IF_PSR_S | IF_PSR_S_SIL\n- else:\n- iflags = IF_PSR_S\n+ iflags = DP_PSR_S[ocode]\n+\nelse:\niflags = 0\nreturn (opcode, mnem, olist, iflags, 0)\n@@ -747,11 +746,7 @@ def p_dp_imm(opval, va):\n)\nif sflag > 0:\n- # IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\n- if ocode in dp_silS:\n- iflags = IF_PSR_S | IF_PSR_S_SIL\n- else:\n- iflags = IF_PSR_S\n+ iflags |= DP_PSR_S[ocode]\nelse:\niflags = 0\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
performance improvement for DP with S flags.
|
718,770 |
23.08.2017 18:38:22
| 14,400 |
cd30142f2cf993c9c0cfb2f42cb8367ccb19a7ae
|
update for reg-thunks: don't emulate past function-end!
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "import sys\n+import envi\nimport vivisect\nimport vivisect.impemu.monitor as viv_monitor\n@@ -84,6 +85,10 @@ def analyzeFunction(vw, fva, prepend=False):\nfor x in range(MAX_INIT_OPCODES):\nop = vw.parseOpcode(tva)\nemu.executeOpcode(op)\n+\n+ if op.iflags & envi.IF_NOFALL:\n+ break\n+\nif not len(op.opers):\ncontinue\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
update for reg-thunks: don't emulate past function-end!
|
718,770 |
23.08.2017 19:05:16
| 14,400 |
b7aec2cc45b8f4d1368b177138633e4086ad5a42
|
arm function emulation analysis module.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -15,20 +15,38 @@ from vivisect.const import *\nclass AnalysisMonitor(viv_monitor.AnalysisMonitor):\n- def __init__(self, vw, fva):\n+ def __init__(self, vw, fva, verbose=True):\nviv_monitor.AnalysisMonitor.__init__(self, vw, fva)\n+ self.verbose = verbose\nself.retbytes = None\n- self.badop = vw.arch.archParseOpcode(\"\\x00\\x00\\x00\\x00\\x00\")\n+ self.badops = vw.arch.archGetBadOps()\nself.last_lr_pc = 0\n+ self.strictops = False\n+ self.returns = False\n+ self.infloops = []\ndef prehook(self, emu, op, starteip):\n- if op == self.badop:\n+ try:\n+ tmode = emu.getFlag(PSR_T_bit)\n+ self.last_tmode = tmode\n+ if self.verbose: print \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op)\n+ #if op == self.badop:\n+ if op in self.badops:\nraise Exception(\"Hit known BADOP at 0x%.8x %s\" % (starteip, repr(op) ))\nviv_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n+ loctup = emu.vw.getLocation(starteip)\n+ if loctup == None:\n+ # do we want to hand this off to makeCode?\n+ emu.vw.addLocation(starteip, len(op), vivisect.LOC_OP, op.iflags)\n+\n+ elif loctup[0] != starteip:\n+ if self.verbose: print \"ARG! emulation found opcode in a location at the wrong address (0x%x): 0x%x: %s\" % (loctup[0], op.va, op)\n+\nif op.iflags & envi.IF_RET:\n+ self.returns = True\nif len(op.opers):\nif hasattr(op.opers, 'imm'):\nself.retbytes = op.opers[0].imm\n@@ -48,9 +66,33 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nif op.opcode == INS_BX:\nif starteip - self.last_lr_pc <= 4:\n# this is a call. the compiler updated lr\n- print \"CALL by mov lr, pc; bx <foo> at 0x%x\" % starteip\n+ if self.verbose: print \"CALL by mov lr, pc; bx <foo> at 0x%x\" % starteip\n+ ### DO SOMETHING?? identify new function like emucode.\n+\n+ if op.iflags & envi.IF_BRANCH:\n+ try:\n+ tgt = op.getOperValue(0, emu)\n+\n+ if self.verbose: print \"BRANCH: \", hex(tgt), hex(op.va), hex(op.va)\n+\n+ if tgt == op.va:\n+ if self.verbose: print \"+++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\"\n+ if op.va not in self.infloops:\n+ self.infloops.append(op.va)\n+\n+ except Exception, e:\n+ # FIXME: make raise Exception?\n+ print \"0x%x: ERROR: %s\" % (op.va, e)\n+\n+ except Exception, e:\n+ # FIXME: make raise Exception?\n+ print \"0x%x: ERROR: %s\" % (op.va, e)\n+ def posthook(self, emu, op, starteip):\n+ if op.opcode == INS_BLX:\n+ emu.setFlag(PSR_T_bit, self.tmode)\n+\ndef analyzeTB(emu, op, starteip, amon):\nprint \"TB at 0x%x\" % starteip\n@@ -97,11 +139,24 @@ def buildFunctionApi(vw, fva, emu, emumon):\nreturn api\ndef analyzeFunction(vw, fva):\n+ #raw_input( \"= 0x%x viv.analysis.arm.emulation... =\" % (fva))\n+ #print( \"= 0x%x viv.analysis.arm.emulation... =\" % (fva))\nemu = vw.getEmulator()\nemumon = AnalysisMonitor(vw, fva)\nemu.setEmulationMonitor(emumon)\n+\n+ loc = vw.getLocation(fva)\n+\n+ if loc != None:\n+ lva, lsz, lt, lti = loc\n+ if lt == LOC_OP:\n+ if (lti & envi.ARCH_MASK) != envi.ARCH_ARMV7:\n+ emu.setFlag(PSR_T_bit, 1)\n+ else:\n+ print \"NO LOCATION at FVA: 0x%x\" % fva\n+\nemu.runFunction(fva, maxhit=1)\n# Do we already have API info in meta?\n@@ -128,4 +183,7 @@ def analyzeFunction(vw, fva):\nemumon.addAnalysisResults(vw, emu)\n+ # handle infinite loops (actually, while 1;)\n+\n+\n# TODO: incorporate some of emucode's analysis but for function analysis... if it makes sense.\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm function emulation analysis module.
|
718,770 |
23.08.2017 19:07:34
| 14,400 |
e2c504eb73613011c6e76718bd05240be18867ae
|
arm emu cleanup
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -556,40 +556,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_stmia = i_stm\ni_push = i_stmia\n- '''\n- def i_push(self, op):\n- srcreg = op.opers[0].reg\n- addr = self.getOperValue(op,0)\n- regvals = self.getOperValue(op, 1)\n- regmask = op.opers[1].val\n- pc = self.getRegister(REG_PC) # store for later check\n-\n- addr = self.getRegister(srcreg)\n- for val in regvals:\n- if op.iflags & IF_DAIB_B == IF_DAIB_B:\n- if op.iflags & IF_DAIB_I == IF_DAIB_I:\n- addr += 4\n- else:\n- addr -= 4\n- self.writeMemValue(addr, val, 4)\n- else:\n- self.writeMemValue(addr, val, 4)\n- if op.iflags & IF_DAIB_I == IF_DAIB_I:\n- addr += 4\n- else:\n- addr -= 4\n-\n- if op.opers[0].oflags & OF_W:\n- self.setRegister(srcreg,addr)\n- #FIXME: add \"shared memory\" functionality? prolly just in strex which will be handled in i_strex\n- # is the following necessary?\n- newpc = self.getRegister(REG_PC) # check whether pc has changed\n- if pc != newpc:\n- return newpc\n-'''\n-\n-\n-\ndef i_ldm(self, op):\nif len(op.opers) == 2:\nsrcreg = op.opers[0].reg\n@@ -634,24 +600,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nregval = self.readMemValue(addr, 4)\nself.setRegister(reg, regval)\naddr -= 4\n- '''\n- for reg in xrange(16):\n- if (1<<reg) & regmask:\n- if flags & IF_DAIB_B == IF_DAIB_B:\n- if flags & IF_DAIB_I == IF_DAIB_I:\n- addr += 4\n- else:\n- addr -= 4\n- regval = self.readMemValue(addr, 4)\n- self.setRegister(reg, regval)\n- else:\n- regval = self.readMemValue(addr, 4)\n- self.setRegister(reg, regval)\n- if flags & IF_DAIB_I == IF_DAIB_I:\n- addr += 4\n- else:\n- addr -= 4\n- '''\n+\nif updatereg:\nself.setRegister(srcreg,addr)\n#FIXME: add \"shared memory\" functionality? prolly just in ldrex which will be handled in i_ldrex\n@@ -671,40 +620,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef setArmMode(self, arm=1):\nself.setFlag(PSR_T_bit, not thumb)\n-\n- '''\n- def i_pop(self, op):\n- srcreg = op.opers[0].reg\n- addr = self.getOperValue(op,0)\n- #regmask = self.getOperValue(op,1)\n- regmask = op.opers[1].val\n- pc = self.getRegister(REG_PC) # store for later check\n-\n- for reg in xrange(16):\n- if (1<<reg) & regmask:\n- if op.iflags & IF_DAIB_B == IF_DAIB_B:\n- if op.iflags & IF_DAIB_I == IF_DAIB_I:\n- addr += 4\n- else:\n- addr -= 4\n- regval = self.readMemValue(addr, 4)\n- self.setRegister(reg, regval)\n- else:\n- regval = self.readMemValue(addr, 4)\n- self.setRegister(reg, regval)\n- if op.iflags & IF_DAIB_I == IF_DAIB_I:\n- addr += 4\n- else:\n- addr -= 4\n- if op.opers[0].oflags & OF_W:\n- self.setRegister(srcreg,addr)\n- #FIXME: add \"shared memory\" functionality? prolly just in ldrex which will be handled in i_ldrex\n- # is the following necessary?\n- newpc = self.getRegister(REG_PC) # check whether pc has changed\n- if pc != newpc:\n- return newpc\n- '''\n-\ndef i_ldr(self, op):\n# hint: covers ldr, ldrb, ldrbt, ldrd, ldrh, ldrsh, ldrsb, ldrt (any instr where the syntax is ldr{condition}stuff)\n# need to check that t variants only allow non-priveleged access (ldrt, ldrht etc)\n@@ -741,14 +656,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n- '''def i_adr(self, op):\n- val = self.getOperValue(op, 1)\n- self.setOperValue(op, 0, val)\n-\n- def i_msr(self, op):\n- val = self.getOperValue(op, 1)\n- self.setOperValue(op, 0, val)\n-'''\ni_msr = i_mov\ni_adr = i_mov\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm emu cleanup
|
718,770 |
23.08.2017 19:11:37
| 14,400 |
bc47acde6fdeda48fafebf0ad28505a024179f28
|
arm workspace emulator cleanup ad troubleshooting
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "import envi\nimport envi.archs.arm as e_arm\n+\n+import vivisect\nimport vivisect.impemu.emulator as v_i_emulator\nimport visgraph.pathcore as vg_path\nfrom envi.archs.arm.regs import *\n+\n+verbose = True\n+\nclass ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\ntaintregs = [ x for x in range(13) ]\n@@ -36,7 +41,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\n# parse out an opcode\ntmode = self.getFlag(PSR_T_bit)\n- print \"tmode: %x\" % tmode\n+ #print \"tmode: %x\" % tmode\nop = self.parseOpcode(starteip | tmode)\nif self.emumon:\nself.emumon.prehook(self, op, starteip)\n@@ -67,7 +72,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nelif funcva & 3:\nself.setFlag(PSR_T_bit, 1)\nfuncva &= -2\n- print \"funcva is THUMB: 0x%x\" % funcva\n+ if verbose: print \"funcva is THUMB: 0x%x\" % funcva\nelse:\nloc = self.vw.getLocation(funcva)\n@@ -77,7 +82,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.setFlag(PSR_T_bit, 1)\nelse:\n- print \"ArmWorkspaceEmulator: Nothing specified, defaulting to ARM\"\n+ if verbose: print \"ArmWorkspaceEmulator: Nothing specified, defaulting to ARM\"\nself.funcva = funcva\n@@ -130,10 +135,9 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\ntry:\ntmode = self.getFlag(PSR_T_bit)\n- print \"tmode: %x\" % tmode\n+ #print \"tmode: %x\" % tmode\n# FIXME unify with stepi code...\nop = self.parseOpcode(starteip | tmode)\n- print \"emu: 0x%x flags: 0x%x \\t %r\" % (starteip, op.iflags, op)\nself.op = op\nif self.emumon:\n@@ -177,15 +181,17 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nexcept envi.UnsupportedInstruction, e:\nif self.strictops:\n+ if verbose: print 'runFunction breaking after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\nbreak\nelse:\n- print 'runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\n+ if verbose: print 'runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\nself.setProgramCounter(e.op.va+ e.op.size)\nexcept Exception, e:\n#traceback.print_exc()\nif self.emumon != None:\nself.emumon.logAnomaly(self, starteip, str(e))\n+ if verbose: print 'runFunction breaking after exception: %s' % ( e)\nbreak # If we exc during execution, this branch is dead.\n#except:\n# sys.excepthook(*sys.exc_info())\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm workspace emulator cleanup ad troubleshooting
|
718,770 |
23.08.2017 23:53:03
| 14,400 |
106ffc1fd0fff3d703cf70dea470975039908b0a
|
emu conditionals mods. don't shift, and use the PSR_*_bit constants. (bugfix)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -61,47 +61,55 @@ def _getRegIdx(idx, mode):\nridx = reg_table[ridx] # magic pointers allowing overlapping banks of registers\nreturn ridx\n-def c0000(flags):\n- return flags & 4\n-def c0001(flags):\n- return flags & 4 == 0\n+ZC_bits = PSR_Z_bit | PSR_C_bit\n+NC_bits = PSR_N_bit | PSR_C_bit\n+NZ_bits = PSR_N_bit | PSR_Z_bit\n+NV_bits = PSR_N_bit | PSR_V_bit\n-def c0010(flags):\n- return flags & 2\n-def c0011(flags):\n- return flags & 2 == 0\n+def c0000(flags): # EQ\n+ return flags & PSR_Z_bit\n-def c0100(flags):\n- return flags & 8\n+def c0001(flags): # NE\n+ return flags & PSR_Z_bit == 0\n-def c0101(flags):\n- return flags & 8 == 0\n+def c0010(flags): # CS\n+ return flags & PSR_C_bit\n-def c0110(flags):\n- return flags & 1\n+def c0011(flags): # CC\n+ return flags & PSR_C_bit == 0\n-def c0111(flags):\n- return flags & 1 == 0\n+def c0100(flags): # MI\n+ return flags & PSR_N_bit\n-def c1000(flags):\n- return (flags & 6) == 2\n+def c0101(flags): # PL\n+ return flags & PSR_N_bit == 0\n-def c1001(flags):\n- return (flags & 0xc) in (0, 4, 6) # C clear or Z set\n+def c0110(flags): # VS\n+ return flags & PSR_V_bit\n-def c1010(flags):\n- return (flags & 9) in (0, 9) # N == V\n+def c0111(flags): # VC\n+ return flags & PSR_V_bit == 0\n-def c1011(flags):\n- return (flags & 9) in (1, 8) # N != V\n+def c1000(flags): # HI\n+ return (flags & ZC_bits) == PSR_C_bit # C set and Z clear\n-def c1100(flags):\n- return (flags & 4) == 0 and (flags & 9) in (0, 9) # Z==0, N==V\n+def c1001(flags): # LS\n+ #return (flags & NZ_bits) in (0, PSR_Z_bit, ZC_bits) # C clear or Z set\n+ return (flags & PSR_C_bit == 0) or (flags & PSR_Z_bit) # C clear or Z set\n-def c1101(flags):\n- return (flags & 4) or (flags & 9) in (1, 8) # Z==1 or N!=V (basically, \"not c1100\")\n+def c1010(flags): # GE\n+ return (flags & NV_bits) in (0, NV_bits) # N == V\n+\n+def c1011(flags): # LT\n+ return (flags & NV_bits) in (PSR_V_bit, PSR_N_bit) # N != V\n+\n+def c1100(flags): # GT\n+ return (flags & PSR_Z_bit) == 0 and (flags & NV_bits) in (0, NV_bits) # Z==0, N==V\n+\n+def c1101(flags): # LE\n+ return (flags & PSR_Z_bit) or (flags & NV_bits) in (PSR_V_bit, PSR_N_bit) # Z==1 or N!=V (basically, \"not c1100\")\nconditionals = [\n@@ -213,7 +221,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ntry:\nself.setMeta('forrealz', True)\nx = None\n- if op.prefixes >= 0xe or conditionals[op.prefixes](self.getRegister(REG_FLAGS)>>28):\n+ #if op.prefixes >= 0xe or conditionals[op.prefixes](self.getRegister(REG_FLAGS)>>28):\n+ if op.prefixes >= 0xe or conditionals[op.prefixes](self.getRegister(REG_FLAGS)):\nmeth = self.op_methods.get(op.mnem, None)\nif meth == None:\nraise envi.UnsupportedInstruction(self, op)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
emu conditionals mods. don't shift, and use the PSR_*_bit constants. (bugfix)
|
718,770 |
25.08.2017 15:20:26
| 14,400 |
367b5139c2009b9b1d914072ffbed5e71d292102
|
fixing several GUI things: 0-based files should now work appropriately, "view" menu shouldn't be shown twice in function graphs.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/qt/memcanvas.py",
"new_path": "envi/qt/memcanvas.py",
"diff": "@@ -190,7 +190,7 @@ class VQMemoryCanvas(QtWebKit.QWebView, e_memcanvas.MemoryCanvas):\nva = self._canv_curva\nmenu = QtGui.QMenu()\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.initMemWindowMenu(va, menu)\nviewmenu = menu.addMenu('view ')\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -96,10 +96,6 @@ class VQVivFuncgraphCanvas(vq_memory.VivCanvasBase):\nself.viewmenu.addAction(\"Paint Down\", ACT(self.paintDown.emit))\nself.viewmenu.addAction(\"Paint Down until remerge\", ACT(self.paintMerge.emit))\n- viewmenu = menu.addMenu('view ')\n- viewmenu.addAction(\"Save frame to HTML\", ACT(self._menuSaveToHtml))\n- viewmenu.addAction(\"Refresh\", ACT(self.refresh))\n-\nmenu.exec_(event.globalPos())\ndef _navExpression(self, expr):\n@@ -505,7 +501,7 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QtGui.\ndef clearText(self):\n# Pop the svg and reset #memcanvas\nframe = self.mem_canvas.page().mainFrame()\n- if self.fva:\n+ if self.fva != None:\nsvgid = '#funcgraph_%.8x' % self.fva\nsvgelem = frame.findFirstElement(svgid)\nsvgelem.removeFromDocument()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "@@ -85,7 +85,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:nextva')\ndef _hotkey_nav_nextva(self):\n- if not self._canv_curva:\n+ if self._canv_curva != None:\nreturn\nloc = self.vw.getLocation(self._canv_curva)\n@@ -97,7 +97,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:prevva')\ndef _hotkey_nav_prevva(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nloc = self.vw.getPrevLocation(self._canv_curva)\n@@ -108,7 +108,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:nextundef')\ndef _hotkey_nav_nextundef(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nvw = self.vw\n@@ -137,7 +137,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:prevundef')\ndef _hotkey_nav_prevundef(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nvw = self.vw\n@@ -166,65 +166,65 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:make:code')\ndef _hotkey_make_code(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeCode(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:function')\ndef _hotkey_make_function(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeFunction(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:string')\ndef _hotkey_make_string(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeString(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:pointer')\ndef _hotkey_make_pointer(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makePointer(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:unicode')\ndef _hotkey_make_unicode(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeUnicode(self._canv_curva)\n@vq_hotkey.hotkey('viv:undefine')\ndef _hotkey_undefine(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.delLocation(self._canv_curva)\n@vq_hotkey.hotkey('viv:setname')\ndef _hotkey_setname(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.getVivGui().setVaName( self._canv_curva, parent=self )\n@vq_hotkey.hotkey('viv:bookmark')\ndef _hotkey_bookmark(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.getVivGui().addBookmark( self._canv_curva, parent=self )\n@vq_hotkey.hotkey('viv:comment')\ndef _hotkey_comment(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.getVivGui().setVaComment( self._canv_curva, parent=self )\n@vq_hotkey.hotkey('viv:make:struct')\ndef _hotkey_make_struct(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nsname = self.vw.getVivGui().makeStruct(self._canv_curva)\nif sname != None:\nself._last_sname = sname\n@vq_hotkey.hotkey('viv:make:struct:again')\ndef _hotkey_make_struct_again(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nif self._last_sname != None:\nself.vw.makeStructure(self._canv_curva, self._last_sname)\n@vq_hotkey.hotkey('viv:make:struct:multi')\ndef _hotkey_make_struct_multi(self, parent=None):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nif self._last_sname != None:\nnumber, ok = QtGui.QInputDialog.getText(parent, 'Make Multiple Consecutive Structs', 'Number of Structures')\nif ok:\n@@ -248,27 +248,27 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:make:number:one')\ndef _hotkey_make_number_one(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 1)\n@vq_hotkey.hotkey('viv:make:number:two')\ndef _hotkey_make_number_two(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 2)\n@vq_hotkey.hotkey('viv:make:number:four')\ndef _hotkey_make_number_four(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 4)\n@vq_hotkey.hotkey('viv:make:number:eight')\ndef _hotkey_make_number_eight(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 8)\n@vq_hotkey.hotkey('viv:make:number:sixteen')\ndef _hotkey_make_number_sixteen(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 16)\n@firethread\n@@ -407,7 +407,7 @@ class VQVivMemoryView(e_mem_qt.VQMemoryWindow, viv_base.VivEventCore):\ndef _viv_xrefsto(self):\n- if self.mem_canvas._canv_curva:\n+ if self.mem_canvas._canv_curva != None:\nxrefs = self.vw.getXrefsTo(self.mem_canvas._canv_curva)\nif len(xrefs) == 0:\nself.vw.vprint('No xrefs found!')\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fixing several GUI things: 0-based files should now work appropriately, "view" menu shouldn't be shown twice in function graphs.
|
718,770 |
25.08.2017 15:11:27
| 14,400 |
4540604c39900d340263f766bcb1788c9b722701
|
ARM emu fixes (primarily, Post-Indexing should work now)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -746,7 +746,7 @@ def p_dp_imm(opval, va):\n)\nif sflag > 0:\n- iflags |= DP_PSR_S[ocode]\n+ iflags = DP_PSR_S[ocode]\nelse:\niflags = 0\n@@ -4275,7 +4275,7 @@ class ArmScaledOffsetOper(ArmOperand):\n# p = indexed\n# u = add\n- if (self.pubwl & 0x2): # write-back\n+ if (self.pubwl & 0x2 or not self.pubwl & 0x10): # write-back if (P==0 || W==1)\nif (emu != None) and (emu.getMeta('forrealz', False)): emu.setRegister( self.base_reg, addr)\nif (self.pubwl & 0x10 == 0): # not indexed\n@@ -4386,7 +4386,7 @@ class ArmRegOffsetOper(ArmOperand):\naddr = base + (pom*rm) & e_bits.u_maxes[self.psize]\n- if (self.pubwl & 0x2): # write-back\n+ if (self.pubwl & 0x2 or not self.pubwl & 0x10): # write-back if (P==0 || W==1)\nif (emu != None) and (emu.getMeta('forrealz', False)): emu.setRegister( self.base_reg, addr)\nif (self.pubwl & 0x10 == 0): # not indexed\n@@ -4505,7 +4505,7 @@ class ArmImmOffsetOper(ArmOperand):\naddr = (base - self.offset) & e_bits.u_maxes[self.psize]\n- if (self.pubwl & 0x2): # write-back\n+ if (self.pubwl & 0x2 or not self.pubwl & 0x10): # write-back if (P==0 || W==1)\nif (emu != None) and (emu.getMeta('forrealz', False)): emu.setRegister( self.base_reg, addr)\nif (self.pubwl & 0x10 == 0): # not indexed\n@@ -4547,13 +4547,12 @@ class ArmImmOffsetOper(ArmOperand):\nmcanv.addNameText(basereg, typename='registers')\nif self.offset == 0:\nmcanv.addText(']')\n+\nelse:\nif (idxing&0x10) == 0:\nmcanv.addText(']')\n- else:\n- mcanv.addText(', ')\n- mcanv.addNameText('#%s0x%x' % (pom,self.offset))\n+ mcanv.addNameText(', #%s0x%x' % (pom,self.offset))\nif idxing == 0x10:\nmcanv.addText(']')\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -222,7 +222,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setMeta('forrealz', True)\nx = None\n#if op.prefixes >= 0xe or conditionals[op.prefixes](self.getRegister(REG_FLAGS)>>28):\n- if op.prefixes >= 0xe or conditionals[op.prefixes](self.getRegister(REG_FLAGS)):\n+\n+ condval = (op.prefixes >= 0xe)\n+ if not condval:\n+ condcheck = conditionals[op.prefixes]\n+ condval = condcheck(self.getRegister(REG_FLAGS))\n+\n+ if condval:\nmeth = self.op_methods.get(op.mnem, None)\nif meth == None:\nraise envi.UnsupportedInstruction(self, op)\n@@ -374,7 +380,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn self.intSubBase(src1, src2, Sflag)\n- def AddWithCarry(self, src1, src2, carry=0, Sflag=0, rd=0):\n+ def AddWithCarry(self, src1, src2, carry=0, Sflag=0, rd=0, tsize=4):\n'''////AddWithCarry()\n==============\n(bits(N), bit, bit) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)\n@@ -399,18 +405,18 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nsubtractions as well as carry flags for additions.\n(@ we don't retrn carry-out and overflow, but set the flags here)\n'''\n- udst = e_bits.unsigned(src1, 4)\n- usrc = e_bits.unsigned(src2, 4)\n+ udst = e_bits.unsigned(src1, tsize)\n+ usrc = e_bits.unsigned(src2, tsize)\n- sdst = e_bits.signed(src1, 4)\n- ssrc = e_bits.signed(src2, 4)\n+ sdst = e_bits.signed(src1, tsize)\n+ ssrc = e_bits.signed(src2, tsize)\n- ures = (udst + usrc + carry) & 0xffffffff\n- sres = (sdst + ssrc + carry)\n+ ures = e_bits.unsigned(udst + usrc + carry, tsize)\n+ sres = e_bits.signed(sdst + ssrc + carry, tsize)\nresult = ures & 0x7fffffff\n- #newcarry = (ures != result)\n- newcarry = (udst >= usrc)\n+ newcarry = (ures != result)\n+ #newcarry = (udst >= usrc)\noverflow = (sres != result)\nif Sflag:\n@@ -421,24 +427,24 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nelse:\nraise Exception(\"Messed up opcode... adding to r15 from PM_usr or PM_sys\")\nelse:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))\n- self.setFlag(PSR_Z_bit, not ures)\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(result, tsize))\n+ self.setFlag(PSR_Z_bit, not result)\nself.setFlag(PSR_C_bit, newcarry)\nself.setFlag(PSR_V_bit, overflow)\n- return ures\n+ return result\n- def intSubBase(self, src1, src2, Sflag=0, rd=0):\n+ def intSubBase(self, src1, src2, Sflag=0, rd=0, tsize=4):\n# So we can either do a BUNCH of crazyness with xor and shifting to\n# get the necessary flags here, *or* we can just do both a signed and\n# unsigned sub and use the results.\n- udst = e_bits.unsigned(src1, 4)\n- usrc = e_bits.unsigned(src2, 4)\n+ udst = e_bits.unsigned(src1, tsize)\n+ usrc = e_bits.unsigned(src2, tsize)\n- sdst = e_bits.signed(src1, 4)\n- ssrc = e_bits.signed(src2, 4)\n+ sdst = e_bits.signed(src1, tsize)\n+ ssrc = e_bits.signed(src2, tsize)\nures = udst - usrc\nsres = sdst - ssrc\n@@ -450,10 +456,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setCPSR(self.getSPSR(curmode))\nelse:\nraise Exception(\"Messed up opcode... adding to r15 from PM_usr or PM_sys\")\n- self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(ures, tsize))\nself.setFlag(PSR_Z_bit, not ures)\n- self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, 4))\n- self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, 4))\n+ self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, tsize))\n+ self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, tsize))\nreturn ures\n@@ -496,6 +502,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, res)\ndef i_orr(self, op):\n+ tsize = op.opers[0].tsize\nval1 = self.getOperValue(op, 1)\nval2 = self.getOperValue(op, 2)\nval = val1 | val2\n@@ -503,10 +510,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, tsize))\nself.setFlag(PSR_Z_bit, not val)\n- self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, 4))\n- self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, tsize))\n+ self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, tsize))\ndef i_stm(self, op):\nif len(op.opers) == 2:\n@@ -698,10 +705,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndsize = op.opers[0].tsize\nssize = op.opers[1].tsize\n- usrc1 = e_bits.unsigned(src1, 4)\n- usrc2 = e_bits.unsigned(src2, 4)\n- ssrc1 = e_bits.signed(src1, 4)\n- ssrc2 = e_bits.signed(src2, 4)\n+ usrc1 = e_bits.unsigned(src1, dsize)\n+ usrc2 = e_bits.unsigned(src2, dsize)\n+ ssrc1 = e_bits.signed(src1, dsize)\n+ ssrc2 = e_bits.signed(src2, dsize)\nures = usrc1 + usrc2\nsres = ssrc1 + ssrc2\n@@ -805,10 +812,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndsize = op.opers[0].tsize\nssize = op.opers[1].tsize\n- usrc1 = e_bits.unsigned(src1, 4)\n- usrc2 = e_bits.unsigned(src2, 4)\n- ssrc1 = e_bits.signed(src1, 4)\n- ssrc2 = e_bits.signed(src2, 4)\n+ usrc1 = e_bits.unsigned(src1, dsize)\n+ usrc2 = e_bits.unsigned(src2, dsize)\n+ ssrc1 = e_bits.signed(src1, dsize)\n+ ssrc2 = e_bits.signed(src2, dsize)\nures = usrc2 - usrc1\nsres = ssrc2 - ssrc1\n@@ -883,6 +890,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, res)\ndef i_eor(self, op):\n+ dsize = op.opers[0].tsize\nsrc1 = self.getOperValue(op, 1)\nsrc2 = self.getOperValue(op, 2)\n@@ -892,8 +900,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, None)\nreturn\n- usrc1 = e_bits.unsigned(src1, 4)\n- usrc2 = e_bits.unsigned(src2, 4)\n+ usrc1 = e_bits.unsigned(src1, dsize)\n+ usrc2 = e_bits.unsigned(src2, dsize)\nures = usrc1 ^ usrc2\n@@ -906,10 +914,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setCPSR(self.getSPSR(curmode))\nelse:\nraise Exception(\"Messed up opcode... adding to r15 from PM_usr or PM_sys\")\n- self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, 4))\n+ self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, dsize))\nself.setFlag(PSR_Z_bit, not ures)\n- self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))\n- self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(ures, dsize))\n+ self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, dsize))\ndef i_cmp(self, op):\n# Src op gets sign extended to dst\n@@ -952,6 +960,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_cmps = i_cmp\ndef i_bic(self, op):\n+ dsize = op.opers[0].tsize\nval = self.getOperValue(op, 1)\nconst = self.getOperValue(op, 2)\nval &= ~const\n@@ -959,16 +968,17 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S # FIXME: IF_PSR_S???\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\n- self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, 4))\n- self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, dsize))\n+ self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_swi(self, op):\n# this causes a software interrupt. we need a good way to handle interrupts\nself.interrupt(op.opers[0].val)\ndef i_mul(self, op):\n+ dsize = op.opers[0].tsize\nRn = self.getOperValue(op, 1)\nif len(op.opers) == 3:\nRm = self.getOperValue(op, 2)\n@@ -979,12 +989,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\n- self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, 4))\n- self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, dsize))\n+ self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_lsl(self, op):\n+ dsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\nimm5 = self.getOperValue(op, 2)\n@@ -999,12 +1010,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\nself.setFlag(PSR_C_bit, carry)\n- #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_lsr(self, op):\n+ dsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\nimm5 = self.getOperValue(op, 2)\n@@ -1019,12 +1031,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\nself.setFlag(PSR_C_bit, carry)\n- #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_asr(self, op):\n+ dsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\nsrclen = op.opers[1].tsize\n@@ -1045,12 +1058,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\nself.setFlag(PSR_C_bit, carry)\n- #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_ror(self, op):\n+ dsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\nimm5 = self.getOperValue(op, 2)\n@@ -1065,12 +1079,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\nself.setFlag(PSR_C_bit, carry)\n- #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_rrx(self, op):\n+ dsize = op.opers[0].tsize\nif len(op.opers) == 3:\nsrc = self.getOperValue(op, 1)\nimm5 = self.getOperValue(op, 2)\n@@ -1087,10 +1102,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = op.iflags & IF_PSR_S\nif Sflag:\n- self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, dsize))\nself.setFlag(PSR_Z_bit, not val)\nself.setFlag(PSR_C_bit, carry)\n- #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))\n+ #self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, dsize))\ndef i_cbz(self, op):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
ARM emu fixes (primarily, Post-Indexing should work now)
|
718,770 |
25.08.2017 15:50:12
| 14,400 |
99bf5c6d0b1c7602ec60ede02f9fce8ff0f9b763
|
missed a couple.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -84,7 +84,7 @@ class VQVivFuncgraphCanvas(vq_memory.VivCanvasBase):\nreturn ret\ndef contextMenuEvent(self, event):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nmenu = vq_ctxmenu.buildContextMenu(self.vw, va=self._canv_curva, parent=self)\nelse:\nmenu = QtGui.QMenu(parent=self)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/views.py",
"new_path": "vivisect/qt/views.py",
"diff": "@@ -408,7 +408,7 @@ class VQXrefView(VQVivTreeView):\nfor fromva, tova, rtype, rflags in xrefs:\nfva = vw.getFunction(fromva)\nfuncname = ''\n- if fva:\n+ if fva != None:\nfuncname = vw.getName(fva)\nself.vivAddRow(fromva, '0x%.8x' % fromva, rtype, rflags, funcname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
missed a couple.
|
718,770 |
23.09.2017 12:41:46
| 14,400 |
dee136a243404c94296067998ae3d8db1bdf6821
|
fix vivisect addEntryPoint to properly handle the default return from archModifyFuncVa()
|
[
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -264,7 +264,7 @@ class CodeFlowContext(object):\n# Architecture gets to decide on actual final VA and Architecture (ARM/THUMB/etc...)\ninfo = { 'arch' : arch }\nva, info = self._mem.arch.archModifyFuncAddr(va, info)\n- arch = info.get('arch', envi.ARCH_DEFAULT)\n+ arch = info.get('arch', arch)\n# Check if this is already a known function.\nif self._funcs.get(va) != None:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fix vivisect addEntryPoint to properly handle the default return from archModifyFuncVa()
|
718,770 |
26.09.2017 23:08:41
| 14,400 |
8c95c7ff0f1b89038944dc0d5764e9775c81ce92
|
fixing mvn decoding
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -113,7 +113,7 @@ def rd_pc_imm8(va, value): # add\ndef rt_pc_imm8(va, value): # ldr\nrt = shmaskval(value, 8, 0x7)\n- imm = e_bits.signed((value & 0xff), 1) << 2\n+ imm = e_bits.unsigned((value & 0xff), 1) << 2\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmImmOffsetOper(REG_PC, imm, (va&0xfffffffc))\nreturn COND_AL,(oper0,oper1), None\n@@ -766,6 +766,13 @@ def dp_mod_imm_32(va, val1, val2):\nopers = (oper1, oper2)\nreturn COND_AL, None, mnem, opers, flags, 0\n+ elif Rn == 15 and (val1 & 0xfbe0 == 0xf060):\n+ mnem = 'mvn'\n+ oper1 = ArmRegOper(Rd)\n+ oper2 = ArmImmOper((i<<11) | (imm3<<8) | const)\n+ opers = (oper1, oper2)\n+ return COND_AL, None, mnem, opers, flags, 0\n+\noper0 = ArmRegOper(Rd)\noper1 = ArmRegOper(Rn)\noper2 = ArmImmOper(const)\n@@ -1862,13 +1869,13 @@ thumb2_extension = [\n('11101011110', (85,'rsb', dp_shift_32, IF_THUMB32)),\n# coproc, adv simd, fp-instrs #ed9f 5a31\n- ('11101100', (85,'coproc simd', coproc_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n- ('11101101', (85,'coproc simd', coproc_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n- ('11101110', (85,'coproc simd', coproc_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n- ('11101111', (85,'adv simd', adv_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n- ('1111110', (85,'coproc simd', coproc_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n- ('11111110', (85,'coproc simd', coproc_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n- ('11111111', (85,'adv simd', adv_simd_32, IF_THUMB32)), # FIXME: not fully implemented\n+ ('11101100', (85,'coproc simd', coproc_simd_32, IF_THUMB32)),\n+ ('11101101', (85,'coproc simd', coproc_simd_32, IF_THUMB32)),\n+ ('11101110', (85,'coproc simd', coproc_simd_32, IF_THUMB32)),\n+ ('11101111', (85,'adv simd', adv_simd_32, IF_THUMB32)),\n+ ('1111110', (85,'coproc simd', coproc_simd_32, IF_THUMB32)),\n+ ('11111110', (85,'coproc simd', coproc_simd_32, IF_THUMB32)),\n+ ('11111111', (85,'adv simd', adv_simd_32, IF_THUMB32)),\n# data-processing (modified immediate)\n('11110000000', (85,'and', dp_mod_imm_32, IF_THUMB32)), # tst if rd=1111 and s=1\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fixing mvn decoding
|
718,770 |
27.09.2017 11:27:19
| 14,400 |
1e8223859e9c9098d8eb6dc88a3d730a584717c7
|
bugfixes: ThumbExpandImm_C, shifters, dp_secondaries (Rn or Rd are 0xF)..
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -523,8 +523,9 @@ def imm5_rm_rd(va, value):\nstype = value >> 11\noper0 = ArmRegOper(rd, va)\n- oper1 = ArmRegShiftImmOper(rm, stype, imm5, va)\n- return COND_AL,(oper0, oper1,), None\n+ oper1 = ArmRegOper(rm, va)\n+ oper2 = ArmImmOper(imm5)\n+ return COND_AL,(oper0, oper1, oper2), None\ndef i_imm5_rn(va, value):\n@@ -719,7 +720,7 @@ def ThumbExpandImm_C(imm4, imm8, carry):\ndp_secondary = (\n'tst',# and\nNone, # bic\n- None, # orr\n+ 'mov', # orr\n'mvn', # orn\n'teq', # eor\nNone, #\n@@ -734,6 +735,13 @@ dp_secondary = (\nNone,\nNone,\n)\n+\n+dp_sec_silS = (0,4,8,13)\n+# IF_PSR_S_SIL is silent s for tst, teq, cmp cmn\n+DP_SEC_PSR_S = [IF_PSR_S for x in range(17)]\n+for x in dp_sec_silS:\n+ DP_SEC_PSR_S[x] |= IF_PSR_S_SIL\n+\ndef dp_mod_imm_32(va, val1, val2):\nif val2 & 0x8000:\nreturn branch_misc(va, val1,val2)\n@@ -747,32 +755,38 @@ def dp_mod_imm_32(va, val1, val2):\ni = (val1 >> 10) & 1\nimm3 = (val2 >> 12) & 0x7\nimm4 = imm3 | (i<<3)\n- const = val2 & 0xff\n+ const = (val2 & 0xff)\n- if S:\n- flags |= IF_PSR_S\n+ dpop = (val1>>5) & 0xf\nconst,carry = ThumbExpandImm_C(imm4, const, 0)\nif Rd==15 and S:\n#raise Exception(\"dp_mod_imm_32 - FIXME: secondary dp encoding\")\n- dpop = (val1>>5) & 0xf\nmnem = dp_secondary[dpop]\nif mnem == None:\nraise Exception(\"dp_mod_imm_32: Rd==15, S, but dpop doesn't have a secondary! va:%x, %x%x\" % (va, val1, val2))\n+ if S:\n+ flags |= DP_SEC_PSR_S[dpop]\noper1 = ArmRegOper(Rn)\noper2 = ArmImmOper(const)\nopers = (oper1, oper2)\nreturn COND_AL, None, mnem, opers, flags, 0\n- elif Rn == 15 and (val1 & 0xfbe0 == 0xf060):\n- mnem = 'mvn'\n+ elif Rn == 15 and (val1 & 0xfbc0 == 0xf040):\n+ dpop = (val1>>5) & 0xf\n+ mnem = dp_secondary[dpop]\n+ if S:\n+ flags |= DP_SEC_PSR_S[dpop]\noper1 = ArmRegOper(Rd)\n- oper2 = ArmImmOper((i<<11) | (imm3<<8) | const)\n+ oper2 = ArmImmOper(const)\nopers = (oper1, oper2)\nreturn COND_AL, None, mnem, opers, flags, 0\n+ if S:\n+ flags |= IF_PSR_S\n+\noper0 = ArmRegOper(Rd)\noper1 = ArmRegOper(Rn)\noper2 = ArmImmOper(const)\n@@ -1671,9 +1685,9 @@ bcc_ops = {\n# FIXME: thumb and arm opcode numbers don't line up. - FIX\nthumb_base = [\n- ('00000', ( INS_LSL,'lsl', imm5_rm_rd, 0)), # LSL<c> <Rd>,<Rm>,#<imm5>\n- ('00001', ( INS_LSR,'lsr', imm5_rm_rd, 0)), # LSR<c> <Rd>,<Rm>,#<imm>\n- ('00010', ( INS_ASR,'asr', imm5_rm_rd, 0)), # ASR<c> <Rd>,<Rm>,#<imm>\n+ ('00000', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n+ ('00001', ( INS_LSR,'lsr', imm5_rm_rd, IF_PSR_S)), # LSR<c> <Rd>,<Rm>,#<imm>\n+ ('00010', ( INS_ASR,'asr', imm5_rm_rd, IF_PSR_S)), # ASR<c> <Rd>,<Rm>,#<imm>\n('0001100', ( INS_ADD,'add', rm_rn_rd, 0)), # ADD<c> <Rd>,<Rn>,<Rm>\n('0001101', ( INS_SUB,'sub', rm_rn_rd, 0)), # SUB<c> <Rd>,<Rn>,<Rm>\n('0001110', ( INS_ADD,'add', imm3_rn_rd, 0)), # ADD<c> <Rd>,<Rn>,#<imm3>\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfixes: ThumbExpandImm_C, shifters, dp_secondaries (Rn or Rd are 0xF)..
|
718,770 |
27.09.2017 11:39:52
| 14,400 |
629ba39fe313fd997d6dbc2c063dfed73a7e02e4
|
str.w immoff bugfix (imm8 should be imm12, meaning different decoder)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1947,7 +1947,7 @@ thumb2_extension = [\n#('111110001001', (INS_LDRB, 'ldrb', ldr_32, IF_THUMB32)),\n('111110001010', (INS_STR, 'str', ldr_32, IF_H | IF_THUMB32)),\n('111110001011', (INS_LDR, 'ldr', ldr_32, IF_H | IF_THUMB32)),\n- ('111110001100', (INS_STR, 'str', ldr_puw_32, IF_THUMB32)),\n+ ('111110001100', (INS_STR, 'str', ldr_32, IF_THUMB32)),\n('111110001101', (INS_LDR, 'ldr', ldr_32, IF_THUMB32)), # T3\n('111110001000', (INS_STR, 'str', ldr_32, IF_B | IF_THUMB32)),\n('111110000000', (INS_STR, 'str', ldr_puw_32, IF_B | IF_THUMB32)),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
str.w immoff bugfix (imm8 should be imm12, meaning different decoder)
|
718,770 |
27.09.2017 11:40:15
| 14,400 |
593ec931984965e7fec3ad278852d8deb41fa800
|
rearranging a few lines.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1936,21 +1936,22 @@ thumb2_extension = [\n('11110111101', (85,'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n('11110111110', (85,'ubfx', ubfx_32, IF_THUMB32)),\n('11110111111', (85,'branchmisc', branch_misc, IF_THUMB32)),\n+ ('111110000000', (INS_STR, 'str', ldr_puw_32, IF_B | IF_THUMB32)),\n('111110000001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n('111110000010', (INS_STR, 'str', ldr_puw_32, IF_H | IF_THUMB32)),\n('111110000011', (INS_LDR, 'ldr', ldr_puw_32, IF_H | IF_THUMB32)),\n('111110000100', (INS_STR, 'str', ldr_puw_32, IF_THUMB32)), # T4 encoding\n('111110000101', (INS_LDR, 'ldr', ldr_puw_32, IF_THUMB32)), # T4 encoding\n- ('111110001001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n- ('111110010001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n- ('111110011001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n#('111110001001', (INS_LDRB, 'ldrb', ldr_32, IF_THUMB32)),\n+ ('111110001001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n('111110001010', (INS_STR, 'str', ldr_32, IF_H | IF_THUMB32)),\n('111110001011', (INS_LDR, 'ldr', ldr_32, IF_H | IF_THUMB32)),\n('111110001100', (INS_STR, 'str', ldr_32, IF_THUMB32)),\n('111110001101', (INS_LDR, 'ldr', ldr_32, IF_THUMB32)), # T3\n('111110001000', (INS_STR, 'str', ldr_32, IF_B | IF_THUMB32)),\n- ('111110000000', (INS_STR, 'str', ldr_puw_32, IF_B | IF_THUMB32)),\n+ ('111110010001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n+ ('111110011001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n+\n# data-processing (register)\n('111110100', (None, 'shift_or_extend', shift_or_ext_32, IF_THUMB32)),\n#('111110101', (None, 'parallel_misc', parallel_misc_32, IF_THUMB32)),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
rearranging a few lines.
|
718,770 |
29.09.2017 22:49:24
| 14,400 |
7cb8d640d1bfdde806e841de5d93c24de55b15b0
|
tracking bugs (including va)
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -191,7 +191,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif self.emumon != None:\nself.emumon.logAnomaly(self, starteip, str(e))\n- if verbose: print 'runFunction breaking after exception: %s' % ( e)\n+ if verbose: print 'runFunction breaking after exception (0x%x): %s' % (e.op.va, e)\nbreak # If we exc during execution, this branch is dead.\n#except:\n# sys.excepthook(*sys.exc_info())\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
tracking bugs (including va)
|
718,770 |
29.09.2017 22:49:59
| 14,400 |
f36f317cabcc6ecc7a2727eec00873f8567eb070
|
arm canvas updates
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -4151,7 +4151,8 @@ class ArmImmOper(ArmOperand):\ndef render(self, mcanv, op, idx):\nval = self.getOperValue(op)\n- mcanv.addNameText('#0x%.2x' % (val))\n+ mcanv.addText('#')\n+ mcanv.addNameText('0x%.2x' % (val))\ndef repr(self, op):\nval = self.getOperValue(op)\n@@ -4552,7 +4553,8 @@ class ArmImmOffsetOper(ArmOperand):\nif (idxing&0x10) == 0:\nmcanv.addText(']')\n- mcanv.addNameText(', #%s0x%x' % (pom,self.offset))\n+ mcanv.addText(', #%s' % (pom))\n+ mcanv.addNameText('0x%x' % (self.offset))\nif idxing == 0x10:\nmcanv.addText(']')\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm canvas updates
|
718,770 |
29.09.2017 22:51:44
| 14,400 |
0d500304f9347bc47dc1ac705574dc5ac1ad2927
|
thumb decoding bugfixes: mcr/mrc, dp, etc...
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -437,7 +437,7 @@ def branch_misc(va, val, val2): # bl and misc control\nbytez=struct.pack(\"<H\", val)+struct.pack(\"<H\", val2), va=va-4)\nelif op1 & 0b100:\n- # bl/lx\n+ # bl/blx\nnotx = (val2>>12) & 1\ns = (val>>10) & 1\nmnem = ('blx','bl')[notx]\n@@ -450,11 +450,11 @@ def branch_misc(va, val, val2): # bl and misc control\nimm = (s<<24) | (j1<<23) | (j2<<22) | ((val&0x3ff) << 12) | ((val2&0x7ff) << 1)\n- #sign extend a 23-bit number\n+ #sign extend a 25-bit number\nif s:\nimm |= 0xff000000\n- oper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va&0xfffffffc)\n+ oper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va&0xfffffffe)\nreturn COND_AL, opcode, mnem, (oper0, ), flags, 0\n@@ -1484,7 +1484,7 @@ def coproc_simd_32(va, val1, val2):\nload = (val1>>4) & 1\ntwo = (val1>>11) & 2\nopc1 = (val1>>5) & 0x7\n- CRn = val2 & 0xf\n+ CRn = val1 & 0xf\nRd = (val2>>12) & 0xf\nopc2 = (val2>>5) & 0x7\nCRm = val2 & 0xf\n@@ -1688,29 +1688,29 @@ thumb_base = [\n('00000', ( INS_LSL,'lsl', imm5_rm_rd, IF_PSR_S)), # LSL<c> <Rd>,<Rm>,#<imm5>\n('00001', ( INS_LSR,'lsr', imm5_rm_rd, IF_PSR_S)), # LSR<c> <Rd>,<Rm>,#<imm>\n('00010', ( INS_ASR,'asr', imm5_rm_rd, IF_PSR_S)), # ASR<c> <Rd>,<Rm>,#<imm>\n- ('0001100', ( INS_ADD,'add', rm_rn_rd, 0)), # ADD<c> <Rd>,<Rn>,<Rm>\n- ('0001101', ( INS_SUB,'sub', rm_rn_rd, 0)), # SUB<c> <Rd>,<Rn>,<Rm>\n- ('0001110', ( INS_ADD,'add', imm3_rn_rd, 0)), # ADD<c> <Rd>,<Rn>,#<imm3>\n- ('0001111', ( INS_SUB,'sub', imm3_rn_rd, 0)), # SUB<c> <Rd>,<Rn>,#<imm3>\n- ('00100', ( INS_MOV,'mov', imm8_rd, 0)), # MOV<c> <Rd>,#<imm8>\n+ ('0001100', ( INS_ADD,'add', rm_rn_rd, IF_PSR_S)), # ADD<c> <Rd>,<Rn>,<Rm>\n+ ('0001101', ( INS_SUB,'sub', rm_rn_rd, IF_PSR_S)), # SUB<c> <Rd>,<Rn>,<Rm>\n+ ('0001110', ( INS_ADD,'add', imm3_rn_rd, IF_PSR_S)), # ADD<c> <Rd>,<Rn>,#<imm3>\n+ ('0001111', ( INS_SUB,'sub', imm3_rn_rd, IF_PSR_S)), # SUB<c> <Rd>,<Rn>,#<imm3>\n+ ('00100', ( INS_MOV,'mov', imm8_rd, IF_PSR_S)), # MOV<c> <Rd>,#<imm8>\n('00101', ( INS_CMP,'cmp', imm8_rd, 0)), # CMP<c> <Rn>,#<imm8>\n- ('00110', ( INS_ADD,'add', imm8_rd, 0)), # ADD<c> <Rdn>,#<imm8>\n- ('00111', (INS_SUB,'sub', imm8_rd, 0)), # SUB<c> <Rdn>,#<imm8>\n+ ('00110', ( INS_ADD,'add', imm8_rd, IF_PSR_S)), # ADD<c> <Rdn>,#<imm8>\n+ ('00111', (INS_SUB,'sub', imm8_rd, IF_PSR_S)), # SUB<c> <Rdn>,#<imm8>\n# Data processing instructions\n- ('0100000000', (INS_AND,'and', rm_rdn, 0)), # AND<c> <Rdn>,<Rm>\n- ('0100000001', (INS_EOR,'eor', rm_rdn, 0)), # EOR<c> <Rdn>,<Rm>\n- ('0100000010', (INS_LSL,'lsl', rm_rdn, 0)), # LSL<c> <Rdn>,<Rm>\n- ('0100000011', (INS_LSR,'lsr', rm_rdn, 0)), # LSR<c> <Rdn>,<Rm>\n- ('0100000100', (INS_ASR,'asr', rm_rdn, 0)), # ASR<c> <Rdn>,<Rm>\n- ('0100000101', (INS_ADC,'adc', rm_rdn, 0)), # ADC<c> <Rdn>,<Rm>\n- ('0100000110', (INS_SBC,'sbc', rm_rdn, 0)), # SBC<c> <Rdn>,<Rm>\n- ('0100000111', (INS_ROR,'ror', rm_rdn, 0)), # ROR<c> <Rdn>,<Rm>\n+ ('0100000000', (INS_AND,'and', rm_rdn, IF_PSR_S)), # AND<c> <Rdn>,<Rm>\n+ ('0100000001', (INS_EOR,'eor', rm_rdn, IF_PSR_S)), # EOR<c> <Rdn>,<Rm>\n+ ('0100000010', (INS_LSL,'lsl', rm_rdn, IF_PSR_S)), # LSL<c> <Rdn>,<Rm>\n+ ('0100000011', (INS_LSR,'lsr', rm_rdn, IF_PSR_S)), # LSR<c> <Rdn>,<Rm>\n+ ('0100000100', (INS_ASR,'asr', rm_rdn, IF_PSR_S)), # ASR<c> <Rdn>,<Rm>\n+ ('0100000101', (INS_ADC,'adc', rm_rdn, IF_PSR_S)), # ADC<c> <Rdn>,<Rm>\n+ ('0100000110', (INS_SBC,'sbc', rm_rdn, IF_PSR_S)), # SBC<c> <Rdn>,<Rm>\n+ ('0100000111', (INS_ROR,'ror', rm_rdn, IF_PSR_S)), # ROR<c> <Rdn>,<Rm>\n('0100001000', (INS_TST,'tst', rm_rd, 0)), # TST<c> <Rn>,<Rm>\n- ('0100001001', (INS_RSB,'rsb', rm_rd_imm0, 0)), # RSB<c> <Rd>,<Rn>,#0\n+ ('0100001001', (INS_RSB,'rsb', rm_rd_imm0, IF_PSR_S)), # RSB<c> <Rd>,<Rn>,#0\n('0100001010', (INS_CMP,'cmp', rm_rd, 0)), # CMP<c> <Rn>,<Rm>\n('0100001011', (INS_CMN,'cmn', rm_rd, 0)), # CMN<c> <Rn>,<Rm>\n- ('0100001100', (INS_ORR,'orr', rm_rdn, 0)), # ORR<c> <Rdn>,<Rm>\n- ('0100001101', (INS_MUL,'mul', rn_rdm, 0)), # MUL<c> <Rdm>,<Rn>,<Rdm>\n+ ('0100001100', (INS_ORR,'orr', rm_rdn, IF_PSR_S)), # ORR<c> <Rdn>,<Rm>\n+ ('0100001101', (INS_MUL,'mul', rn_rdm, IF_PSR_S)), # MUL<c> <Rdm>,<Rn>,<Rdm>\n('0100001110', (INS_BIC,'bic', rm_rdn, 0)), # BIC<c> <Rdn>,<Rm>\n('0100001111', (INS_MVN,'mvn', rm_rd, 0)), # MVN<c> <Rd>,<Rm>\n# Special data in2tructions and branch and exchange\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
thumb decoding bugfixes: mcr/mrc, dp, etc...
|
718,770 |
29.09.2017 23:13:22
| 14,400 |
d055d7289ac77a3c5c3b4c8c0e0635ec55b91294
|
ArmImmOffsetOper render bugfix
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -4558,7 +4558,7 @@ class ArmImmOffsetOper(ArmOperand):\nif idxing == 0x10:\nmcanv.addText(']')\n- elif idxing != 0:\n+ elif idxing &0x10 != 0:\nmcanv.addText(']!')\ndef repr(self, op):\n@@ -4568,10 +4568,7 @@ class ArmImmOffsetOper(ArmOperand):\nif self.base_reg == REG_PC:\naddr = self.getOperAddr(op) # only works without an emulator because we've already verified base_reg is PC\ntname = \"[#0x%x]\" % addr\n- # FIXME: is there any chance of us doing indexing on PC?!?\n- # ldcl literal trips this in some cases\n- #if idxing != 0x2:\n- #print \"OMJ! WRITING to the program counter!\"\n+\nelse:\npom = ('-','')[u]\nif self.offset != 0:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
ArmImmOffsetOper render bugfix
|
718,770 |
09.12.2017 10:21:01
| 18,000 |
31443d585f35d6b4ab7cd32f3be40a8db8a796ca
|
minor tweaks, about to get serious about finding the funcgraph bugs
|
[
{
"change_type": "MODIFY",
"old_path": "envi/qt/memcanvas.py",
"new_path": "envi/qt/memcanvas.py",
"diff": "@@ -203,8 +203,8 @@ class VQMemoryCanvas(e_memcanvas.MemoryCanvas, QtWebKitWidgets.QWebView):\ninitMemSendtoMenu('0x%.8x' % va, menu)\ndef _menuSaveToHtml(self):\n- fname = QtWidgets.QFileDialog.getSaveFileName(self, 'Save As HTML...')[0]\n- if fname != None:\n+ fname, ftype = QtWidgets.QFileDialog.getSaveFileName(self, 'Save As HTML...')\n+ if fname != None and len(fname):\nhtml = self.page().mainFrame().toHtml()\nfile(fname, 'w').write(html)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -15,7 +15,7 @@ import vivisect.qt.ctxmenu as vq_ctxmenu\nimport vivisect.tools.graphutil as viv_graphutil\nfrom PyQt5.QtCore import pyqtSignal, QPoint\n-from PyQt5 import QtCore, QtGui, QtWebKit\n+from PyQt5 import QtCore, QtGui, QtWidgets, QtWebKit\nfrom vqt.main import idlethread, idlethreadsync, eatevents, vqtconnect, workthread, vqtevent\nfrom vqt.common import *\n@@ -91,7 +91,7 @@ class VQVivFuncgraphCanvas(vq_memory.VivCanvasBase):\nmenu = QtWidgets.QMenu(parent=self)\nself.viewmenu = menu.addMenu('view ')\n- self.viewmenu.addAction(\"Save frame to HTML\", ACT(self._menuSaveToHtml))\n+ #self.viewmenu.addAction(\"Save frame to HTML\", ACT(self._menuSaveToHtml))\nself.viewmenu.addAction(\"Refresh\", ACT(self.refresh))\nself.viewmenu.addAction(\"Paint Up\", ACT(self.paintUp.emit))\nself.viewmenu.addAction(\"Paint Down\", ACT(self.paintDown.emit))\n@@ -425,14 +425,10 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QtWidg\ncbva = nprops.get('cbva')\ncbname = 'codeblock_%.8x' % cbva\n- w = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname)\n- if w == None:\n- continue\n- girth, ok = w\n- h = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname)\n- if h == None:\n- continue\n- height, ok = h\n+ #girth, ok = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname).toInt()\n+ girth = int(frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname))\n+ #height, ok = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname).toInt()\n+ height = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname)\nself.graph.setNodeProp((nid,nprops), \"size\", (girth, height))\nself.dylayout = vg_dynadag.DynadagLayout(self.graph)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -216,7 +216,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nstate = settings.value('%s/DockState' % guid)\ngeom = settings.value('%s/DockGeometry' % guid)\n- if dwcls == None:\n+ if dwcls == None or not len(dwcls):\nnames = self.vw.filemeta.keys()\nnames.sort()\nname = '+'.join(names)\n@@ -224,17 +224,17 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nstate = settings.value('%s/DockState' % name)\ngeom = settings.value('%s/DockGeometry' % name)\n- if dwcls == None:\n+ if dwcls == None or not len(dwcls):\ndwcls = settings.value('DockClasses')\nstate = settings.value('DockState')\ngeom = settings.value('DockGeometry')\n- if not dwcls == None:\n+ if dwcls != None and len(dwcls):\nfor i, clsname in enumerate(dwcls):\nname = 'VQDockWidget%d' % i\ntry:\n- tup = self.vqBuildDockWidget(str(clsname), floating=True)\n+ tup = self.vqBuildDockWidget(str(clsname)) # FIXME:, floating=True)\nif tup != None:\nd, obj = tup\nd.setObjectName(name)\n@@ -302,7 +302,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndef _menuFileSaveAs(self):\nfname = QtWidgets.QFileDialog.getSaveFileName(self, 'Save As...')[0]\n- if fname == None:\n+ if fname == None or not len(fname):\nreturn\nself.vw.setMeta('StorageName', fname)\nself._menuFileSave(fullsave=True)\n@@ -320,7 +320,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndef _menuViewLayoutsSave(self):\nfname = QtWidgets.QFileDialog.getSaveFileName(self, 'Save Layout')[0]\n- if fname == None:\n+ if fname == None or not len(fname):\nreturn\nsettings = QtCore.QSettings(fname, QtCore.QSettings.IniFormat)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "@@ -18,7 +18,7 @@ import vivisect.qt.views as viv_q_views\nimport vivisect.qt.ctxmenu as viv_q_ctxmenu\nimport vivisect.qt.funcviews as viv_q_funcviews\n-from PyQt5 import QtCore, QtGui, QtWebKit\n+from PyQt5 import QtCore, QtGui, QtWidgets, QtWebKit\nfrom envi.threads import firethread\nfrom vqt.main import *\n@@ -295,7 +295,10 @@ class VQVivMemoryCanvas(VivCanvasBase):\nsbmin = frame.scrollBarMinimum(qt_vertical)\nsbmax = frame.scrollBarMaximum(qt_vertical)\n- if sbcur == sbmax:\n+ if not len(self._canv_rendvas):\n+ pass\n+\n+ elif sbcur == sbmax:\nlastva, lastsize = self._canv_rendvas[-1]\nmapva, mapsize, mperm, mfname = self.vw.getMemoryMap(lastva)\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/qt.py",
"new_path": "vtrace/qt.py",
"diff": "@@ -32,6 +32,7 @@ class VQTraceNotifier(vtrace.Notifier):\ndef __init__(self, trace=None):\nself.trace = trace\nvtrace.Notifier.__init__(self)\n+ if trace != None:\nself.trace.registerNotifier(NOTIFY_ALL, self)\n@idlethreadsync\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
minor tweaks, about to get serious about finding the funcgraph bugs
|
718,770 |
09.12.2017 10:44:55
| 18,000 |
6bd3cc8ec0b1276a4f5b1fdb508c2c0f88189057
|
funcgraph works again. stupid me, turning the isNull() to ==None for the one time it's a problem.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "import vqt.hotkeys as vq_hotkey\n-from PyQt5.QtWidgets import *\nimport vqt.saveable as vq_save\nimport envi.qt.memory as e_mem_qt\nimport envi.memcanvas as e_memcanvas\n@@ -72,7 +71,7 @@ class VQVivFuncgraphCanvas(vq_memory.VivCanvasBase):\ncanvelem = frame.findFirstElement('#memcanvas')\nelem = frame.findFirstElement('#codeblock_%.8x' % va)\n- if elem == None:\n+ if elem.isNull():\n# Lets add a codeblock element for this\ncanvelem.appendInside('<div class=\"codeblock\" id=\"codeblock_%.8x\"></div>' % va)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
funcgraph works again. stupid me, turning the isNull() to ==None for the one time it's a problem.
|
718,770 |
30.12.2017 19:41:09
| 18,000 |
13f31b16b56cb6b7f769d0238871f4064715ccbf
|
bugfix: thumb32 blx offset
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -449,13 +449,19 @@ def branch_misc(va, val, val2): # bl and misc control\nj2 = not ((val2>>11)&1 ^ s)\nimm = (s<<24) | (j1<<23) | (j2<<22) | ((val&0x3ff) << 12) | ((val2&0x7ff) << 1)\n- #imm += 2 # why is this necessary?\n#sign extend a 25-bit number\nif s:\nimm |= 0xff000000\n- oper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va&0xfffffffe)\n+ vamask = (\n+ 0xfffffffc,\n+ 0xfffffffe\n+ )\n+\n+ va &= vamask[notx]\n+\n+ oper0 = ArmPcOffsetOper(e_bits.signed(imm,4), va=va)\nreturn COND_AL, opcode, mnem, (oper0, ), flags, 0\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: thumb32 blx offset
|
718,770 |
02.02.2018 13:02:48
| 18,000 |
c3fa6d37de60b8b47dc8cbaa2b18cfe5e80c5adb
|
walkTree depth correction, and plumbing 'once' through constraints and effects
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/common.py",
"new_path": "vivisect/symboliks/common.py",
"diff": "@@ -319,6 +319,7 @@ class SymbolikBase:\n# let's get into the minds of our kids...\ncur = kid\nidx = 0\n+ continue\n#else:\n# sys.stdout.write('.')\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/constraints.py",
"new_path": "vivisect/symboliks/constraints.py",
"diff": "@@ -21,9 +21,9 @@ class Constraint:\nself._v1.clearCache()\nself._v2.clearCache()\n- def walkTree(self, cb, ctx=None):\n- self._v1 = self._v1.walkTree(cb, ctx=ctx)\n- self._v2 = self._v2.walkTree(cb, ctx=ctx)\n+ def walkTree(self, cb, ctx=None, once=True):\n+ self._v1 = self._v1.walkTree(cb, ctx=ctx, once=once)\n+ self._v2 = self._v2.walkTree(cb, ctx=ctx, once=once)\ndef getWidth(self):\nreturn self._v1.getWidth()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/effects.py",
"new_path": "vivisect/symboliks/effects.py",
"diff": "@@ -23,7 +23,7 @@ class SymbolikEffect:\ndef reduce(self, emu=None):\nraise Exception('%s must implement reduce()!' % (self.__class__.__name__))\n- def walkTree(self, cb, ctx=None):\n+ def walkTree(self, cb, ctx=None, once=True):\nraise Exception('%s must implement walkTree()!' % (self.__class__.__name__))\ndef applyEffect(self, emu):\n@@ -61,7 +61,7 @@ class DebugEffect(SymbolikEffect):\nreturn True\n- def walkTree(self, cb, ctx=None):\n+ def walkTree(self, cb, ctx=None, once=True):\npass\ndef reduce(self, emu=None):\n@@ -102,8 +102,8 @@ class SetVariable(SymbolikEffect):\nreturn True\n- def walkTree(self, cb, ctx=None):\n- self.symobj = self.symobj.walkTree(cb, ctx=ctx)\n+ def walkTree(self, cb, ctx=None, once=True):\n+ self.symobj = self.symobj.walkTree(cb, ctx=ctx, once=once)\ndef reduce(self, emu=None):\nself.symobj = self.symobj.reduce(emu=emu)\n@@ -146,9 +146,9 @@ class ReadMemory(SymbolikEffect):\nreturn True\n- def walkTree(self, cb, ctx=None):\n- self.symaddr = self.symaddr.walkTree(cb, ctx=ctx)\n- self.symsize = self.symsize.walkTree(cb, ctx=ctx)\n+ def walkTree(self, cb, ctx=None, once=True):\n+ self.symaddr = self.symaddr.walkTree(cb, ctx=ctx, once=once)\n+ self.symsize = self.symsize.walkTree(cb, ctx=ctx, once=once)\ndef reduce(self, emu=None):\nself.symaddr = self.symaddr.reduce(emu=emu)\n@@ -191,10 +191,10 @@ class WriteMemory(SymbolikEffect):\nreturn True\n- def walkTree(self, cb, ctx=None):\n- self.symval = self.symval.walkTree(cb, ctx=ctx)\n- self.symaddr = self.symaddr.walkTree(cb, ctx=ctx)\n- self.symsize = self.symsize.walkTree(cb, ctx=ctx)\n+ def walkTree(self, cb, ctx=None, once=True):\n+ self.symval = self.symval.walkTree(cb, ctx=ctx, once=once)\n+ self.symaddr = self.symaddr.walkTree(cb, ctx=ctx, once=once)\n+ self.symsize = self.symsize.walkTree(cb, ctx=ctx, once=once)\ndef reduce(self, emu=None):\nself.symaddr = self.symaddr.reduce(emu=emu)\n@@ -245,10 +245,10 @@ class CallFunction(SymbolikEffect):\nreturn True\n- def walkTree(self, cb, ctx=None):\n- self.funcsym = self.funcsym.walkTree(cb, ctx=ctx)\n+ def walkTree(self, cb, ctx=None, once=True):\n+ self.funcsym = self.funcsym.walkTree(cb, ctx=ctx, once=once)\nif self.argsyms != None:\n- self.argsyms = [ a.walkTree(cb,ctx=ctx) for a in self.argsyms ]\n+ self.argsyms = [ a.walkTree(cb,ctx=ctx, once=once) for a in self.argsyms ]\ndef reduce(self, emu=None):\nself.funcsym = self.funcsym.reduce(emu=emu)\n@@ -300,8 +300,8 @@ class ConstrainPath(SymbolikEffect):\nself.addrsym = addrsym\nself.cons = cons\n- def walkTree(self, cb, ctx=None):\n- self.cons.walkTree(cb, ctx=ctx)\n+ def walkTree(self, cb, ctx=None, once=True):\n+ self.cons.walkTree(cb, ctx=ctx, once=once)\ndef reduce(self, emu=None):\nself.addrsym = self.addrsym.reduce(emu=emu)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
walkTree depth correction, and plumbing 'once' through constraints and effects
|
718,770 |
04.02.2018 23:24:28
| 18,000 |
f840d21b1abfa9c89238bb36863bb44d933ee0af
|
modified for correct disassembly.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/crypto/constants.py",
"new_path": "vivisect/analysis/crypto/constants.py",
"diff": "@@ -34,7 +34,14 @@ def analyze(vw):\nfor va, size, funcva in vw.getFunctionBlocks(fva):\nmaxva = va+size\nwhile va < maxva:\n- op = vw.parseOpcode(va)\n+ loctup = vw.getLocation(va)\n+ if loctup == None:\n+ print \"error parsing through function 0x%x at 0x%x\" % (fva, va)\n+ va += 1\n+ continue\n+ lva,lsize,ltype,tinfo = loctup\n+\n+ op = vw.parseOpcode(va, arch=tinfo)\nfor o in op.opers:\nif not o.isImmed():\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
modified for correct disassembly.
|
718,770 |
05.02.2018 00:15:37
| 18,000 |
ba69ec4cb8a075377ae6faa6fa9eaaeb788be674
|
bunch of gui fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/qt/memcanvas.py",
"new_path": "envi/qt/memcanvas.py",
"diff": "@@ -191,7 +191,7 @@ class VQMemoryCanvas(e_memcanvas.MemoryCanvas, QtWebKitWidgets.QWebView):\nva = self._canv_curva\nmenu = QtWidgets.QMenu()\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.initMemWindowMenu(va, menu)\nviewmenu = menu.addMenu('view ')\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/qt/memory.py",
"new_path": "envi/qt/memory.py",
"diff": "@@ -90,7 +90,7 @@ class EnviNavModel(vq_tree.VQTreeModel):\npnode = idx[0].internalPointer()\nexpr = pnode.rowdata[self.navcol]\nmdata = QtCore.QMimeData()\n- mdata.setData('envi/expression',expr)\n+ mdata.setData('envi/expression',str(expr))\nreturn mdata\nclass VQMemoryWindow(vq_hotkey.HotKeyMixin, EnviNavMixin, vq_save.SaveableWidget, QtWidgets.QWidget):\n"
},
{
"change_type": "MODIFY",
"old_path": "vdb/__init__.py",
"new_path": "vdb/__init__.py",
"diff": "@@ -1051,6 +1051,7 @@ class Vdb(e_cli.EnviMutableCli, v_notif.Notifier, v_util.TraceManager):\npc = t.getProgramCounter()\n+ try:\nif pc == taddr:\nbreak\n@@ -1086,6 +1087,9 @@ class Vdb(e_cli.EnviMutableCli, v_notif.Notifier, v_util.TraceManager):\nelif op.iflags & envi.IF_RET:\ndepth -= 1\n+ except Exception, e:\n+ print \"[E@0x%x] %r\" % (pc, e)\n+\ntid = t.getCurrentThread()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -84,7 +84,7 @@ class VQVivFuncgraphCanvas(vq_memory.VivCanvasBase):\nreturn ret\ndef contextMenuEvent(self, event):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nmenu = vq_ctxmenu.buildContextMenu(self.vw, va=self._canv_curva, parent=self)\nelse:\nmenu = QtWidgets.QMenu(parent=self)\n@@ -96,10 +96,6 @@ class VQVivFuncgraphCanvas(vq_memory.VivCanvasBase):\nself.viewmenu.addAction(\"Paint Down\", ACT(self.paintDown.emit))\nself.viewmenu.addAction(\"Paint Down until remerge\", ACT(self.paintMerge.emit))\n- viewmenu = menu.addMenu('view ')\n- viewmenu.addAction(\"Save frame to HTML\", ACT(self._menuSaveToHtml))\n- viewmenu.addAction(\"Refresh\", ACT(self.refresh))\n-\nmenu.exec_(event.globalPos())\ndef _navExpression(self, expr):\n@@ -403,7 +399,12 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QtWidg\nself.fva = fva\n#self.graph = self.vw.getFunctionGraph(fva)\nif graph == None:\n+ try:\ngraph = viv_graphutil.buildFunctionGraph(self.vw, fva, revloop=True)\n+ except Exception, e:\n+ import sys\n+ sys.excepthook(*sys.exc_info())\n+ return\nself.graph = graph\n@@ -507,7 +508,7 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QtWidg\ndef clearText(self):\n# Pop the svg and reset #memcanvas\nframe = self.mem_canvas.page().mainFrame()\n- if self.fva:\n+ if self.fva != None:\nsvgid = '#funcgraph_%.8x' % self.fva\nsvgelem = frame.findFirstElement(svgid)\nsvgelem.removeFromDocument()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "@@ -86,7 +86,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:nextva')\ndef _hotkey_nav_nextva(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nloc = self.vw.getLocation(self._canv_curva)\n@@ -98,7 +98,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:prevva')\ndef _hotkey_nav_prevva(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nloc = self.vw.getPrevLocation(self._canv_curva)\n@@ -109,7 +109,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:nextundef')\ndef _hotkey_nav_nextundef(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nvw = self.vw\n@@ -138,7 +138,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:nav:prevundef')\ndef _hotkey_nav_prevundef(self):\n- if not self._canv_curva:\n+ if self._canv_curva == None:\nreturn\nvw = self.vw\n@@ -167,65 +167,65 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:make:code')\ndef _hotkey_make_code(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeCode(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:function')\ndef _hotkey_make_function(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeFunction(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:string')\ndef _hotkey_make_string(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeString(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:pointer')\ndef _hotkey_make_pointer(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makePointer(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:unicode')\ndef _hotkey_make_unicode(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeUnicode(self._canv_curva)\n@vq_hotkey.hotkey('viv:undefine')\ndef _hotkey_undefine(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.delLocation(self._canv_curva)\n@vq_hotkey.hotkey('viv:setname')\ndef _hotkey_setname(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.getVivGui().setVaName( self._canv_curva, parent=self )\n@vq_hotkey.hotkey('viv:bookmark')\ndef _hotkey_bookmark(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.getVivGui().addBookmark( self._canv_curva, parent=self )\n@vq_hotkey.hotkey('viv:comment')\ndef _hotkey_comment(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.getVivGui().setVaComment( self._canv_curva, parent=self )\n@vq_hotkey.hotkey('viv:make:struct')\ndef _hotkey_make_struct(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nsname = self.vw.getVivGui().makeStruct(self._canv_curva)\nif sname != None:\nself._last_sname = sname\n@vq_hotkey.hotkey('viv:make:struct:again')\ndef _hotkey_make_struct_again(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nif self._last_sname != None:\nself.vw.makeStructure(self._canv_curva, self._last_sname)\n@vq_hotkey.hotkey('viv:make:struct:multi')\ndef _hotkey_make_struct_multi(self, parent=None):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nif self._last_sname != None:\nnumber, ok = QtWidgets.QInputDialog.getText(parent, 'Make Multiple Consecutive Structs', 'Number of Structures')\nif ok:\n@@ -249,27 +249,27 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:make:number:one')\ndef _hotkey_make_number_one(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 1)\n@vq_hotkey.hotkey('viv:make:number:two')\ndef _hotkey_make_number_two(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 2)\n@vq_hotkey.hotkey('viv:make:number:four')\ndef _hotkey_make_number_four(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 4)\n@vq_hotkey.hotkey('viv:make:number:eight')\ndef _hotkey_make_number_eight(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 8)\n@vq_hotkey.hotkey('viv:make:number:sixteen')\ndef _hotkey_make_number_sixteen(self):\n- if self._canv_curva:\n+ if self._canv_curva != None:\nself.vw.makeNumber(self._canv_curva, 16)\n@firethread\n@@ -411,7 +411,7 @@ class VQVivMemoryView(e_mem_qt.VQMemoryWindow, viv_base.VivEventCore):\ndef _viv_xrefsto(self):\n- if self.mem_canvas._canv_curva:\n+ if self.mem_canvas._canv_curva != None:\nxrefs = self.vw.getXrefsTo(self.mem_canvas._canv_curva)\nif len(xrefs) == 0:\nself.vw.vprint('No xrefs found!')\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/views.py",
"new_path": "vivisect/qt/views.py",
"diff": "@@ -255,8 +255,7 @@ class VQVivFunctionsView(VQVivTreeView):\nfva, fmeta = einfo\nself.vivAddFunction(fva)\n- def VWE_DELFUNCTION(self, vw, event, efino):\n- fva, fmeta = einfo\n+ def VWE_DELFUNCTION(self, vw, event, fva):\nself.vivDelRow(fva)\ndef VWE_SETNAME(self, vw, event, einfo):\n@@ -408,7 +407,7 @@ class VQXrefView(VQVivTreeView):\nfor fromva, tova, rtype, rflags in xrefs:\nfva = vw.getFunction(fromva)\nfuncname = ''\n- if fva:\n+ if fva != None:\nfuncname = vw.getName(fva)\nself.vivAddRow(fromva, '0x%.8x' % fromva, rtype, rflags, funcname)\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/tree.py",
"new_path": "vqt/tree.py",
"diff": "@@ -32,6 +32,14 @@ class VQTreeItem(object):\nself.children.append(child)\nreturn child\n+ def delete(self, rowdata):\n+ idx = 0\n+ for child in self.children:\n+ if child.rowdata == rowdata:\n+ return self.children.pop(idx)\n+\n+ idx += 1\n+\ndef child(self, row):\nreturn self.children[row]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bunch of gui fixes
|
718,770 |
14.02.2018 19:51:03
| 18,000 |
180a3628369ab0cfdafb607e6932b4e4f8710909
|
improved logging of errors in crypto constant analysis module
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/crypto/constants.py",
"new_path": "vivisect/analysis/crypto/constants.py",
"diff": "import envi\n+import logging\n+logger = logging.getLogger(__name__)\n+#logger.setLevel(logging.DEBUG)\n+\nfrom vivisect.const import *\n\"\"\"Locate the basic use of known crypto constants\"\"\"\n@@ -36,7 +40,7 @@ def analyze(vw):\nwhile va < maxva:\nloctup = vw.getLocation(va)\nif loctup == None:\n- print \"error parsing through function 0x%x at 0x%x\" % (fva, va)\n+ logger.error(\"error parsing through function 0x%x at 0x%x\" % (fva, va))\nva += 1\ncontinue\nlva,lsize,ltype,tinfo = loctup\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
improved logging of errors in crypto constant analysis module
|
718,770 |
08.03.2018 14:41:31
| 18,000 |
d7544ea230d6dad4566b8aa18d3f50353da4cf3f
|
handle exceptions raised within GUI ACTivities.
|
[
{
"change_type": "MODIFY",
"old_path": "vqt/common.py",
"new_path": "vqt/common.py",
"diff": "+import sys\n+import logging\n+import traceback\n+\n# Some common GUI helpers\nfrom PyQt5 import QtCore, QtGui, QtWidgets\n+logger = logging.getLogger(__name__)\n+#logger.setLevel(logging.DEBUG)\n+if not len(logger.handlers):\n+ logger.addHandler(logging.StreamHandler())\n+\n+\n+\nclass ACT:\ndef __init__(self, meth, *args, **kwargs):\nself.meth = meth\n@@ -8,7 +19,12 @@ class ACT:\nself.kwargs = kwargs\ndef __call__(self):\n+ try:\nreturn self.meth( *self.args, **self.kwargs )\n+ except:\n+ logger.warn(\"error in ACT(%r, %r, %r)\" % (self.meth, self.args, self.kwargs))\n+ logger.debug(''.join(traceback.format_exception(*sys.exc_info())))\n+\nclass VqtModel(QtCore.QAbstractItemModel):\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/hotkeys.py",
"new_path": "vqt/hotkeys.py",
"diff": "+import sys\n+import logging\n+import traceback\n+\n+logger = logging.getLogger(__name__)\n+#logger.setLevel(logging.INFO)\n+if not len(logger.handlers):\n+ logger.addHandler(logging.StreamHandler())\n+\nfrom PyQt5 import QtCore\nfrom PyQt5.QtWidgets import *\n@@ -139,7 +148,12 @@ class HotKeyMixin(object):\ntarget = self._vq_hotkeys.get( hotkey )\nif target != None:\ncallback, args, kwargs = self._vq_hotkey_targets.get( target )\n+ try:\ncallback(*args,**kwargs)\n+ except:\n+ logger.warn(\"error in eatKeyPressEvent(%r, %r, %r)\" % (event, args, kwargs))\n+ logger.debug(''.join(traceback.format_exception(*sys.exc_info())))\n+\nevent.accept()\nreturn True\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
handle exceptions raised within GUI ACTivities.
|
718,770 |
09.03.2018 08:23:06
| 18,000 |
24cf4282dd7855032b3c638c58cb69ea7f98aed8
|
arm/thumb decoding bug-fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1540,11 +1540,11 @@ def p_vmov_scalar(opval, va):\nif op:\nopers = (\nArmRegOper(rt, va),\n- ArmRegScalarOper(rctx.getRegisterIndex('d%d' % vm), index),\n+ ArmRegScalarOper(rctx.getRegisterIndex('d%d' % vd), index),\n)\nelse:\nopers = (\n- ArmRegScalarOper(rctx.getRegisterIndex('d%d' % vm), index),\n+ ArmRegScalarOper(rctx.getRegisterIndex('d%d' % vd), index),\nArmRegOper(rt, va),\n)\n@@ -1569,7 +1569,7 @@ def p_vstm(opval, va): #p1078\nopers = (\nArmRegOper(rn, va, oflags=oflags),\n- ArmExtRegListOper(vn, regsize, op),\n+ ArmExtRegListOper(vd, regsize, op),\n)\nreturn opcode, mnem, opers, flags, simdflags\n@@ -4618,11 +4618,12 @@ class ArmPcOffsetOper(ArmOperand):\ndef render(self, mcanv, op, idx):\nvalue = self.getOperValue(op)\n- if mcanv.mem.isValidPointer(value):\n- name = addrToName(mcanv, value)\n- mcanv.addVaText(name, value)\n+ va = value & -2\n+ if mcanv.mem.isValidPointer(va):\n+ name = addrToName(mcanv, va)\n+ mcanv.addVaText(name, va)\nelse:\n- mcanv.addVaText('0x%.8x' % value, value)\n+ mcanv.addVaText('0x%.8x' % va, va)\ndef repr(self, op):\ntarg = self.getOperValue(op)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -823,13 +823,14 @@ def shift_or_ext_32(va, val1, val2):\nraise InvalidInstruction(mesg=\"shift_or_ext_32 needs to hand off for val2 & 0xf000 != 0xf000 at va 0x%x: val1:%.4x val2:%.4x\" % (va, val1, val2), va=va)\n+ op1 = (val>>4) & 0xf\nop2 = (val2>>4) & 0xf\nrn = (val1 & 0xf)\nrd = (val2 >> 8) & 0xf\nrm = (val2 & 0xf)\nif (op2):\n- if op1 > 6:\n+ if op1 > 5:\nraise InvalidInstruction(\nmesg=\"shift_or_ext_32 parsing an unsupported instruction encoding\",\nbytez=struct.pack(\"<H\", val1)+struct.pack(\"<H\", val2), va=va)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm/thumb decoding bug-fixes
|
718,770 |
09.03.2018 08:25:40
| 18,000 |
9078e244523600e68e9fb0e43a3a5f21fb8f4011
|
arm/thumb emulation enhancements/bug-fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -645,6 +645,15 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setThumbMode(val & 1)\nreturn val & -2\n+ i_ldrb = i_ldr\n+ i_ldrbt = i_ldr\n+ i_ldrd = i_ldr\n+ i_ldrh = i_ldr\n+ i_ldrht = i_ldr\n+ i_ldrsh = i_ldr\n+ i_ldrsb = i_ldr\n+ i_ldrt = i_ldr\n+\ndef i_mov(self, op):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n@@ -687,6 +696,14 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 1, val)\ni_strh = i_str\n+ i_strb = i_str\n+ i_strbt = i_str\n+ i_strd = i_str\n+ i_strh = i_str\n+ i_strsh = i_str\n+ i_strsb = i_str\n+ i_strt = i_str\n+\ndef i_add(self, op):\nif len(op.opers) == 3:\n@@ -763,13 +780,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_bx(self, op):\ntarget = self.getOperValue(op, 0)\nself.setFlag(PSR_T_bit, target & 1)\n- return target\n+ return target & -2\ndef i_blx(self, op):\nself.setRegister(REG_LR, self.getRegister(REG_PC) + len(op))\ntarget = self.getOperValue(op, 0)\nself.setFlag(PSR_T_bit, target & 1)\n- return target\n+ return target & -2\ndef i_svc(self, op):\nsvc = self.getOperValue(op, 0)\n@@ -975,6 +992,34 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_cmps = i_cmp\n+ def i_uxth(self, op):\n+ val = self.getOperValue(op, 1)\n+ self.setOperValue(op, 0, val)\n+\n+ def i_uxtah(self, op):\n+ val = self.getOperValue(op, 2)\n+ val += self.getOperValue(op, 1)\n+\n+ self.setOperValue(op, 0, val)\n+\n+ def i_sxth(self, op):\n+ slen = op.opers[1].tsize\n+ dlen = op.opers[0].tsize\n+\n+ val = self.getOperValue(op, 1)\n+ val = ebits.sign_extend(val, slen, dlen)\n+ self.setOperValue(op, 0, val)\n+\n+ def i_sxtah(self, op):\n+ slen = op.opers[2].tsize\n+ dlen = op.opers[0].tsize\n+\n+ val = self.getOperValue(op, 2)\n+ val = ebits.sign_extend(val, slen, dlen)\n+ val += self.getOperValue(op, 1)\n+\n+ self.setOperValue(op, 0, val)\n+\ndef i_bic(self, op):\ndsize = op.opers[0].tsize\nval = self.getOperValue(op, 1)\n@@ -1210,6 +1255,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n+ def i_cps(self, op):\n+ print(\"CPS: 0x%x %r\" % (op.va, op))\ndef i_pld2(self, op):\nprint(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -172,6 +172,12 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nfor bva,bpath in blist:\ntodo.append((bva, esnap, bpath))\nbreak\n+ else:\n+ # check if we've blx'd to a different thumb state. if so,\n+ # be sure to return to the original tmode before continuing emulation pass\n+ newtmode = self.getFlag(PSR_T_bit)\n+ if newtmode != tmode:\n+ self.setFlag(PSR_T_bit, tmode)\n# If we enounter a procedure exit, it doesn't\n# matter what EIP is, we're done here.\n@@ -182,7 +188,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nexcept envi.UnsupportedInstruction, e:\nif self.strictops:\nif verbose: print 'runFunction breaking after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\n- break\n+ raise e\nelse:\nif verbose: print 'runFunction continuing after unsupported instruction: 0x%08x %s' % (e.op.va, e.op.mnem)\nself.setProgramCounter(e.op.va+ e.op.size)\n@@ -191,7 +197,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif self.emumon != None:\nself.emumon.logAnomaly(self, starteip, str(e))\n- if verbose: print 'runFunction breaking after exception (0x%x): %s' % (e.op.va, e)\n+ if verbose: print 'runFunction breaking after exception (fva: 0x%x): %s' % (funcva, e)\nbreak # If we exc during execution, this branch is dead.\n#except:\n# sys.excepthook(*sys.exc_info())\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm/thumb emulation enhancements/bug-fixes
|
718,770 |
09.03.2018 16:18:10
| 18,000 |
d3d72bc5c63f4c9f54ea34adce75fefe406f992e
|
thumb decode, arm emu bugfixes.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -464,8 +464,14 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn ures\ndef logicalAnd(self, op):\n+ opercnt = len(op.opers)\n+\n+ if opercnt == 3:\nsrc1 = self.getOperValue(op, 1)\nsrc2 = self.getOperValue(op, 2)\n+ else:\n+ src1 = self.getOperValue(op, 0)\n+ src2 = self.getOperValue(op, 1)\n# PDE\nif src1 == None or src2 == None:\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -823,11 +823,12 @@ def shift_or_ext_32(va, val1, val2):\nraise InvalidInstruction(mesg=\"shift_or_ext_32 needs to hand off for val2 & 0xf000 != 0xf000 at va 0x%x: val1:%.4x val2:%.4x\" % (va, val1, val2), va=va)\n- op1 = (val>>4) & 0xf\n+ op1 = (val1>>4) & 0xf\nop2 = (val2>>4) & 0xf\nrn = (val1 & 0xf)\nrd = (val2 >> 8) & 0xf\nrm = (val2 & 0xf)\n+ flags = 0\nif (op2):\nif op1 > 5:\n@@ -870,7 +871,6 @@ def shift_or_ext_32(va, val1, val2):\nelse:\n# lsl/lsr/asr/ror\n- flags = 0\nop1 = (val1>>4) & 0xf\nopcode, mnem, nothing = mov_ris_ops[op1>>1]\n@@ -882,6 +882,7 @@ def shift_or_ext_32(va, val1, val2):\nif (op1 & 1):\nflags |= IF_PSR_S\n+\nreturn COND_AL, opcode, mnem, opers, flags, 0\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
thumb decode, arm emu bugfixes.
|
718,770 |
09.03.2018 18:03:03
| 18,000 |
7ac37340aed9a0b2f5702cfd24713253c531acb8
|
thumb2 ldrb decode bugfix
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1052,6 +1052,8 @@ def ldrb_memhints_32(va, val1, val2):\nopers = (\nArmScaledOffsetOper(rn, rm, S_LSL, imm2, va),\n)\n+ return COND_AL, opcode, mnem, opers, flags, 0\n+\nelse:\n# LDRB (literal)\nopcode, mnem, flags = ldrb_instrs[Sbit]\n@@ -1060,6 +1062,7 @@ def ldrb_memhints_32(va, val1, val2):\nArmRegOper(rt),\nArmPcOffsetOper(imm12, va),\n)\n+ return COND_AL, opcode, mnem, opers, flags, 0\nelse:\nif op1&1:\n@@ -1070,6 +1073,7 @@ def ldrb_memhints_32(va, val1, val2):\nArmRegOper(rt),\nArmImmOffsetOper(rn, imm12, va),\n)\n+ return COND_AL, opcode, mnem, opers, flags, 0\nelif not op1:\nif not op2 and rt == 0xf:\n@@ -1080,6 +1084,7 @@ def ldrb_memhints_32(va, val1, val2):\nopers = (\nArmScaledOffsetOper(rn, rm, S_LSL, imm2, va),\n)\n+ return COND_AL, opcode, mnem, opers, flags, 0\nelif (val2>>11) & 1:\n# LDRB (register)\n@@ -1090,7 +1095,7 @@ def ldrb_memhints_32(va, val1, val2):\nArmRegOper(rt),\nArmImmOffsetOper(rn, imm8, va, pubwl)\n)\n-\n+ return COND_AL, opcode, mnem, opers, flags, 0\nelse:\n# LDRB (register)\n@@ -1101,10 +1106,10 @@ def ldrb_memhints_32(va, val1, val2):\nArmRegOper(rt),\nArmScaledOffsetOper(rn, rm, S_LSL, imm2, va),\n)\n+ return COND_AL, opcode, mnem, opers, flags, 0\n- #else:\n- # raise envi.InvalidInstruction(\n- # mesg=\"ldrb_memhints_32: fall 1\", va=va)\n+ raise envi.InvalidInstruction(\n+ mesg=\"ldrb_memhints_32: fall 1\", va=va)\nreturn COND_AL, opcode, mnem, opers, flags, 0\n@@ -1731,7 +1736,7 @@ thumb_base = [\n('0100001011', (INS_CMN,'cmn', rm_rd, 0)), # CMN<c> <Rn>,<Rm>\n('0100001100', (INS_ORR,'orr', rm_rdn, IF_PSR_S)), # ORR<c> <Rdn>,<Rm>\n('0100001101', (INS_MUL,'mul', rn_rdm, IF_PSR_S)), # MUL<c> <Rdm>,<Rn>,<Rdm>\n- ('0100001110', (INS_BIC,'bic', rm_rdn, 0)), # BIC<c> <Rdn>,<Rm>\n+ ('0100001110', (INS_BIC,'bic', rm_rdn, IF_PSR_S)), # BIC<c> <Rdn>,<Rm>\n('0100001111', (INS_MVN,'mvn', rm_rd, 0)), # MVN<c> <Rd>,<Rm>\n# Special data in2tructions and branch and exchange\n('0100010000', (INS_ADD,'add', d1_rm4_rd3, 0)), # ADD<c> <Rdn>,<Rm>\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
thumb2 ldrb decode bugfix
|
718,770 |
09.03.2018 18:06:17
| 18,000 |
e6ab12a0615c0b4f3308efe3b0f2fe8d32feb918
|
emulation bugfixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -741,10 +741,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncurmode = self.getProcMode()\nif op.iflags & IF_PSR_S:\n- if op.opers[0].reg == 15 and (curmode != PM_sys and curmode != PM_usr):\n+ if op.opers[0].reg == 15:\n+ if (curmode != PM_sys and curmode != PM_usr):\nself.setCPSR(self.getSPSR(curmode))\nelse:\nraise Exception(\"Messed up opcode... adding to r15 from PM_usr or PM_sys\")\n+\nself.setFlag(PSR_N_bit, e_bits.is_signed(ures, dsize))\nself.setFlag(PSR_Z_bit, not ures)\nself.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, dsize))\n@@ -1028,8 +1030,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_bic(self, op):\ndsize = op.opers[0].tsize\n+ if len(op.opers) == 3:\nval = self.getOperValue(op, 1)\nconst = self.getOperValue(op, 2)\n+ else:\n+ val = self.getOperValue(op, 0)\n+ const = self.getOperValue(op, 1)\n+\nval &= ~const\nself.setOperValue(op, 0, val)\n@@ -1188,48 +1195,48 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn imm32\ndef i_smulbb(self, op):\n- oper1 = op.getOperValue(1) & 0xffff\n- oper2 = op.getOperValue(2) & 0xffff\n+ oper1 = self.getOperValue(op, 1) & 0xffff\n+ oper2 = self.getOperValue(op, 2) & 0xffff\ns1 = e_bits.signed(oper1 & 0xffff, 2)\ns2 = e_bits.signed(oper2 & 0xffff, 2)\nresult = s1 * s2\n- op.setOperValue(0, result)\n+ self.setOperValue(op, 0, result)\ndef i_smultb(self, op):\n- oper1 = op.getOperValue(1) & 0xffff\n- oper2 = op.getOperValue(2) & 0xffff\n+ oper1 = self.getOperValue(op, 1) & 0xffff\n+ oper2 = self.getOperValue(op, 2) & 0xffff\ns1 = e_bits.signed(oper1 >> 16, 2)\ns2 = e_bits.signed(oper2 & 0xffff, 2)\nresult = s1 * s2\n- op.setOperValue(0, result)\n+ self.setOperValue(op, 0, result)\ndef i_smulbt(self, op):\n- oper1 = op.getOperValue(1) & 0xffff\n- oper2 = op.getOperValue(2) & 0xffff\n+ oper1 = self.getOperValue(op, 1) & 0xffff\n+ oper2 = self.getOperValue(op, 2) & 0xffff\ns1 = e_bits.signed(oper1 & 0xffff, 2)\ns2 = e_bits.signed(oper2 >> 16, 2)\nresult = s1 * s2\n- op.setOperValue(0, result)\n+ self.setOperValue(op, 0, result)\ndef i_smultt(self, op):\n- oper1 = op.getOperValue(1) & 0xffff\n- oper2 = op.getOperValue(2) & 0xffff\n+ oper1 = self.getOperValue(op, 1) & 0xffff\n+ oper2 = self.getOperValue(op, 2) & 0xffff\ns1 = e_bits.signed(oper1 >>16, 2)\ns2 = e_bits.signed(oper2 >>16, 2)\nresult = s1 * s2\n- op.setOperValue(0, result)\n+ self.setOperValue(op, 0, result)\ndef i_tb(self, op):\n# TBB and TBH both come here.\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
emulation bugfixes
|
718,770 |
10.03.2018 18:29:38
| 18,000 |
17447b131ddaee79e5c7522ccc3f0b2340d2073f
|
much more statistical data
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -667,8 +667,10 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nreturn stats\ndef printDiscoveredStats(self):\n- disc, undisc = self.getDiscoveredInfo()\n+ disc, undisc, numXrefs, numLocs, numFuncs, numBlocks, numOps, numUnis, numStrings, numNumbers, numPointers, numVtables = self.getDiscoveredInfo()\nself.vprint(\"Percentage of discovered executable surface area: %.1f%% (%s / %s)\" % (disc*100.0/(disc+undisc), disc, disc+undisc))\n+ self.vprint(\" Xrefs/Blocks/Funcs: (%s / %s / %s)\" % (numXrefs, numBlocks, numFuncs))\n+ self.vprint(\" Locs, Ops/Strings/Unicode/Nums/Ptrs/Vtables: (%s: %s / %s / %s / %s / %s / %s)\" % (numLocs, numOps, numStrings, numUnis, numNumbers, numPointers, numVtables))\ndef getDiscoveredInfo(self):\n\"\"\"\n@@ -689,7 +691,19 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nelse:\noff += loc[L_SIZE]\ndisc += loc[L_SIZE]\n- return disc, undisc\n+\n+ numXrefs = len(self.getXrefs())\n+ numLocs = len(self.getLocations())\n+ numFuncs = len(self.getFunctions())\n+ numBlocks = len(self.getCodeBlocks())\n+ numOps = len(self.getLocations(LOC_OP))\n+ numUnis = len(self.getLocations(LOC_UNI))\n+ numStrings = len(self.getLocations(LOC_STRING))\n+ numNumbers = len(self.getLocations(LOC_NUMBER))\n+ numPointers = len(self.getLocations(LOC_POINTER))\n+ numVtables = len(self.getLocations(LOC_VFTABLE))\n+\n+ return disc, undisc, numXrefs, numLocs, numFuncs, numBlocks, numOps, numUnis, numStrings, numNumbers, numPointers, numVtables\ndef getImports(self):\n\"\"\"\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
much more statistical data
|
718,770 |
10.03.2018 18:35:48
| 18,000 |
5156eacaf30dbb4d2c467a38fb346135e715c4ad
|
mild cosmetics
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -679,6 +679,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nnumNumbers,\nnumPointers,\nnumVtables ) = self.getDiscoveredInfo()\n+\nself.vprint(\"Percentage of discovered executable surface area: %.1f%% (%s / %s)\" % (disc*100.0/(disc+undisc), disc, disc+undisc))\nself.vprint(\" Xrefs/Blocks/Funcs: (%s / %s / %s)\" % (numXrefs, numBlocks, numFuncs))\nself.vprint(\" Locs, Ops/Strings/Unicode/Nums/Ptrs/Vtables: (%s: %s / %s / %s / %s / %s / %s)\" % (numLocs, numOps, numStrings, numUnis, numNumbers, numPointers, numVtables))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
mild cosmetics
|
718,770 |
10.03.2018 18:44:53
| 18,000 |
b8d7c9516a35666f639c877f70e229d2d0c3805a
|
arm emulation improvement
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1004,12 +1004,16 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n+ i_ustb = i_uxth\n+\ndef i_uxtah(self, op):\nval = self.getOperValue(op, 2)\nval += self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n+ i_ustab = i_uxtah\n+\ndef i_sxth(self, op):\nslen = op.opers[1].tsize\ndlen = op.opers[0].tsize\n@@ -1018,6 +1022,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = e_bits.sign_extend(val, slen, dlen)\nself.setOperValue(op, 0, val)\n+ i_sxtb = i_sxth\n+\ndef i_sxtah(self, op):\nslen = op.opers[2].tsize\ndlen = op.opers[0].tsize\n@@ -1028,6 +1034,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, val)\n+ i_sxtab = i_sxtah\n+\ndef i_bic(self, op):\ndsize = op.opers[0].tsize\nif len(op.opers) == 3:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm emulation improvement
|
718,770 |
30.03.2018 18:21:29
| 14,400 |
427cf1588b18115b2f2842d2d0cc4ef038ac6137
|
a couple logic bugs in detectUnicode. changed so that the charset-code can be anything but it better be the same thing (instead of 0x00)
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -829,15 +829,17 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n#FIXME this does not detect Unicode...\noffset, bytes = self.getByteDef(va)\n- maxlen = len(bytes) + offset\n+ maxlen = len(bytes) - offset\ncount = 0\n+ charset = bytes[offset + 1]\nwhile count < maxlen:\n# If we hit another thing, then probably not.\n# Ignore when count==0 so detection can check something\n# already set as a location.\nif (count > 0):\nloc = self.getLocation(va+count)\n- if loc and loc[L_LTYPE] == LOC_UNI:\n+ if loc:\n+ if loc[L_LTYPE] == LOC_UNI:\nreturn loc[L_VA] - (va + count) + loc[L_SIZE]\nreturn -1\n@@ -848,7 +850,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n# If it's not null,char,null,char then it's\n# not simple unicode...\n- if ord(c1) != 0:\n+ if c1 != charset:\nreturn -1\n# If we find our null terminator after more\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
a couple logic bugs in detectUnicode. changed so that the charset-code can be anything but it better be the same thing (instead of 0x00)
|
718,770 |
30.03.2018 18:48:47
| 14,400 |
aaa24250ac08d7bc097c18b769bebf4128f3f176
|
lots of updates to disasm and emu. IT needs work.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1439,7 +1439,7 @@ def p_swint(opval, va):\nopcode = INS_SVC\nreturn (opcode, \"svc\", olist, 0, 0)\n-def p_vmov_single(opval, va):\n+def p_vmov_single(opval, va): # p944\nop = (val >> 20) & 1\nn = (opval >> 7) & 1\n@@ -1460,7 +1460,7 @@ def p_vmov_single(opval, va):\n)\nreturn opcode, mnem, opers, 0, 0\n-def p_vmov_2single(opval, va): # p944\n+def p_vmov_2single(opval, va): # p944 (946?)\nop = (val >> 20) & 1\nrt2 = (opval >> 16) & 0xf\n@@ -4789,7 +4789,7 @@ class ArmExtRegListOper(ArmOperand):\nreturn True\ndef isDeref(self):\n- return True\n+ return False\ndef render(self, mcanv, op, idx):\nregbase = (\"s%d\", \"d%d\")[self.size]\n@@ -4842,6 +4842,12 @@ class ArmExtRegListOper(ArmOperand):\ns.append('}')\nreturn \"\".join(s)\n+ def getRegCount(self):\n+ return self.count\n+\n+ def getRegSize(self):\n+ return (4, 8)[self.size]\n+\naif_flags = (None, 'f','i','if','a','af','ai','aif')\nclass ArmPSRFlagsOper(ArmOperand):\ndef __init__(self, flags):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -139,6 +139,11 @@ MSB_FMT_SIGNED = [0, 'b', '>h', 0, '>i', 0, 0, 0, '>q',]\nclass ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef __init__(self):\n+ # if-then placeholders\n+ self.itva = None\n+ self.itflags = None\n+ self.itcount = None\n+\n# FIXME: this should be None's, and added in for each real coproc... but this will work for now.\nself.coprocs = [CoProcEmulator(x) for x in xrange(16)]\nself.int_handlers = [self.default_int_handler for x in range(100)]\n@@ -221,14 +226,22 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ntry:\nself.setMeta('forrealz', True)\nx = None\n- #if op.prefixes >= 0xe or conditionals[op.prefixes](self.getRegister(REG_FLAGS)>>28):\n+ skip = False\n+\n+ # IT block handling\n+ if self.itcount:\n+ self.itcount -= 1\n+ print \"untested IT functionality\"\n+ if not (self.itflags & 1):\n+ skip = True\n+ # standard conditional handling\ncondval = (op.prefixes >= 0xe)\nif not condval:\ncondcheck = conditionals[op.prefixes]\ncondval = condcheck(self.getRegister(REG_FLAGS))\n- if condval:\n+ if condval and not skip:\nmeth = self.op_methods.get(op.mnem, None)\nif meth == None:\nraise envi.UnsupportedInstruction(self, op)\n@@ -268,6 +281,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n'''\nreturn self._rctx_vals[REG_CPSR]\n+ def getAPSR(self):\n+ '''\n+ return the Current Program Status Register.\n+ '''\n+ apsr = self.getCPSR() & REG_APSR_MASK\n+ return apsr\n+\ndef setCPSR(self, psr, mask=0xffffffff):\n'''\nset the CPSR for the current ARM processor mode\n@@ -275,6 +295,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\npsr = self._rctx_vals[REG_CPSR] & (~mask) | (psr & mask)\nself._rctx_vals[REG_CPSR] = psr\n+ def setAPSR(self, psr):\n+ '''\n+ set the CPSR for the current ARM processor mode\n+ '''\n+ self.setCPSR(psr, mask=0xffff0000)\n+\ndef getSPSR(self, mode):\n'''\nget the SPSR for the given ARM processor mode\n@@ -578,6 +604,92 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_stmia = i_stm\ni_push = i_stmia\n+ def i_vpush(self, op):\n+ oper = op.opers[0]\n+ tsize = oper.getRegSize()\n+ reglist = oper.getOperValue(op, self)\n+\n+ for reg in reglist:\n+ sp = self.getRegister(REG_SP)\n+ sp -= tsize\n+ self.writeMemValue(sp, reg, tsize)\n+ self.setRegister(REG_SP, sp)\n+\n+ def i_vpop(self, op):\n+ oper = op.opers[0]\n+ tsize = oper.getRegSize()\n+\n+ reglist = []\n+ for ridx in range(oper.getRegCount()):\n+ sp = self.getRegister(REG_SP)\n+ val = self.readMemValue(sp, 4)\n+ reglist.append(val)\n+ self.setRegister(REG_SP, sp+4)\n+\n+ oper.setOperValue(op, reglist, self)\n+\n+ def i_vldm(self, op):\n+ if len(op.opers) == 2:\n+ srcreg = op.opers[0].reg\n+ updatereg = op.opers[0].oflags & OF_W\n+ addr = self.getOperValue(op,0)\n+ flags = op.iflags\n+ else:\n+ srcreg = REG_SP\n+ updatereg = 1\n+ addr = self.getStackCounter()\n+ flags = IF_DAIB_I\n+\n+ pc = self.getRegister(REG_PC) # store for later check\n+\n+ # set up\n+ reglistoper = op.opers[1]\n+ count = reglistoper.getRegCount()\n+ size = reglistoper.getRegSize()\n+\n+ # do multiples based on base and count. unlike ldm, these must be consecutive\n+ if flags & IF_DAIB_I == IF_DAIB_I:\n+ for reg in xrange(count):\n+ regval = self.readMemValue(addr, size)\n+ self.setRegister(reg, regval)\n+ addr += size\n+ else:\n+ for reg in xrange(count-1, -1, -1):\n+ addr -= size\n+ regval = self.readMemValue(addr, size)\n+ self.setRegister(reg, regval)\n+\n+ if updatereg:\n+ self.setRegister(srcreg,addr)\n+ #FIXME: add \"shared memory\" functionality? prolly just in ldrex which will be handled in i_ldrex\n+ # is the following necessary?\n+ newpc = self.getRegister(REG_PC) # check whether pc has changed\n+ if pc != newpc:\n+ self.setThumbMode(newpc & 1)\n+ return newpc\n+\n+ def i_vmov(self, op):\n+ if len(op.opers) == 2:\n+ if isinstance(ArmImmOper, op.opers[1]):\n+ # immediate version copies immediate into each element (Q=2 elements, D=1)\n+ print \"vmov: immediate\"\n+\n+ # vreg to vreg: 1 to 1 copy\n+ # core reg to vreg\n+ # vret to core reg\n+ # core reg to single\n+ # 2 core reg to 2 singles\n+ elif len(op.opers) == 4:\n+ src1 = self.getOperValue(op, 2)\n+ src2 = self.getOperValue(op, 3)\n+ self.setOperValue(op, 0, src1)\n+ self.setOperValue(op, 1, src2)\n+\n+ # 2 core reg to double\n+ #\n+ raise Exception(\"implement me: vmov\")\n+\n+\ndef i_ldm(self, op):\nif len(op.opers) == 2:\nsrcreg = op.opers[0].reg\n@@ -603,25 +715,15 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif flags & IF_DAIB_I == IF_DAIB_I:\nfor reg in xrange(16):\nif (1<<reg) & regmask:\n- if flags & IF_DAIB_B == IF_DAIB_B:\n- addr += 4\n- regval = self.readMemValue(addr, 4)\n- self.setRegister(reg, regval)\n- else:\nregval = self.readMemValue(addr, 4)\nself.setRegister(reg, regval)\naddr += 4\nelse:\nfor reg in xrange(15, -1, -1):\nif (1<<reg) & regmask:\n- if flags & IF_DAIB_B == IF_DAIB_B:\naddr -= 4\nregval = self.readMemValue(addr, 4)\nself.setRegister(reg, regval)\n- else:\n- regval = self.readMemValue(addr, 4)\n- self.setRegister(reg, regval)\n- addr -= 4\nif updatereg:\nself.setRegister(srcreg,addr)\n@@ -690,6 +792,86 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_msr = i_mov\ni_adr = i_mov\n+ def i_vmsr(self, op):\n+ if len(op.opers) == 1:\n+ val = self.getOperValue(op, 0)\n+ else:\n+ val = self.getOperValue(op, 1)\n+\n+ self.setRegister(REG_FPSCR, val)\n+\n+ #def i_vmrs(self, op):\n+ #val = self.getRegister(REG_FPSCR)\n+ #\n+ #if len(op.opers) == 1:\n+ #self.setOperValue(op, 0, val)\n+ #else:\n+ #self.setOperValue(op, 1, val)\n+\n+ def i_mrs(self, op):\n+ val = self.getAPSR()\n+ self.setOperValue(op, 0, val)\n+\n+ def i_vmrs(self, op):\n+ src = self.getRegister(REG_FPSCR)\n+\n+ if op.opers[0].reg != 15:\n+ self.setOperValue(op, 0, src)\n+ else:\n+ apsr = self.getAPSR() & 0x0fffffff\n+ apsr |= (src | 0xf0000000)\n+ self.setOperValue(op, 0, apsr)\n+\n+ def i_it(self, op):\n+ if self.itcount:\n+ raise Exception(\"IT block within an IT block!\")\n+\n+ oper = op.opers[0]\n+ self.itva = op.va\n+ self.itcount = oper.getCondInstrCount()\n+ self.itflags = oper.getFlags()\n+ print \"IT flags need to be set such that each bit means YES or NO\"\n+\n+\n+ def i_bfi(self, op):\n+ lsb = self.getOperValue(op, 2)\n+ width = self.getOperValue(op, 3)\n+ mask = e_bits.b_masks[width]\n+\n+ addit = self.getOperValue(op, 1) & mask\n+ print lsb, width, bin(mask), bin(addit)\n+\n+ mask <<= lsb\n+ val = self.getOperValue(op, 0) & ~mask\n+ val |= addit\n+ print bin(mask), bin(val)\n+\n+ self.setOperValue(op, 0, val)\n+\n+ def i_bfc(self, op):\n+ lsb = self.getOperValue(op, 1)\n+ width = self.getOperValue(op, 2)\n+ mask = e_bits.b_masks[width] << lsb\n+ mask ^= 0xffffffff\n+ print lsb, width, bin(mask)\n+\n+ val = self.getOperValue(op, 0) & mask\n+ print bin(mask), bin(val)\n+\n+ self.setOperValue(op, 0, val)\n+\n+\n+ def i_clz(self, op):\n+ oper = self.getOperValue(op, 1)\n+ bsize = op.opers[1].tsize * 8\n+ lzcnt = 0\n+ for x in range(tsize):\n+ if oper & 0x80000000:\n+ break\n+ lzcnt += 1\n+\n+ self.setOperValue(op, 0, lzcnt)\n+\ndef i_mvn(self, op):\nval = self.getOperValue(op, 1)\nval ^= 0xffffffff\n@@ -1004,7 +1186,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nval = self.getOperValue(op, 1)\nself.setOperValue(op, 0, val)\n- i_ustb = i_uxth\n+ i_uxtb = i_uxth\ndef i_uxtah(self, op):\nval = self.getOperValue(op, 2)\n@@ -1012,7 +1194,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, val)\n- i_ustab = i_uxtah\n+ i_uxtab = i_uxtah\ndef i_sxth(self, op):\nslen = op.opers[1].tsize\n@@ -1333,14 +1515,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_dsb = i_nop\ni_isb = i_nop\n- def i_vmrs(self, op):\n- src = self.getRegister(REG_FPSCR)\n- if op.opers[0].reg != 15:\n- self.setOperValue(op, 0, src)\n- else:\n- apsr = self.getCPSR() & 0x0fffffff\n- apsr |= (src | 0xf0000000)\n- self.setOperValue(op, 0, apsr)\n#TODO: IT EQ\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/regs.py",
"new_path": "envi/archs/arm/regs.py",
"diff": "@@ -38,6 +38,7 @@ arm_metas = [\n(\"r15\", REG_PC, 0, 32),\n]\n+REG_APSR_MASK = 0xffff0000\n# build a translation table to allow for fast access of banked registers\nmodes = proc_modes.keys()\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -564,6 +564,24 @@ class ThumbITOper(ArmOperand):\nself.mask = mask\nself.firstcond = firstcond\n+ def getCondInstrCount(self):\n+ mask = self.mask\n+ for x in range(4, 0, -1):\n+ if mask & 1:\n+ break\n+ mask >>= 1\n+ return x\n+\n+ def getFlags(self):\n+ fiz = self.firstcond & 1\n+ flags = 1\n+ count = self.getCondInstrCount()\n+ for x in range(1, count):\n+ print x, bin(flags)\n+ flags |= ((((self.mask>>(4-x))&1) == fiz) << (x+1))\n+\n+ return flags\n+\ndef repr(self, op):\nmask = self.mask\ncond = self.firstcond\n@@ -942,6 +960,54 @@ def dp_bin_imm_32(va, val1, val2): # p232\nreturn COND_AL, None, None, opers, flags, 0\n+def dp_bfi_imm_32(va, val1, val2): # p232\n+ flags = IF_THUMB32\n+ if val2 & 0x8000:\n+ return branch_misc(va, val1,val2)\n+\n+ Rd = (val2 >> 8) & 0xf\n+\n+ imm4 = val1 & 0xf\n+ i = (val1 >> 10) & 1\n+ imm3 = (val2 >> 12) & 0x7\n+ const = val2 & 0xff\n+\n+ op = (val1>>4) & 0x1f\n+ const |= (imm4 << 12) | (i << 11) | (imm3 << 8)\n+\n+ oper0 = ArmRegOper(Rd)\n+ oper2 = ArmImmOper(const)\n+\n+ if op in (0b00100, 0b01100): # movw, movt\n+ return COND_AL, None, None, (oper0, oper2), 0, 0\n+\n+ Rn = val1 & 0xf\n+ if Rn==15:\n+ if op in (0,0b1010): # add/sub\n+ # adr\n+ return COND_AL, None, 'adr', (oper0, oper2), None, 0\n+\n+ oper1 = ArmRegOper(Rn)\n+\n+ if op == 0b10110:\n+ imm2 = (val2>>6) & 0x3\n+ msb = val2 & 0x1f\n+ lsb = (imm3<<2) | imm2\n+ width = msb - lsb + 1\n+\n+ if Rn == 15:\n+ # bfc\n+ mnem = 'bfc'\n+ opers = (oper0, ArmImmOper(lsb), ArmImmOper(width))\n+ else:\n+ # bfi\n+ mnem = 'bfi'\n+ opers = (oper0, oper1, ArmImmOper(lsb), ArmImmOper(width))\n+\n+ return COND_AL, None, mnem, opers, None, 0\n+\n+ return COND_AL, None, None, (oper0, oper1, oper2), flags, 0\n+\ndef ldm_reg_mode_32(va, val1, val2):\nrn = val1 & 0xf\n@@ -1944,7 +2010,7 @@ thumb2_extension = [\n('11110011000', (85,'ssat', dp_bin_imm_32, IF_THUMB32)),\n('11110011001', (85,'ssat16', dp_bin_imm_32, IF_THUMB32)),\n('11110011010', (85,'sbfx', dp_bin_imm_32, IF_THUMB32)),\n- ('11110011011', (85,'bfi', dp_bin_imm_32, IF_THUMB32)), # bfc if rn=1111\n+ ('11110011011', (85,'bfi', dp_bfi_imm_32, IF_THUMB32)), # bfc if rn=1111\n('11110011100', (85,'usat', dp_bin_imm_32, IF_THUMB32)),\n('111100111010', (85,'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n('111100111011', (85,'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n@@ -1956,7 +2022,7 @@ thumb2_extension = [\n('11110111000', (85,'ssat', dp_bin_imm_32, IF_THUMB32)),\n('11110111001', (85,'ssat16', dp_bin_imm_32, IF_THUMB32)),\n('11110111010', (85,'sbfx', dp_bin_imm_32, IF_THUMB32)),\n- ('11110111011', (85,'bfi', dp_bin_imm_32, IF_THUMB32)), # bfc if rn=1111\n+ ('11110111011', (85,'bfi', dp_bfi_imm_32, IF_THUMB32)), # bfc if rn=1111\n('11110111100', (85,'usat', dp_bin_imm_32, IF_THUMB32)),\n('11110111101', (85,'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n('11110111110', (85,'ubfx', ubfx_32, IF_THUMB32)),\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -86,7 +86,8 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nexcept Exception, e:\n# FIXME: make raise Exception?\n- print \"0x%x: ERROR: %s\" % (op.va, e)\n+ print \"0x%x: (%r) ERROR: %s\" % (op.va, op, e)\n+ sys.excepthook(*sys.exc_info())\ndef posthook(self, emu, op, starteip):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
lots of updates to disasm and emu. IT needs work.
|
718,770 |
30.03.2018 18:50:32
| 14,400 |
ec370930f1c335cc923cdd599ac3fb48c8926d13
|
unsure of these ARM flags... FIXME:
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -89,11 +89,13 @@ IF_IB = 7<<(IF_DAIB_SHFT-1) # Increment Before\nIF_DAIB_B = 5<<(IF_DAIB_SHFT-1) # Before mask\nIF_DAIB_I = 3<<(IF_DAIB_SHFT-1) # Before mask\n+### what do these do? i can't find reference to them in use\nIFS_VQ = 1<<1 # Adv SIMD: operation uses saturating arithmetic\nIFS_VR = 1<<2 # Adv SIMD: operation performs rounding\nIFS_VD = 1<<3 # Adv SIMD: operation doubles the result\nIFS_VH = 1<<4 # Adv SIMD: operation halves the result\nIFS_SYS_MODE = 1<<8 # instruction is encoded to be executed in SYSTEM mode, not USER mode\n+####################################333\nIFS = [\nNone,\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
unsure of these ARM flags... FIXME:
|
718,770 |
03.04.2018 23:39:33
| 14,400 |
ba59703032da8949e3f3de13a563e01526ad78a6
|
initial cleanup of ARM stuff.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "\"\"\"\nThe initial arm module.\n-\n-\n-FIXME:\n- 00000000:0x00002494 f001ec3a blx sub_00003d0c ;sub_00003d0c()\n- 00000000:0x00002498 f001ec44 blx sub_00003d24 ;UnknownApi() ** Why doesn't this go?\n-\n- Make infinite loop VASET\n-\n- 00000000:0x00002b64 fafffe4a blx loc_00002495 ;UnknownApi() ** Why doesn't this go?\n- 00000000:0x00002b68 00 ;Emu Anomaly: InvalidInstruction(\"extra_load_store: invalid Rt argument 'f7ff0800' at 0x2b70\",)\n-\n-\n\"\"\"\nimport envi\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -351,29 +351,6 @@ IENC_MAX = len(iencs)\nfor ieidx in range(IENC_MAX):\nglobals()[iencs[ieidx]] = ieidx\n-# offchutes\n-IENC_MEDIA_PARALLEL = ((IENC_MEDIA << 8) + 1) << 8\n-IENC_MEDIA_SAT = ((IENC_MEDIA << 8) + 2) << 8\n-IENC_MEDIA_REV = ((IENC_MEDIA << 8) + 3) << 8\n-IENC_MEDIA_SEL = ((IENC_MEDIA << 8) + 4) << 8\n-IENC_MEDIA_USAD8 = ((IENC_MEDIA << 8) + 5) << 8\n-IENC_MEDIA_USADA8 = ((IENC_MEDIA << 8) + 6) << 8\n-IENC_MEDIA_EXTEND = ((IENC_MEDIA << 8) + 7) << 8\n-IENC_MEDIA_PACK = ((IENC_MEDIA << 8) + 8) << 8\n-IENC_MEDIA_SBFX = IENC_MEDIA_PACK #FIXME\n-IENC_MEDIA_PDIV = IENC_MEDIA_PACK #FIXME\n-IENC_UNCOND_CPS = ((IENC_UNCOND << 8) + 1) << 8\n-IENC_UNCOND_SETEND = ((IENC_UNCOND << 8) + 2) << 8\n-IENC_UNCOND_PLD = ((IENC_UNCOND << 8) + 3) << 8\n-IENC_UNCOND_PLI = IENC_UNCOND_PLD #FIXME\n-IENC_UNCOND_BLX = ((IENC_UNCOND << 8) + 4) << 8\n-IENC_UNCOND_RFE = ((IENC_UNCOND << 8) + 5) << 8\n-IENC_UNCOND_CLREX = IENC_UNCOND_PLD #FIXME\n-IENC_UNCOND_DMB = IENC_UNCOND_PLD #FIXME\n-IENC_UNCOND_DSB = IENC_UNCOND_PLD #FIXME\n-IENC_UNCOND_ISB = IENC_UNCOND_PLD #FIXME\n-\n-\n# The supported types of operand shifts (by the 2 bit field)\nS_LSL = 0\nS_LSR = 1\n@@ -388,9 +365,6 @@ SOT_IMM = 1\n#ia was removed as it is not UAL\ndaib = (\"da\", \"\", \"db\", \"ib\")\n-\n-\n-\ninstrnames = [\n'AND',\n'EOR',\n@@ -432,7 +406,6 @@ instrnames = [\n'STC2',\n'LDC',\n'LDC2',\n-\n'VHADD',\n'VQADD',\n'VRHADD',\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
initial cleanup of ARM stuff.
|
718,770 |
10.04.2018 15:56:11
| 14,400 |
9ebb8f41c217c504401240a0837e0ca9e6a46f39
|
make QT4/5 compatability.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/qt/memcanvas.py",
"new_path": "envi/qt/memcanvas.py",
"diff": "@@ -2,9 +2,11 @@ import cgi\ntry:\nfrom PyQt5 import QtCore, QtGui, QtWebKit, QtWebKitWidgets\nfrom PyQt5.QtWebKitWidgets import *\n+ from PyQt5.QtWidgets import *\nexcept:\nfrom PyQt4 import QtCore, QtGui, QtWebKit\nfrom PyQt4.QtWebKit import *\n+ from PyQt4.QtGui import *\nimport vqt.main as vq_main\n@@ -194,7 +196,7 @@ class VQMemoryCanvas(e_memcanvas.MemoryCanvas, QWebView):\ndef contextMenuEvent(self, event):\nva = self._canv_curva\n- menu = QtWidgets.QMenu()\n+ menu = QMenu()\nif self._canv_curva != None:\nself.initMemWindowMenu(va, menu)\n@@ -207,8 +209,10 @@ class VQMemoryCanvas(e_memcanvas.MemoryCanvas, QWebView):\ninitMemSendtoMenu('0x%.8x' % va, menu)\ndef _menuSaveToHtml(self):\n- fname, ftype = QtWidgets.QFileDialog.getSaveFileName(self, 'Save As HTML...')\n- if fname != None and len(fname):\n+ fname = getSaveFileName(self, 'Save As HTML...')\n+ if fname != None:\n+ fname = str(fname)\n+ if len(fname):\nhtml = self.page().mainFrame().toHtml()\nfile(fname, 'w').write(html)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/qt/memdump.py",
"new_path": "envi/qt/memdump.py",
"diff": "@@ -3,6 +3,8 @@ try:\nexcept:\nfrom PyQt4.QtGui import *\n+from vqt.main import getOpenFileName, getSaveFileName\n+\nclass MemDumpDialog(QDialog):\n'''\ngui for memdump cli command.\n@@ -51,7 +53,7 @@ class MemDumpDialog(QDialog):\nself.setWindowTitle(title)\ndef showSaveAsDialog(self):\n- fname = str(QFileDialog.getSaveFileName(caption='Select file to dump memory to'))[0]\n+ fname = str(getSaveFileName(caption='Select file to dump memory to'))\nself.fname_edit.setText(fname)\ndef cancelClicked(self):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/qt/memsearch.py",
"new_path": "envi/qt/memsearch.py",
"diff": "@@ -3,6 +3,7 @@ import string\nimport envi.memory as e_mem\nimport envi.memcanvas as e_canvas\nimport envi.memcanvas.renderers as e_render\n+from vqt.main import getOpenFileName, getSaveFileName\ntry:\nfrom PyQt5 import QtCore, QtGui\n@@ -147,7 +148,7 @@ class MemSearchDialog(QDialog):\nself.hex_edit.setPlainText(str(self.canvas))\ndef showSaveAsDialog(self):\n- fname = str(QFileDialog.getSaveFileName(caption='Select file to save results to'))[0]\n+ fname = str(getSaveFileName(caption='Select file to save results to'))\nself.fname_label.setText(fname)\ndef cancelClicked(self):\n"
},
{
"change_type": "MODIFY",
"old_path": "vdb/qt/main.py",
"new_path": "vdb/qt/main.py",
"diff": "@@ -363,28 +363,28 @@ class VdbWindow(vq_app.VQMainCmdWindow):\nself.vqBuildDockWidget('VdbRegistersWindow', area=QtCore.Qt.RightDockWidgetArea)\ndef menuViewLayoutsLoad(self):\n- fname = QFileDialog.getOpenFileName(self, 'Load Layout')[0]\n+ fname = getOpenFileName(self, 'Load Layout')\nif fname == None:\nreturn\nself.vqClearDockWidgets()\n- settings = QtCore.QSettings(fname, QtCore.QSettings.IniFormat)\n+ settings = QtCore.QSettings(str(fname), QtCore.QSettings.IniFormat)\nself.vqRestoreGuiSettings(settings)\ndef menuViewLayoutsSave(self):\n- fname = QFileDialog.getSaveFileName(self, 'Save Layout')[0]\n+ fname = getSaveFileName(self, 'Save Layout')\nif fname == None:\nreturn\n- settings = QtCore.QSettings(fname, QtCore.QSettings.IniFormat)\n+ settings = QtCore.QSettings(str(fname), QtCore.QSettings.IniFormat)\nself.vqSaveGuiSettings(settings)\ndef menuViewLayoutsClear(self):\nself.vqClearDockWidgets()\ndef menuFileOpen(self, *args, **kwargs):\n- fname = str(QFileDialog.getOpenFileName(parent=self, caption='File to execute and attach to'))[0]\n+ fname = str(getOpenFileName(parent=self, caption='File to execute and attach to'))\nif fname != '':\nself._vq_cli.onecmd('exec \"%s\"' % fname)\n"
},
{
"change_type": "MODIFY",
"old_path": "vdb/qt/memory.py",
"new_path": "vdb/qt/memory.py",
"diff": "@@ -3,7 +3,7 @@ try:\nfrom PyQt5.QtWidgets import QApplication\nexcept:\nfrom PyQt4 import QtCore\n- from PyQt5.QtGui import QApplication\n+ from PyQt4.QtGui import QApplication\nimport vtrace.qt\nimport envi.qt.memory\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -28,16 +28,26 @@ import vivisect.remote.server as viv_server\ntry:\nfrom PyQt5 import QtCore\nfrom PyQt5.QtWidgets import QInputDialog, QFileDialog\n+ from PyQt5.QtCore import PYQT_VERSION_STR\nexcept:\nfrom PyQt4 import QtCore\nfrom PyQt4.QtGui import QInputDialog, QFileDialog\n+ from PyQt4.QtCore import PYQT_VERSION_STR\nfrom vqt.common import *\nfrom vivisect.const import *\n+from vqt.main import getOpenFileName, getSaveFileName\n+from vqt.saveable import compat_isNone, compat_toByteArray\ndock_top = QtCore.Qt.TopDockWidgetArea\ndock_right = QtCore.Qt.RightDockWidgetArea\n+def compat_strList(dwcls):\n+ if PYQT_VERSION_STR.startswith('4'):\n+ return dwcls.toStringList()\n+ return dwcls\n+\n+\nclass VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\n# Child windows may emit this on \"navigate\" requests...\n@@ -222,6 +232,50 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nstate = settings.value('%s/DockState' % guid)\ngeom = settings.value('%s/DockGeometry' % guid)\n+ # PyQt4 is very different here\n+ if compat_isNone(dwcls):\n+ names = self.vw.filemeta.keys()\n+ names.sort()\n+ name = '+'.join(names)\n+ dwcls = settings.value('%s/DockClasses' % name)\n+ state = settings.value('%s/DockState' % name)\n+ geom = settings.value('%s/DockGeometry' % name)\n+\n+ if compat_isNone(dwcls):\n+ dwcls = settings.value('DockClasses')\n+ state = settings.value('DockState')\n+ geom = settings.value('DockGeometry')\n+\n+\n+ if not compat_isNone(dwcls):\n+ print repr(dwcls)\n+ for i, clsname in enumerate(compat_strList(dwcls)):\n+ name = 'VQDockWidget%d' % i\n+ try:\n+ tup = self.vqBuildDockWidget(str(clsname), floating=True)\n+ if tup != None:\n+ d, obj = tup\n+ d.setObjectName(name)\n+ d.vqRestoreState(settings,name)\n+ d.show()\n+ except Exception, e:\n+ print('Error Building: %s: %s' % (clsname,e))\n+\n+ # Once dock widgets are loaded, we can restoreState\n+ if not compat_isNone(state):\n+ self.restoreState(compat_toByteArray(state))\n+\n+ if not compat_isNone(geom):\n+ self.restoreGeometry(compat_toByteArray(geom))\n+\n+ # Just get all the resize activities done...\n+ vq_main.eatevents()\n+ for w in self.vqGetDockWidgets():\n+ w.show()\n+\n+ return True\n+\n+ # or it's Qt5\nif dwcls == None or not len(dwcls):\nnames = self.vw.filemeta.keys()\nnames.sort()\n@@ -240,7 +294,8 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nfor i, clsname in enumerate(dwcls):\nname = 'VQDockWidget%d' % i\ntry:\n- tup = self.vqBuildDockWidget(str(clsname)) # FIXME:, floating=True)\n+ #tup = self.vqBuildDockWidget(str(clsname)) # FIXME:, floating=True)\n+ tup = self.vqBuildDockWidget(str(clsname), floating=True)\nif tup != None:\nd, obj = tup\nd.setObjectName(name)\n@@ -307,7 +362,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nself.vw.vprint('complete!')\ndef _menuFileSaveAs(self):\n- fname = QFileDialog.getSaveFileName(self, 'Save As...')[0]\n+ fname = getSaveFileName(self, 'Save As...')\nif fname == None or not len(fname):\nreturn\nself.vw.setMeta('StorageName', fname)\n@@ -317,7 +372,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nviv_q_remote.saveToServer(self.vw, parent=self)\ndef _menuViewLayoutsLoad(self):\n- fname = QFileDialog.getOpenFileName(self, 'Load Layout')[0]\n+ fname = getOpenFileName(self, 'Load Layout')\nif fname == None:\nreturn\n@@ -325,7 +380,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nself.vqRestoreGuiSettings(settings)\ndef _menuViewLayoutsSave(self):\n- fname = QFileDialog.getSaveFileName(self, 'Save Layout')[0]\n+ fname = getSaveFileName(self, 'Save Layout')\nif fname == None or not len(fname):\nreturn\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/main.py",
"new_path": "vqt/main.py",
"diff": "@@ -252,3 +252,16 @@ def vqtdisconnect(callback, event=None):\nif chan != None:\nchan.guievents.disconnect(callback)\n+def getOpenFileName(*args, **kwargs):\n+ fname = QFileDialog.getOpenFileName(*args, **kwargs)\n+ if type(fname) == tuple:\n+ return fname[0]\n+ return fname\n+\n+def getSaveFileName(*args, **kwargs):\n+ fname = QFileDialog.getSaveFileName(*args, **kwargs)\n+ if type(fname) == tuple:\n+ return fname[0]\n+ return fname\n+\n+\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/saveable.py",
"new_path": "vqt/saveable.py",
"diff": "import json\n+try:\n+ from PyQt5.QtCore import PYQT_VERSION_STR\n+except:\n+ from PyQt4.QtCore import PYQT_VERSION_STR\n+\n+def compat_isNone(state):\n+ if PYQT_VERSION_STR.startswith('4'):\n+ return state.isNull()\n+ return state == None or not len(state)\n+\n+def compat_toStr(qstate):\n+ if PYQT_VERSION_STR.startswith('4'):\n+ return str(qstate.toString())\n+ return str(qstate)\n+\n+def compat_toByteArray(strobj):\n+ if PYQT_VERSION_STR.startswith('4'):\n+ return strobj.toByteArray()\n+ return strobj\n+\nclass SaveableWidget(object):\n'''\nInherited by widgets that want to save and restore settings.\n@@ -16,7 +36,7 @@ class SaveableWidget(object):\nreturn\ntry:\n- state = json.loads(str(qstate))\n+ state = json.loads(compat_toStr(qstate))\nself.vqSetSaveState(state)\nexcept Exception, e:\nprint('failed to restore %s: %s' % (name,e))\n@@ -27,3 +47,4 @@ class SaveableWidget(object):\ndef vqSetSaveState(self, state):\nreturn None\n+\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
make QT4/5 compatability.
|
718,770 |
10.04.2018 16:38:11
| 14,400 |
fb67156a2fd900b334d36ccc4a873e65fde0efd0
|
couple missed bugs
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -14,11 +14,11 @@ import vivisect.qt.ctxmenu as vq_ctxmenu\nimport vivisect.tools.graphutil as viv_graphutil\ntry:\n- from PyQt5.QtCore import pyqtSignal, QPoint\n+ from PyQt5.QtCore import pyqtSignal, QPoint, PYQT_VERSION_STR\nfrom PyQt5 import QtCore, QtGui, QtWebKit\nfrom PyQt5.QtWidgets import *\nexcept:\n- from PyQt4.QtCore import pyqtSignal, QPoint\n+ from PyQt4.QtCore import pyqtSignal, QPoint, PYQT_VERSION_STR\nfrom PyQt4 import QtCore, QtGui, QtWebKit\nfrom PyQt4.QtGui import *\n@@ -207,6 +207,16 @@ function drawSvgLine(svgid, lineid, points) {\n}\n'''\n+def compat_getFrameDimensions(frame, cbname):\n+ if PYQT_VERSION_STR.startswith('4'):\n+ girth, ok = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname).toInt()\n+ height, ok = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname).toInt()\n+ else:\n+ girth = int(frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname))\n+ height = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname)\n+ return girth, height\n+\n+\nimport itertools\nimport collections\n@@ -433,9 +443,10 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\ncbname = 'codeblock_%.8x' % cbva\n#girth, ok = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname).toInt()\n- girth = int(frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname))\n+ #girth = int(frame.evaluateJavaScript('document.getElementById(\"%s\").offsetWidth;' % cbname))\n#height, ok = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname).toInt()\n- height = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname)\n+ #height = frame.evaluateJavaScript('document.getElementById(\"%s\").offsetHeight;' % cbname)\n+ girth, height = compat_getFrameDimensions(frame, cbname)\nself.graph.setNodeProp((nid,nprops), \"size\", (girth, height))\nself.dylayout = vg_dynadag.DynadagLayout(self.graph)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -252,7 +252,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nfor i, clsname in enumerate(compat_strList(dwcls)):\nname = 'VQDockWidget%d' % i\ntry:\n- tup = self.vqBuildDockWidget(str(clsname), floating=True)\n+ tup = self.vqBuildDockWidget(str(clsname), floating=False)\nif tup != None:\nd, obj = tup\nd.setObjectName(name)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
couple missed bugs
|
718,770 |
10.04.2018 17:32:42
| 14,400 |
31592a34f82041056ac0793e361994ca4edb6a37
|
additional cleanup and bugfix for Viv-specific docks.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -231,8 +231,8 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndwcls = settings.value('%s/DockClasses' % guid)\nstate = settings.value('%s/DockState' % guid)\ngeom = settings.value('%s/DockGeometry' % guid)\n+ basename = '%s/VQDockWidget%%d' % guid\n- # PyQt4 is very different here\nif compat_isNone(dwcls):\nnames = self.vw.filemeta.keys()\nnames.sort()\n@@ -240,17 +240,18 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndwcls = settings.value('%s/DockClasses' % name)\nstate = settings.value('%s/DockState' % name)\ngeom = settings.value('%s/DockGeometry' % name)\n+ basename = '%s/VQDockWidget%%d' % name\nif compat_isNone(dwcls):\ndwcls = settings.value('DockClasses')\nstate = settings.value('DockState')\ngeom = settings.value('DockGeometry')\n+ basename = 'VQDockWidget%d'\nif not compat_isNone(dwcls):\n- print repr(dwcls)\nfor i, clsname in enumerate(compat_strList(dwcls)):\n- name = 'VQDockWidget%d' % i\n+ name = basename % i\ntry:\ntup = self.vqBuildDockWidget(str(clsname), floating=False)\nif tup != None:\n@@ -275,49 +276,6 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\nreturn True\n- # or it's Qt5\n- if dwcls == None or not len(dwcls):\n- names = self.vw.filemeta.keys()\n- names.sort()\n- name = '+'.join(names)\n- dwcls = settings.value('%s/DockClasses' % name)\n- state = settings.value('%s/DockState' % name)\n- geom = settings.value('%s/DockGeometry' % name)\n-\n- if dwcls == None or not len(dwcls):\n- dwcls = settings.value('DockClasses')\n- state = settings.value('DockState')\n- geom = settings.value('DockGeometry')\n-\n-\n- if dwcls != None and len(dwcls):\n- for i, clsname in enumerate(dwcls):\n- name = 'VQDockWidget%d' % i\n- try:\n- #tup = self.vqBuildDockWidget(str(clsname)) # FIXME:, floating=True)\n- tup = self.vqBuildDockWidget(str(clsname), floating=True)\n- if tup != None:\n- d, obj = tup\n- d.setObjectName(name)\n- d.vqRestoreState(settings,name)\n- d.show()\n- except Exception, e:\n- print('Error Building: %s: %s' % (clsname,e))\n-\n- # Once dock widgets are loaded, we can restoreState\n- if not state == None:\n- self.restoreState(state)\n-\n- if not geom == None:\n- self.restoreGeometry(geom)\n-\n- # Just get all the resize activities done...\n- vq_main.eatevents()\n- for w in self.vqGetDockWidgets():\n- w.show()\n-\n- return True\n-\ndef vqSaveGuiSettings(self, settings):\ndock_classes = []\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
additional cleanup and bugfix for Viv-specific docks.
|
718,770 |
11.04.2018 12:42:21
| 14,400 |
23023c15d7f859597a5166ec0ede763eb67e4807
|
got PyQt5 restoring state! turns out QByteArray == None. who knew?!
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -231,7 +231,7 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndwcls = settings.value('%s/DockClasses' % guid)\nstate = settings.value('%s/DockState' % guid)\ngeom = settings.value('%s/DockGeometry' % guid)\n- basename = '%s/VQDockWidget%%d' % guid\n+ stub = '%s/' % guid\nif compat_isNone(dwcls):\nnames = self.vw.filemeta.keys()\n@@ -240,24 +240,24 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndwcls = settings.value('%s/DockClasses' % name)\nstate = settings.value('%s/DockState' % name)\ngeom = settings.value('%s/DockGeometry' % name)\n- basename = '%s/VQDockWidget%%d' % name\n+ stub = '%s/' % name\nif compat_isNone(dwcls):\ndwcls = settings.value('DockClasses')\nstate = settings.value('DockState')\ngeom = settings.value('DockGeometry')\n- basename = 'VQDockWidget%d'\n+ stub = ''\nif not compat_isNone(dwcls):\nfor i, clsname in enumerate(compat_strList(dwcls)):\n- name = basename % i\n+ name = 'VQDockWidget%d' % i\ntry:\ntup = self.vqBuildDockWidget(str(clsname), floating=False)\nif tup != None:\nd, obj = tup\nd.setObjectName(name)\n- d.vqRestoreState(settings,name)\n+ d.vqRestoreState(settings,name,stub)\nd.show()\nexcept Exception, e:\nprint('Error Building: %s: %s' % (clsname,e))\n@@ -279,6 +279,10 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndef vqSaveGuiSettings(self, settings):\ndock_classes = []\n+ guid = self.vw.getVivGuid()\n+ names = self.vw.filemeta.keys()\n+ names.sort()\n+ vivname = '+'.join(names)\n# Enumerate the current dock windows and set\n# their names by their list order...\n@@ -287,21 +291,21 @@ class VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\ndock_classes.append(widget.__class__.__name__)\nname = 'VQDockWidget%d' % i\nw.setObjectName(name)\n- w.vqSaveState(settings,name)\n+ w.vqSaveState(settings,'%s/%s' % (guid, name))\n+ w.vqSaveState(settings,'%s/%s' % (vivname, name))\n+\n+ geom = self.saveGeometry()\n+ state = self.saveState()\n# first store for this specific workspace\n- guid = self.vw.getVivGuid()\nsettings.setValue('%s/DockClasses' % guid, dock_classes)\n- settings.setValue('%s/DockGeometry' % guid, self.saveGeometry())\n- settings.setValue('%s/DockState' % guid, self.saveState())\n+ settings.setValue('%s/DockGeometry' % guid, geom)\n+ settings.setValue('%s/DockState' % guid, state)\n# next store for this filename\n- names = self.vw.filemeta.keys()\n- names.sort()\n- name = '+'.join(names)\n- settings.setValue('%s/DockClasses' % name, dock_classes)\n- settings.setValue('%s/DockGeometry' % name, self.saveGeometry())\n- settings.setValue('%s/DockState' % name, self.saveState())\n+ settings.setValue('%s/DockClasses' % vivname, dock_classes)\n+ settings.setValue('%s/DockGeometry' % vivname, geom)\n+ settings.setValue('%s/DockState' % vivname, state)\n# don't store the default. that should be saved manually\ndef _menuToolsDebug(self):\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/application.py",
"new_path": "vqt/application.py",
"diff": "@@ -23,15 +23,15 @@ class VQDockWidget(vq_hotkeys.HotKeyMixin, QDockWidget):\nself.addHotKeyTarget('mem:undockmaximize', self._hotkey_undock_maximize)\nself.setAllowedAreas(QtCore.Qt.AllDockWidgetAreas)\n- def vqSaveState(self, settings, name):\n+ def vqSaveState(self, settings, name, stub=''):\nwid = self.widget()\nif isinstance(wid, vq_save.SaveableWidget):\n- return wid.vqSaveState(settings, name)\n+ return wid.vqSaveState(settings, name, stub)\n- def vqRestoreState(self, settings, name):\n+ def vqRestoreState(self, settings, name, stub=''):\nwid = self.widget()\nif isinstance(wid, vq_save.SaveableWidget):\n- return wid.vqRestoreState(settings, name)\n+ return wid.vqRestoreState(settings, name, stub)\ndef setWidget(self, widget):\n# If he sets his window title, we want to...\n@@ -141,7 +141,7 @@ class VQMainCmdWindow(vq_hotkey.HotKeyMixin, QMainWindow):\nif tup != None:\nd, obj = tup\nd.setObjectName(name)\n- d.vqRestoreState(settings,name)\n+ d.vqRestoreState(settings,name,stub='')\nd.show()\nexcept Exception, e:\nprint('Error Building: %s: %s' % (clsname,e))\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/saveable.py",
"new_path": "vqt/saveable.py",
"diff": "@@ -8,7 +8,12 @@ except:\ndef compat_isNone(state):\nif PYQT_VERSION_STR.startswith('4'):\nreturn state.isNull()\n- return state == None or not len(state)\n+\n+ # WTF! (QByteArray == None) is True!\n+ if state is None:\n+ return True\n+\n+ return not len(state)\ndef compat_toStr(qstate):\nif PYQT_VERSION_STR.startswith('4'):\n@@ -26,12 +31,12 @@ class SaveableWidget(object):\nImplement vqGetSaveState/vqSetSaveState.\n'''\n- def vqSaveState(self, settings, name):\n+ def vqSaveState(self, settings, name, stub=''):\nstate = self.vqGetSaveState()\n- settings.setValue(name, json.dumps(state))\n+ settings.setValue(stub+name, json.dumps(state))\n- def vqRestoreState(self, settings, name):\n- qstate = settings.value(name)\n+ def vqRestoreState(self, settings, name, stub=''):\n+ qstate = settings.value(stub+name)\nif qstate == None:\nreturn\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
got PyQt5 restoring state! turns out QByteArray == None. who knew?!
|
718,770 |
11.04.2018 13:34:37
| 14,400 |
55c85c13494169a2f75db9bb1392688c0832adf3
|
vdb fixes and minor refactor
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/main.py",
"new_path": "vivisect/qt/main.py",
"diff": "@@ -37,16 +37,11 @@ except:\nfrom vqt.common import *\nfrom vivisect.const import *\nfrom vqt.main import getOpenFileName, getSaveFileName\n-from vqt.saveable import compat_isNone, compat_toByteArray\n+from vqt.saveable import compat_isNone, compat_toByteArray, compat_strList\ndock_top = QtCore.Qt.TopDockWidgetArea\ndock_right = QtCore.Qt.RightDockWidgetArea\n-def compat_strList(dwcls):\n- if PYQT_VERSION_STR.startswith('4'):\n- return dwcls.toStringList()\n- return dwcls\n-\nclass VQVivMainWindow(viv_base.VivEventDist, vq_app.VQMainCmdWindow):\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/application.py",
"new_path": "vqt/application.py",
"diff": "@@ -13,6 +13,7 @@ import vqt.main as vq_main\nimport vqt.saveable as vq_save\nimport vqt.hotkeys as vq_hotkeys\nimport vqt.menubuilder as vq_menu\n+from vqt.saveable import compat_isNone, compat_toByteArray, compat_strList\nclass VQDockWidget(vq_hotkeys.HotKeyMixin, QDockWidget):\n@@ -129,31 +130,30 @@ class VQMainCmdWindow(vq_hotkey.HotKeyMixin, QMainWindow):\nobj = cls(*args)\nreturn self.vqDockWidget(obj, area, floating=floating), obj\n- def vqRestoreGuiSettings(self, settings):\n-\n+ def vqRestoreGuiSettings(self, settings, stub=''):\ndwcls = settings.value('DockClasses')\n- if dwcls != None:\n- for i, clsname in enumerate(dwcls):\n+ if not compat_isNone(dwcls):\n+ for i, clsname in enumerate(compat_strList(dwcls)):\nname = 'VQDockWidget%d' % i\ntry:\n- tup = self.vqBuildDockWidget(str(clsname), floating=True)\n+ tup = self.vqBuildDockWidget(str(clsname), floating=False)\nif tup != None:\nd, obj = tup\nd.setObjectName(name)\n- d.vqRestoreState(settings,name,stub='')\n+ d.vqRestoreState(settings,name,stub)\nd.show()\nexcept Exception, e:\nprint('Error Building: %s: %s' % (clsname,e))\n# Once dock widgets are loaded, we can restoreState\nstate = settings.value('DockState')\n- if state != None:\n- self.restoreState(state)\n+ if not compat_isNone(state):\n+ self.restoreState(compat_toByteArray(state))\ngeom = settings.value('DockGeometry')\n- if geom != None:\n- self.restoreGeometry(geom)\n+ if not compat_isNone(geom):\n+ self.restoreGeometry(compat_toByteArray(geom))\n# Just get all the resize activities done...\nvq_main.eatevents()\n@@ -162,7 +162,7 @@ class VQMainCmdWindow(vq_hotkey.HotKeyMixin, QMainWindow):\nreturn True\n- def vqSaveGuiSettings(self, settings):\n+ def vqSaveGuiSettings(self, settings, stub=''):\ndock_classes = []\n@@ -173,7 +173,7 @@ class VQMainCmdWindow(vq_hotkey.HotKeyMixin, QMainWindow):\ndock_classes.append(widget.__class__.__name__)\nname = 'VQDockWidget%d' % i\nw.setObjectName(name)\n- w.vqSaveState(settings,name)\n+ w.vqSaveState(settings,name,stub)\nsettings.setValue('DockClasses', dock_classes)\nsettings.setValue('DockGeometry', self.saveGeometry())\n"
},
{
"change_type": "MODIFY",
"old_path": "vqt/saveable.py",
"new_path": "vqt/saveable.py",
"diff": "@@ -25,6 +25,11 @@ def compat_toByteArray(strobj):\nreturn strobj.toByteArray()\nreturn strobj\n+def compat_strList(dwcls):\n+ if PYQT_VERSION_STR.startswith('4'):\n+ return dwcls.toStringList()\n+ return dwcls\n+\nclass SaveableWidget(object):\n'''\nInherited by widgets that want to save and restore settings.\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
vdb fixes and minor refactor
|
718,770 |
11.04.2018 20:43:55
| 14,400 |
235d285be65fd5806d3a885d0e0a61260ebb9697
|
updated arm/thumb archGetNopInstr
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -28,7 +28,7 @@ class ArmModule(envi.ArchitectureModule):\nreturn\ndef archGetNopInstr(self):\n- return '\\x00'\n+ return ('\\x00\\x00\\x60\\xe3', '\\xe3\\x60\\x00\\x00')[self._endian] #FIXME: this is only ARM mode. this arch mod should cover both. the ENVI architecture doesn't support this model yet.\ndef archGetBadOps(self):\noplist = [ self.archParseOpcode(badop,0,0) for badop in self._arch_badopbytes ]\n@@ -93,7 +93,7 @@ class ThumbModule(envi.ArchitectureModule):\nreturn\ndef archGetNopInstr(self):\n- return '\\x00'\n+ return ('\\xc0\\x46', '\\x46\\xc0')[self._endian]\ndef archGetBadOps(self):\noplist = [ self.archParseOpcode(badop,0,0) for badop in self._arch_badopbytes ]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updated arm/thumb archGetNopInstr
|
718,770 |
28.06.2018 17:20:00
| 14,400 |
469de1635510da331ee9106d51ad43f40cf0ba23
|
updates to IT and conflicts...
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -788,7 +788,7 @@ def p_dp_movt(opval, va):\nreturn(opcode, \"movt\", olist, iflags, 0)\nhint_mnem = {\n- 0: ('Nop',INS_NOP),\n+ 0: ('nop',INS_NOP),\n1: ('yield',INS_YIELD),\n2: ('wfe',INS_WFE),\n3: ('wfi',INS_WFI),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -232,22 +232,27 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif self.itcount:\nself.itcount -= 1\nprint \"untested IT functionality\"\n- if not (self.itflags & 1):\n+ if not (self.itmask & 1):\nskip = True\n+ self.itmask >>= 1\n# standard conditional handling\ncondval = (op.prefixes >= 0xe)\n+\nif not condval:\ncondcheck = conditionals[op.prefixes]\ncondval = condcheck(self.getRegister(REG_FLAGS))\n+ # the actual execution... if we're supposed to.\nif condval and not skip:\nmeth = self.op_methods.get(op.mnem, None)\nif meth == None:\nraise envi.UnsupportedInstruction(self, op)\n- x = meth(op)\n+ # executing opcode now...\n+ x = meth(op)\n+ # returned None, so the instruction hasn't directly changed PC\nif x == None:\npc = self.getProgramCounter()\nx = pc+op.size\n@@ -1510,6 +1515,10 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n#TODO: IT EQ\n+ def i_it(self, op):\n+ self.itcount, self.ittype, self.itmask = op.opers[0].getCondData()\n+ condcheck = conditionals[self.ittype]\n+ self.itva = op.va\nopcode_dist = \\\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -559,6 +559,14 @@ def itblock(va, val):\nfirstcond = (val>>4) & 0xf\nreturn COND_AL,(ThumbITOper(mask, firstcond),), None\n+\n+\n+it_strs_0 = ['']\n+it_strs_1 = ['e', 't']\n+it_strs_2 = ['ee','et','te','tt']\n+it_strs_3 = ['eee','tee','ete','tte','eet','tet','ett','ttt']\n+it_strs = (it_strs_0, it_strs_1, it_strs_2, it_strs_3)\n+\nclass ThumbITOper(ArmOperand):\ndef __init__(self, mask, firstcond):\nself.mask = mask\n@@ -570,63 +578,56 @@ class ThumbITOper(ArmOperand):\nif mask & 1:\nbreak\nmask >>= 1\n- return x\n+ return x - 1\ndef getFlags(self):\nfiz = self.firstcond & 1\nflags = 1\ncount = self.getCondInstrCount()\n- for x in range(1, count):\n- print x, bin(flags)\n- flags |= ((((self.mask>>(4-x))&1) == fiz) << (x+1))\n+ print bin(fiz), bin(self.mask)\n+ for x in range(count):\n+ bit = bool(((self.mask>>(3-x))&1) == fiz)\n+ print x, bit, bin(flags)\n+ flags |= (bit << (x+1))\nreturn flags\n- def repr(self, op):\n+ def getCondData(self):\nmask = self.mask\ncond = self.firstcond\n-\n- fcond = cond_codes.get(cond)\n-\n- itbytes = []\n-\n+ count = 0\ngo = 0\ncond0 = cond & 1\n+ data = 0\n+\nfor idx in range(4):\nmbit = (mask>>idx) & 1\nif go:\n- if mbit == cond0:\n- itbytes.append('t')\n- else:\n- itbytes.append('e')\n+ bit = bool(mbit == cond0)\n+ data <<= 1\n+ data |= bit\n+ count += 1\nif mbit:\ngo = 1\n- nextfew = ''.join(itbytes)\n- return \"%s %s\" % (nextfew, fcond)\n- def render(self, mcanv, op, idx):\n+ return count, self.firstcond, data\n+\n+ def repr(self, op):\nmask = self.mask\n- cond = self.firstcond\n- fcond = cond_codes.get(cond)\n+ count, cond, data = self.getCondData()\n- itbytes = []\n+ fcond = cond_codes.get(cond)\n+ nextfew = it_strs[count][data]\n+ return \"%s %s\" % (nextfew, fcond)\n- go = 0\n- cond0 = cond & 1\n- for idx in range(4):\n- mbit = (mask>>idx) & 1\n- if go:\n- if mbit == cond0:\n- itbytes.append('t')\n- else:\n- itbytes.append('e')\n+ def render(self, mcanv, op, idx):\n+ mask = self.mask\n- if mbit:\n- go = 1\n+ count, cond, data = self.getCondData()\n- nextfew = ''.join(itbytes)\n+ fcond = cond_codes.get(cond)\nmcanv.addText(\"%s %s\" % (nextfew, fcond))\ndef getOperValue(self, idx, emu=None):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updates to IT and conflicts...
|
718,770 |
06.07.2018 15:15:33
| 14,400 |
d3eaee4afb37f85f392b3dc79904337097e7578e
|
bunch of decode/emu/codeflow bugfixes, improved floating point decoding
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -114,7 +114,9 @@ class ThumbModule(envi.ArchitectureModule):\nreturn self._arch_dis.disasm(bytes, offset, va)\ndef getEmulator(self):\n- return ArmEmulator()\n+ emu = ArmEmulator()\n+ emu.setThumbMode()\n+ return emu\ndef setEndian(self, endian):\nself._endian = endian\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3061,7 +3061,9 @@ def _do_adv_simd_32(val, va, u):\nshift_amount = imm - 8\nuop = (u<<1) | op\n+ #print \"uop: %x\" % uop\nsimdflags = adv_2_vqshl_typesize.get(esize)[uop]\n+ #print \"enctype4: simdflags: %r\" % simdflags\nelif enctype == 5: # VCVT\nlimm = (l<<6) | imm\n@@ -3097,6 +3099,7 @@ def _do_adv_simd_32(val, va, u):\n#simdflags = { 8: IFS_8, 16: IFS_16, 32: IFS_32, 64: IFS_64 }[esize]\nidx = {8:0, 16:1, 32:2, 64:3}[esize]\nsimdflags = adv_simd_dts[20 + (idx) + foffset]\n+ #print \"simdflags: %r\" % simdflags\nelif enctype == 7: # VSHRN needs different simdflags...\nlimm = (l<<6) | imm\n@@ -3769,10 +3772,6 @@ class ArmOpcode(envi.Opcode):\n# check for location being ODD\noperval = oper.getOperValue(self, emu)\n- if operval == None:\n- # probably a branch to a register. just return.\n- return ret\n-\nif self.opcode in (INS_BLX, INS_BX):\nif operval & 3:\nflags |= envi.ARCH_THUMB\n@@ -3784,10 +3783,15 @@ class ArmOpcode(envi.Opcode):\nelse:\nflags |= self._def_arch\n+ # if branch to register, let's return an entry for the DynamicBranch handler\n+ #if operval == None:\n+ # probably a branch to a register. just return.\n+ #ret.append((None, flags))\n#operval &= 0xfffffffe # this has to work for both arm and thumb\nif self.iflags & envi.IF_CALL:\nflags |= envi.BR_PROC\n+\nret.append((operval, flags))\n#print \"getBranches: (0x%x) add 0x%x %x\"% (self.va, operval, flags)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -11,7 +11,7 @@ import envi.bits as e_bits\nfrom envi.const import *\nfrom envi.archs.arm.regs import *\nfrom envi.archs.arm import ArmModule\n-from envi.archs.arm.disasm import ArmRegOper, ArmRegShiftImmOper\n+from envi.archs.arm.disasm import ArmRegOper, ArmRegShiftImmOper, ArmImmOper\nlogger = logging.getLogger(__name__)\n@@ -540,8 +540,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_orr(self, op):\ntsize = op.opers[0].tsize\n+ if len(op.opers) == 3:\nval1 = self.getOperValue(op, 1)\nval2 = self.getOperValue(op, 2)\n+ else:\n+ val1 = self.getOperValue(op, 0)\n+ val2 = self.getOperValue(op, 1)\nval = val1 | val2\nself.setOperValue(op, 0, val)\n@@ -747,7 +751,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setFlag(PSR_T_bit, thumb)\ndef setArmMode(self, arm=1):\n- self.setFlag(PSR_T_bit, not thumb)\n+ self.setFlag(PSR_T_bit, not arm)\ndef i_ldr(self, op):\n# hint: covers ldr, ldrb, ldrbt, ldrd, ldrh, ldrsh, ldrsb, ldrt (any instr where the syntax is ldr{condition}stuff)\n@@ -1117,8 +1121,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_eor(self, op):\ndsize = op.opers[0].tsize\n+ if len(op.opers) == 3:\nsrc1 = self.getOperValue(op, 1)\nsrc2 = self.getOperValue(op, 2)\n+ else:\n+ src1 = self.getOperValue(op, 0)\n+ src2 = self.getOperValue(op, 1)\n#FIXME PDE and flags\nif src1 == None or src2 == None:\n@@ -1454,6 +1462,22 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_umull(self, op):\nprint(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n+ def i_mla(self, op):\n+ src1 = self.getOperValue(op, 1)\n+ src2 = self.getOperValue(op, 2)\n+ src3 = self.getOperValue(op, 3)\n+\n+ val = (src1 * src2 + src3) & 0xffffffff\n+\n+ self.setOperValue(op, 0, val)\n+\n+ Sflag = op.iflags & IF_PSR_S\n+ if Sflag:\n+ self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))\n+ self.setFlag(PSR_Z_bit, not val)\n+\n+\n+\ndef i_cps(self, op):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -36,7 +36,7 @@ class simpleops:\ndef __call__(self, va, value):\nret = []\nfor otype, shval, mask in self.operdef:\n- oval = shmaskval(value, shval, mask)\n+ #oval = shmaskval(value, shval, mask)\noper = OperType[otype]((value >> shval) & mask, va=va)\nret.append( oper )\nreturn COND_AL, (ret), None\n@@ -49,7 +49,6 @@ rm_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))\nrn_rdm = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))\nrm_rdn = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))\nrm_rd_imm0 = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 0, 0))\n-rm4_shift3 = simpleops((O_REG, 3, 0xf))\nrm_rn_rt = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG, 6, 0x7))\nimm8 = simpleops((O_IMM, 8, 0xff))\n#imm11 = simpleops((O_IMM, 11, 0x7ff))\n@@ -118,6 +117,15 @@ def rt_pc_imm8(va, value): # ldr\noper1 = ArmImmOffsetOper(REG_PC, imm, (va&0xfffffffc))\nreturn COND_AL,(oper0,oper1), None\n+def rm4_shift3(va, value): #bx/blx\n+ iflags = None\n+ otype, shval, mask = O_REG, 3, 0xf\n+ oval = shmaskval(value, shval, mask)\n+ oper = ArmRegOper((value >> shval) & mask, va=va)\n+ if oval == REG_LR:\n+ l = bool(value & 0b0000000010000000)\n+ iflags = envi.IF_RET | (envi.IF_NOFALL, envi.IF_CALL)[l]\n+ return COND_AL, (oper,), iflags\nbanked_regs = (\n( REG_OFFSET_USR + 8, ),\n@@ -347,8 +355,8 @@ def branch_misc(va, val, val2): # bl and misc control\nelse:\nopcode, mnem = cpsh_mnems.get(op2, (INS_DEBUGHINT, 'dbg'))\n+ opers = []\n- #raise Exception(\"FIXME: Change processor state ad hints p A6-234\")\nreturn COND_AL, opcode, mnem, opers, flags, 0\nelif op == 0b0111011:\n@@ -628,6 +636,7 @@ class ThumbITOper(ArmOperand):\ncount, cond, data = self.getCondData()\nfcond = cond_codes.get(cond)\n+ nextfew = it_strs[count][data]\nmcanv.addText(\"%s %s\" % (nextfew, fcond))\ndef getOperValue(self, idx, emu=None):\n@@ -1432,47 +1441,8 @@ def dp_shift_32(va, val1, val2):\nreturn COND_AL, opcode, mnem, opers, flags, 0\n-def dp_mod_imm_32_deprecated(va, val1, val2):\n- op = (val1 >> 5) & 0xf\n- rn = val1 & 0xf\n- rd = (val2 >> 8) & 0xf\n- imm = ((val1 >> 10) & 1) | ((val2 >> 4) & 0xf00) | (val2 & 0xff)\n- s = (val1 >> 4) & 1\n-\n- oper2 = ArmImmOper(imm)\n-\n- if rd == 0xf and s:\n- opcode, mnem, opcnt = dp_shift_alt1[op]\n- oper1 = ArmRegOper(rn, va=va)\n- if opcnt == 3:\n- oper0 = ArmRegOper(rd, va=va)\n- opers = (oper0, oper1, oper2)\n- else:\n- opers = (oper1, oper2)\n-\n- elif rn == 0xf:\n- opcode, mnem, opcnt = dp_shift_alt2[op]\n- oper0 = ArmRegOper(rd, va=va)\n- if opcnt == 3:\n- oper1 = ArmRegOper(rn, va=va)\n- opers = (oper0, oper1, oper2)\n- else:\n- opers = (oper0, oper2)\n-\n- else:\n- opcode, mnem, opcnt = dp_shift_ops[op]\n- oper0 = ArmRegOper(rd, va=va)\n- oper1 = ArmRegOper(rn, va=va)\n- opers = (oper0, oper1, oper2)\n-\n- if s:\n- flags = IF_PSR_S\n- else:\n- flags = 0\n-\n- return COND_AL, opcode, mnem, opers, flags, 0\n-\ndef coproc_simd_32(va, val1, val2):\n+ #print \"coproc_simd_32\"\n# p249 of ARMv7-A and ARMv7-R arch ref manual, parts 2 and 3 (not top section)\nval32 = (val1 << 16) | val2\n@@ -1487,6 +1457,7 @@ def coproc_simd_32(va, val1, val2):\niflags = 0\nsimdflags = 0\n+ #print bin(coproc), bin(op1),bin(op)\nif op1 & 0b110000 == 0b110000:\nreturn adv_simd_32(va, val1, val2)\n@@ -1557,7 +1528,7 @@ def coproc_simd_32(va, val1, val2):\nCRd = (val2>>12) & 0xf\nopc2 = (val2>>5) & 0x7\nCRm = val2 & 0xf\n- mnem = cdp_mnem[(val1>>12)&1]\n+ mnem, opcode = cdp_mnem[(val1>>12)&1]\nopers = (\nArmCoprocOper(coproc),\n@@ -1568,8 +1539,6 @@ def coproc_simd_32(va, val1, val2):\nArmCoprocOpcodeOper(opc2),\n)\n- opcode = (IENC_COPROC_DP << 16)\n-\nelif op1 & 0b110000 == 0b100000 and op == 1: # 10xxx0 and 10xxx1\n# mcr/mcr2 (a8-474)\n# mrc/mrc2 (a8-490)\n@@ -1594,6 +1563,7 @@ def coproc_simd_32(va, val1, val2):\nopcode = (IENC_COPROC_REG_XFER << 16)\nelse:\n+ # coproc = 0b101x\n# FIXME: REMOVE WHEN DONE IMPLEMENTING\nopcode = 0\niflags = 0\n@@ -1682,7 +1652,9 @@ def coproc_simd_32(va, val1, val2):\nelse:\n# adv simd fp (a7-276)\nmnem = 'UNIMPL: adv simd' # FIXME\n- return adv_simd_32(va, val1, val2)\n+ #print \"->adv_xfer_arm_ext_32\"\n+ return adv_xfer_arm_ext_32(va, val1, val2)\n+ #return adv_simd_32(va, val1, val2)\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n@@ -1696,59 +1668,62 @@ def adv_simd_32(va, val1, val2):\nval = (val1 << 16) | val2\nu = (val1 >> 12) & 1\nopcode, mnem, opers, iflags, simdflags = _do_adv_simd_32(val, va, u)\n+ #print \"simdflags: %r\" % simdflags\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n-def _adv_simd_32(va, val1, val2):\n- # aside from u and the first 8 bits, ARM and Thumb2 decode identically (A7-259)\n- u = (val1>>12) & 1\n- a = (val1>>3) & 0x1f\n- b = (val2>>8) & 0xf\n- c = (val2>>4) & 0xf\n-\n- print \"a=%x\\tb=%x\\tu=%x\\tc=%x\" % (a, b, u, c)\n- if not (a & 0x10):\n- # three registers of the same length\n- a = (val2>>8) & 0xf\n- b = (val2>>4) & 1\n- c = (val1>>4) & 3\n-\n- #print \" adv simd: 3 same: a=%x\\tb=%x\\tu=%x\\tc=%x\" % (a, b, u, c)\n- index = c | (u<<2) | (b<<3) | (a<<4)\n- #print \" adv simd: 3 same: %x\" % index\n- mnem, opcode, simdflags, handler = adv_simd_3_regs[index]\n-\n- d = (val1 >> 2) & 0x10\n- d |= ((val2 >> 12) & 0xf)\n-\n- n = (val2 >> 3) & 0x10\n- n |= (val1 & 0xf)\n-\n- m = (val2 >> 1) & 0x10\n- m |= (val2 & 0xf)\n-\n- q = (val2 >> 2) & 0x10\n-\n- rbase = ('d%d', 'q%d')[q]\n- opers = (\n- ArmRegOper(rctx.getRegisterIndex(rbase%d)),\n- ArmRegOper(rctx.getRegisterIndex(rbase%n)),\n- ArmRegOper(rctx.getRegisterIndex(rbase%m)),\n- )\n+def adv_xfer_arm_ext_32(va, val1, val2):\n+ val = (val1 << 16) | val2\n+ if val & 0x0f000e10 != 0x0e000a10:\n+ bytez = struct.pack(\"<I\", val)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_32\", bytez=bytez, va=va)\n- if handler != None:\n- nmnem, nopcode, nflags, nopers = handler(val, va, mnem, opcode, simdflags, opers)\n- if nmnem != None:\n- mnem = nmnem\n- opcode = nopcode\n- if nflags != None:\n- simdflags = nflags\n- if nopers != None:\n- opers = nopers\n+ a = (val>>21) & 7\n+ l = (val>>20) & 1\n+ c = (val>>8) & 1\n+ b = (val>>5) & 3\n- return COND_AL, opcode, mnem, opers, 0, simdflags\n+ iflags = 0\n+ simdflags = 0\n+ opers = None\n+ if l == 0:\n+ if c == 0:\n+ if a == 0:\n+ # p.A8-944\n+ mnem, opcode = 'vmov', INS_VMOV\n+ opers = ()\n+ elif a == 7:\n+ # p.A8-956\n+ mnem, opcode = 'vmsr', INS_VMSR\n+ opers = ()\n+ else: # c == 1\n+ if (a & 0b100) == 0:\n+ # p.A8-940\n+ mnem, opcode = 'vmov', INS_VMOV\n+ opers = ()\n+ else:\n+ if b & 2:\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_32: b & 2\", bytez=bytez, va=va)\n+ # p.A8-886\n+ mnem, opcode = 'vdup', INS_VDUP\n+ opers = ()\n+ else: # l == 1\n+ if c == 0:\n+ if a == 0:\n+ # p.A8-944\n+ mnem, opcode = 'vmov', INS_VMOV\n+ opers = ()\n+ elif a == 7:\n+ # p.A8-954 & B9-2012\n+ mnem, opcode = 'vmrs', INS_VMRS\n+ opers = ()\n+ else: # c == 1\n+ # p.A8-942\n+ mnem, opcode = 'vmov', INS_VMOV\n+ opers = ()\n+ return COND_AL, opcode, mnem, opers, iflags, simdflags\nbcc_ops = {\n@@ -1988,6 +1963,7 @@ thumb2_extension = [\n('11110000001', (85,'bic', dp_mod_imm_32, IF_THUMB32)),\n('11110000010', (85,'orr', dp_mod_imm_32, IF_THUMB32)),\n('11110000011', (85,'orn', dp_mod_imm_32, IF_THUMB32)), # mvn if rn=1111\n+ ('11110000110', (85,'blx', branch_misc, IF_THUMB32)),\n('11110000100', (85,'eor', dp_mod_imm_32, IF_THUMB32)), # teq if rd=1111 and s=1\n('11110001000', (85,'add', dp_mod_imm_32, IF_THUMB32)), # cmn if rd=1111 and s=1\n('11110001010', (85,'adc', dp_mod_imm_32, IF_THUMB32)),\n@@ -2163,6 +2139,7 @@ class ThumbDisasm:\nif flags & IF_THUMB32:\nval2, = struct.unpack_from(self.hfmt, bytez, offset+2)\ncond, nopcode, nmnem, olist, nflags, simdflags = opermkr(va+4, val, val2)\n+ #print \"simdflags: %r\" % simdflags\nif nmnem != None: # allow opermkr to set the mnem\nmnem = nmnem\n@@ -2199,6 +2176,7 @@ class ThumbDisasm:\nif mnem == None or type(mnem) == int:\nraise Exception(\"mnem == %r! 0x%xi (thumb)\" % (mnem, opval))\n+ #print \"simdflags: %r\" % simdflags\nop = ThumbOpcode(va, opcode, mnem, cond, oplen, olist, flags, simdflags)\n#print hex(va), oplen, len(op), op.size, hex(op.iflags)\nreturn op\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -164,6 +164,10 @@ class CodeFlowContext(object):\n# The opcode callback may filter branches...\nbranches = self._cb_opcode(va, op, branches)\n+ # FIXME: if IF_BRANCH: if IF_COND and len(branches)<2: _cb_dynamic_branch()\n+ # FIXME: if IF_BRANCH and not IF_COND and len(branches)<1: _cb_dynamic_branch()\n+ # FIXME: if IF_CALL and len(branches)<2: _cb_dynamic_branch()\n+\nwhile len(branches):\nbva, bflags = branches.pop()\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -30,7 +30,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\ntry:\ntmode = emu.getFlag(PSR_T_bit)\nself.last_tmode = tmode\n- if self.verbose: print \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op)\n+ #if self.verbose: print \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op)\n#if op == self.badop:\nif op in self.badops:\nraise Exception(\"Hit known BADOP at 0x%.8x %s\" % (starteip, repr(op) ))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/lookup.py",
"new_path": "vivisect/impemu/lookup.py",
"diff": "@@ -7,6 +7,7 @@ import vivisect.impemu.platarch.i386 as v_i_i386\nimport vivisect.impemu.platarch.amd64 as v_i_amd64\nimport vivisect.impemu.platarch.msp430 as v_i_msp430\nimport vivisect.impemu.platarch.windows as v_i_windows\n+import vivisect.impemu.platarch.decree as v_i_decree\nworkspace_emus = {\n'h8' :v_i_h8.H8WorkspaceEmulator,\n@@ -14,5 +15,7 @@ workspace_emus = {\n'i386' :v_i_i386.i386WorkspaceEmulator,\n'amd64' :v_i_amd64.Amd64WorkspaceEmulator,\n'msp430' :v_i_msp430.Msp430WorkspaceEmulator,\n+ 'thumb2' :v_i_arm.ThumbWorkspaceEmulator,\n('windows','i386'):v_i_windows.Windowsi386Emulator,\n+ ('decree','i386'):v_i_decree.Decreei386WorkspaceEmulator,\n}\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/monitor.py",
"new_path": "vivisect/impemu/monitor.py",
"diff": "@@ -205,6 +205,6 @@ class AnalysisMonitor(EmulationMonitor):\n# WOOT - we have found a runtime resolved function!\nself.vw.verbprint('0x%.8x: Emulation Found 0x%.8x (from func: 0x%.8x) via %s' % (op.va, pc, self.fva, repr(op)))\n- self.vw.makeFunction(pc)\n+ self.vw.makeFunction(pc, arch=op.iflags)\nself.vw.addXref(op.va, pc, REF_CODE, envi.BR_PROC)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "+import sys\nimport envi\nimport envi.archs.arm as e_arm\n@@ -19,6 +20,14 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nv_i_emulator.WorkspaceEmulator.__init__(self, vw, logwrite=logwrite, logread=logread)\nself.setMemArchitecture(envi.ARCH_ARMV7)\n+ def setThumbMode(self, thumb=1):\n+ self.opcache = {}\n+ e_arm.ArmEmulator.setThumbMode(self, thumb)\n+\n+ def setArmMode(self, arm=1):\n+ self.opcache = {}\n+ e_arm.ArmEmulator.setArmMode(self, arm)\n+\ndef parseOpcode(self, va, arch=envi.ARCH_DEFAULT):\n'''\nCaching version.\n@@ -29,6 +38,11 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nMade for ARM, because envi.Emulator doesn't understand the Thumb flag\n'''\nop = self.opcache.get(va)\n+\n+ tmode = self.getFlag(PSR_T_bit)\n+ if arch == envi.ARCH_DEFAULT:\n+ arch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[tmode]\n+\nif op == None:\nop = envi.archs.arm.emu.ArmEmulator.parseOpcode(self, va, arch=arch)\nself.opcache[va] = op\n@@ -198,10 +212,19 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.emumon.logAnomaly(self, starteip, str(e))\nif verbose: print 'runFunction breaking after exception (fva: 0x%x): %s' % (funcva, e)\n+ if verbose: sys.excepthook(*sys.exc_info())\nbreak # If we exc during execution, this branch is dead.\n#except:\n# sys.excepthook(*sys.exc_info())\n+\n+class ThumbWorkspaceEmulator(ArmWorkspaceEmulator):\n+ def __init__(self, vw, logwrite=False, logread=False):\n+ ArmWorkspaceEmulator.__init__(self, vw, logwrite, logread)\n+ self.setThumbMode()\n+\n+ def runFunction(self, funcva, stopva=None, maxhit=None, maxloop=None, tmode=None):\n+ return ArmWorkspaceEmulator.runFunction(self, funcva, stopva, maxhit, maxloop, tmode=1)\n'''\nst0len gratuitously from wikipedia:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bunch of decode/emu/codeflow bugfixes, improved floating point decoding
|
718,770 |
20.08.2018 14:02:13
| 14,400 |
91d57c5b638bfde5aeff88a2e624e5059e4186bb
|
arm/thumb bugfixes and enhancements
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -71,6 +71,18 @@ class ArmModule(envi.ArchitectureModule):\nreturn tova & -2, reftype, rflags\nreturn tova, reftype, rflags\n+ def archGetRegisterGroups(self):\n+ groups = envi.ArchitectureModule.archGetRegisterGroups(self)\n+\n+ groups.append(('general', arm_regs))\n+\n+ # compilers use the following regs to stick the module baseaddr in for\n+ # switchcase code\n+ #switch_mapbase = ('switch_mapbase', [ 'edi', 'esi' ],)\n+ #groups.append(switch_mapbase)\n+ return groups\n+\n+\nclass ThumbModule(envi.ArchitectureModule):\n'''\nThis architecture module will *not* shift to ARM mode. Evar.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -73,7 +73,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\ntry:\ntgt = op.getOperValue(0, emu)\n- if self.verbose: print \"BRANCH: \", hex(tgt), hex(op.va), hex(op.va)\n+ #if self.verbose: print \"BRANCH: \", hex(tgt), hex(op.va), hex(op.va)\nif tgt == op.va:\nif self.verbose: print \"+++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\"\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -86,7 +86,7 @@ def analyzeFunction(vw, fva, prepend=False):\nop = vw.parseOpcode(tva)\nemu.executeOpcode(op)\n- if op.iflags & envi.IF_NOFALL:\n+ if op.iflags & (envi.IF_BRANCH | envi.IF_COND) == (envi.IF_BRANCH | envi.IF_COND):\nbreak\nif not len(op.opers):\n@@ -121,7 +121,7 @@ def analyzeFunction(vw, fva, prepend=False):\ntry:\nemu.runFunction(fva, maxhit=1)\nexcept:\n- print(\"Error emulating function 0x%x\\n\\t%s\" % (fva, repr(emumon.emuanom)))\n+ vw.vprint(\"Error emulating function 0x%x\\n\\t%s\" % (fva, repr(emumon.emuanom)))\nif vw.verbose: sys.stderr.write('=')\n@@ -131,7 +131,12 @@ def analyzeFunction(vw, fva, prepend=False):\nfor va, tgt in items:\n# if we already have xrefs, don't make more...\nif vw.getLocation(tgt) == None:\n+ try:\nvw.followPointer(tgt)\n+ except envi.SegmentationViolation:\n+ if vw.verbose: vw.vprint(\"SegV: %x (va:0x%x)\" % (tgt,va))\n+ emumon.emuanom.append(\"SegV: %x (va:0x%x)\" % (tgt,va))\n+ continue\nnogo = False\nfor xfr,xto,xtype,xflag in vw.getXrefsFrom(va):\n@@ -170,6 +175,11 @@ def analyze(vw):\npass\nif globals().get('vw') != None:\n+ if len(argv) > 1:\n+ va = vw.parseExpression(argv[1])\n+ vw.vprint(\"analyzing workspace function %x for thunk_reg\", va)\n+ analyzeFunction(vw, va)\n+ else:\nvw.vprint(\"analyzing workspace for thunk_reg\")\nanalyze(vw)\nvw.vprint(\"done\")\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm/thumb bugfixes and enhancements
|
718,770 |
20.08.2018 14:27:10
| 14,400 |
0aa0798a760e08dd10737b31864aeb97c0b91bae
|
for derefs, shows the OperAddr as well.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/ctxmenu.py",
"new_path": "vivisect/qt/ctxmenu.py",
"diff": "@@ -45,6 +45,10 @@ def printEmuState(vw, fva, va):\nfor i in xrange(len(op.opers)):\no = op.opers[i]\no.render(vw.canvas, op, i)\n+ oaddr = o.getOperAddr(op, emu)\n+ if oaddr != None:\n+ vw.canvas.addText(' [ 0x%x ] ' % oaddr)\n+\nvw.canvas.addText(\" = \")\noval = o.getOperValue(op, emu)\ntaint = emu.getVivTaint(oval)\n@@ -67,7 +71,10 @@ def buildContextMenu(vw, va=None, expr=None, menu=None, parent=None, nav=None):\nnav - the \"local\" EnviNavMixin instance\n'''\nif va == None:\n+ try:\nva = vw.parseExpression(expr)\n+ except Exception, e:\n+ sys.excepthook(*sys.exc_info())\nif expr == None:\nexpr = '0x%.8x' % va\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
for derefs, shows the OperAddr as well.
|
718,770 |
20.08.2018 14:33:59
| 14,400 |
53aa7492df3747017a2d53fe5df224ad7c851c6c
|
residue from a separate delta.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/ctxmenu.py",
"new_path": "vivisect/qt/ctxmenu.py",
"diff": "@@ -71,10 +71,7 @@ def buildContextMenu(vw, va=None, expr=None, menu=None, parent=None, nav=None):\nnav - the \"local\" EnviNavMixin instance\n'''\nif va == None:\n- try:\nva = vw.parseExpression(expr)\n- except Exception, e:\n- sys.excepthook(*sys.exc_info())\nif expr == None:\nexpr = '0x%.8x' % va\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
residue from a separate delta.
|
718,770 |
20.08.2018 15:05:51
| 14,400 |
dc82d6c604406a0c8b173bf6eabf9099ea1b6b0f
|
added .readMemString() to envi.MemoryObject, to efficiently scrape a string out of a memory map.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -475,6 +475,36 @@ class MemoryObject(IMemory):\noff, b = self.getByteDef(va)\nreturn self.imem_archs[ (arch & envi.ARCH_MASK) >> 16 ].archParseOpcode(b, off, va)\n+ def readMemString(self, va, maxlen=0xfffffff):\n+ '''\n+ Returns a C-style string from memory. Stops at Memory Map boundaries, or the first NULL (\\x00) byte.\n+ '''\n+\n+ for mva, mmaxva, mmap, mbytes in self._map_defs:\n+ if va >= mva and va < mmaxva:\n+ mva, msize, mperms, mfname = mmap\n+ if not mperms & MM_READ:\n+ raise envi.SegmentationViolation(va)\n+ offset = va - mva\n+\n+ # now find the end of the string based on either \\x00, maxlen, or end of map\n+ end = mbytes.find('\\x00', offset)\n+\n+ left = end - offset\n+ if end == -1:\n+ # couldn't find the NULL byte\n+ mend = offset + maxlen\n+ cstr = mbytes[offset:mend]\n+ else:\n+ # couldn't find the NULL byte go to the end of the map or maxlen\n+ mend = offset + (maxlen, left)[left < maxlen]\n+ cstr = mbytes[offset:mend]\n+ return cstr\n+\n+ raise envi.SegmentationViolation(va)\n+\n+\n+\nclass MemoryFile:\n'''\nA file like object to wrap around a memory object.\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
added .readMemString() to envi.MemoryObject, to efficiently scrape a string out of a memory map.
|
718,770 |
20.08.2018 15:30:40
| 14,400 |
a1cde836328622dd10e6b36699246c2e61e186c7
|
catching a few exceptions. is there a reason the PyQt4 version caught these exceptions while PyQt5 version crashes?
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -491,6 +491,7 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\n@idlethread\ndef _renderMemory(self):\n+ try:\nexpr = str(self.addr_entry.text())\nif not expr:\n@@ -517,6 +518,8 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\nself.updateWindowTitle()\nself._renderDoneSignal.emit()\n+ except Exception, e:\n+ print e\ndef loadDefaultRenderers(self):\nvivrend = viv_rend.WorkspaceRenderer(self.vw)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/symboliks.py",
"new_path": "vivisect/qt/symboliks.py",
"diff": "@@ -222,7 +222,11 @@ class VivSymbolikFuncPane(e_q_memory.EnviNavMixin, vq_save.SaveableWidget, QWidg\ndef symPathSelected(self, emu, effects):\nself.curemu = emu\nself.cureffects = effects\n+ try:\nself.rendSymbolikPath()\n+ except Exception, e:\n+ import sys\n+ sys.excepthook(*sys.exc_info())\ndef rendSymbolikPath(self, *args, **kwargs):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
catching a few exceptions. is there a reason the PyQt4 version caught these exceptions while PyQt5 version crashes?
|
718,770 |
20.08.2018 16:13:54
| 14,400 |
3966409b0e6015e1f944ce0465d1fdc712e6049e
|
typo bugfixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1565,7 +1565,7 @@ def p_vstr(opval, va):\nrbase = (\"s%d\",\"d%d\")[sz]\nopers = (\nArmRegOper(rctx.getRegisterIndex(rbase % vd)),\n- ArmImmOffsetOper(rn, imm, va, pudwl=pudwl)\n+ ArmImmOffsetOper(rn, imm, va, pubwl=pudwl)\n)\nreturn INS_VSTR, 'vstr', opers, 0, 0\n@@ -1622,7 +1622,7 @@ def p_vldr(opval, va):\nrbase = (\"s%d\",\"d%d\")[sz]\nopers = (\nArmRegOper(rctx.getRegisterIndex(rbase % vd)),\n- ArmImmOffsetOper(rn, imm, va, pudwl=pudwl)\n+ ArmImmOffsetOper(rn, imm, va, pubwl=pudwl)\n)\nreturn INS_VLDR, 'vldr', opers, 0, simdflags\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
typo bugfixes
|
718,770 |
21.08.2018 22:38:14
| 14,400 |
6f6388c65a663b8940b8e5998707572d9583c8bf
|
bugfixes and minor cleanup
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -630,6 +630,8 @@ def p_load_store_word_ubyte(opval, va, psize=4):\nArmRegOper(Rd, va=va),\nArmScaledOffsetOper(Rn, Rm, shtype, shval, va, pubwl, psize=psize) # u=-/+, b=word/byte\n)\n+ if Rd == REG_PC:\n+ iflags |= envi.IF_BRANCH\nmnem, opcode = ldr_mnem[pubwl&1]\nreturn (opcode, mnem, olist, iflags, 0)\n@@ -886,6 +888,9 @@ def p_load_imm_off(opval, va, psize=4):\niflags = IF_B\nif (pubwl & 0x12) == 2:\niflags |= IF_T\n+ if Rd == REG_PC:\n+ iflags |= envi.IF_BRANCH\n+\nif (opval & 0xfff0fff) == 0x52D0004:\nmnem = \"push\"\nolist = (\n@@ -952,7 +957,7 @@ def p_media(opval, va):\nmedia_parsers_tmp[4] = p_media_usada\nmedia_parsers_tmp[5] = p_media_sbfx\nmedia_parsers_tmp[6] = p_media_bf\n- media_parsers_tmp[7] = p_media_smul\n+ #media_parsers_tmp[7] = p_media_smul\nmedia_parsers = tuple(media_parsers_tmp)\nmedia_codes = (\n@@ -3773,7 +3778,7 @@ class ArmOpcode(envi.Opcode):\noperval = oper.getOperValue(self, emu)\nif self.opcode in (INS_BLX, INS_BX):\n- if operval & 3:\n+ if operval != None and operval & 3:\nflags |= envi.ARCH_THUMB\noperval &= -2\nelse:\n@@ -5118,7 +5123,6 @@ class ArmDisasm:\nolist[0].involvesPC() and\n(opcode & 0xffff) not in no_update_Rd ): # FIXME: only want IF_NOFALL if it *writes* to PC!\n- showop = True\nflags |= envi.IF_NOFALL\nelse:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfixes and minor cleanup
|
718,770 |
21.08.2018 22:39:28
| 14,400 |
70a09fc0268fb0d97a72e21e2ad5686d6b8b545f
|
arm elf plt tables use addition to calculate the got address. engage special arm emulator-based plt analysis!
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -82,6 +82,7 @@ def addAnalysisModules(vw):\nelif arch == 'arm':\nvw.addVaSet('thunk_reg', ( ('fva', vivisect.VASET_ADDRESS), ('reg', vivisect.VASET_INTEGER), ))\nvw.addFuncAnalysisModule('vivisect.analysis.arm.thunk_reg')\n+ vw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\nvw.addAnalysisModule(\"vivisect.analysis.generic.funcentries\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.relocations\")\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "vivisect/analysis/arm/elfplt.py",
"diff": "+\"\"\"\n+If a \"function\" is in the plt it's a wrapper for something in the GOT.\n+Make that apparent.\n+\"\"\"\n+\n+import vivisect\n+import envi\n+import envi.archs.i386 as e_i386\n+import envi.archs.i386.opcode86 as opcode86\n+\n+def analyze(vw):\n+ \"\"\"\n+ Do simple linear disassembly of the .plt section if present.\n+ \"\"\"\n+ for sva,ssize,sname,sfname in vw.getSegments():\n+ if sname != \".plt\":\n+ continue\n+ nextva = sva + ssize\n+ while sva < nextva:\n+ vw.makeCode(sva)\n+ ltup = vw.getLocation(sva)\n+ sva += ltup[vivisect.L_SIZE]\n+\n+\n+MAX_INSTR_COUNT = 3\n+\n+def analyzeFunction(vw, funcva):\n+ #global emu, op, oper0, opval\n+ #try:\n+ seg = vw.getSegment(funcva)\n+ if seg == None:\n+ return\n+\n+ segva, segsize, segname, segfname = seg\n+\n+ if segname not in (\".plt\", \".plt.got\"):\n+ return\n+ #print \"ARM EMU-PLT: %x\" % funcva\n+\n+ emu = vw.getEmulator()\n+ emu.setProgramCounter(funcva)\n+ offset = 0\n+ branch = False\n+ for cnt in range(MAX_INSTR_COUNT):\n+ op = vw.parseOpcode(funcva + offset)\n+ if op.iflags & envi.IF_BRANCH == 0:\n+ emu.executeOpcode(op)\n+ offset += len(op)\n+ #print \"skip->\", hex(emu.getProgramCounter())\n+ continue\n+ branch = True\n+ break\n+\n+ if not branch:\n+ return\n+\n+ #print \"got branch\"\n+ loctup = None\n+ oper1 = op.opers[1]\n+ #print oper1\n+ opval = oper1.getOperAddr(op, emu=emu)\n+ #raw_input(\"ASDFASDF\")\n+ #if opval == None:\n+ #print op, hex(op.va), (opval)\n+ #else:\n+ #print op, hex(op.va), hex(opval)\n+ loctup = vw.getLocation(opval)\n+ #raw_input( loctup)\n+\n+ if loctup == None:\n+ return\n+\n+ if loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT: # FIXME: Why are AMD64 IMPORTS showing up as POINTERs?\n+ print \"0x%x: \" % funcva, loctup[vivisect.L_LTYPE], ' != ', vivisect.LOC_IMPORT\n+ #return\n+\n+ gotname = vw.getName(opval)\n+ #print hex(opval), gotname\n+ tinfo = gotname\n+ #vw.makeName(funcva, \"plt_%s\" % fname, filelocal=True)\n+ vw.makeFunctionThunk(funcva, tinfo)\n+\n+ #except Exception, e:\n+ #print e\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm elf plt tables use addition to calculate the got address. engage special arm emulator-based plt analysis!
|
718,770 |
21.08.2018 22:43:18
| 14,400 |
cf23da10d8108f4769cf111a38091669fb448d5c
|
cleanup arm thunk_reg output (only display if verbose==True)
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -159,9 +159,9 @@ def analyzeFunction(vw, fva, prepend=False):\ncmt = \"0x%x: %s ;\\n %s\" % (tgt, reprPointer(vw, tgt), curcmt)\nvw.setComment(va, cmt)\n- vw.vprint(\"PIE XREF: %x %s\" % (va, cmt))\n+ if vw.verbose: vw.vprint(\"PIE XREF: %x %s\" % (va, cmt))\n- vw.vprint(\"ANOMS: \\n\", repr(emumon.emuanom))\n+ if vw.verbose: vw.vprint(\"ANOMS: \\n\", repr(emumon.emuanom))\ndef analyze(vw):\n# don't want to run this multiple times on the same function... comments get outa hand.\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup arm thunk_reg output (only display if verbose==True)
|
718,770 |
30.08.2018 10:34:39
| 14,400 |
0e35c212bf4ba845b0990d23317a4a7fd4151953
|
thumb support wrapped into ELF parser and analysis modules (thumb-architecture, not the thumb part of arm... ie. Cortex-M series processors)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -25,7 +25,7 @@ arch_names = {\nARCH_AMD64: 'amd64',\nARCH_ARMV7: 'arm',\nARCH_THUMB16: 'thumb16',\n- ARCH_THUMB: 'thumb2',\n+ ARCH_THUMB: 'thumb',\nARCH_MSP430: 'msp430',\nARCH_H8: 'h8',\n}\n@@ -38,6 +38,7 @@ arch_by_name = {\n'armv6l': ARCH_ARMV7,\n'armv7l': ARCH_ARMV7,\n'thumb16': ARCH_THUMB16,\n+ 'thumb': ARCH_THUMB,\n'thumb2': ARCH_THUMB,\n'msp430': ARCH_MSP430,\n'h8': ARCH_H8,\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -322,6 +322,7 @@ iencs = (\\\n'IENC_COPROC_LOAD', # Coprocessor load/store and double reg xfers\n'IENC_COPROC_DP', # Coprocessor data processing\n'IENC_COPROC_REG_XFER', # Coprocessor register transfers\n+ 'IENC_COPROC_SIMD', # Coprocessor SIMD\n'IENC_MCR', # Move to Corprocessor from ARM Regs and vice versa\n'IENC_SWINT', # Sofware interrupts\n'IENC_UNCOND', # unconditional wacko instructions\n@@ -397,10 +398,19 @@ instrnames = [\n'MOVT',\n'MOVW',\n'LDR',\n+ 'LDRH',\n+ 'LDRB',\n+ 'LDRD',\n+ 'LDREX',\n+ 'LDRSB',\n+ 'LDRSH',\n'LDREX',\n'LDM',\n'STR',\n'STREX',\n+ 'STRH',\n+ 'STRB',\n+ 'STRD',\n'STM',\n'STC',\n'STC2',\n@@ -466,8 +476,6 @@ instrnames = [\n'VQRSHRUN',\n'VSHLL',\n'VCVT',\n- #'LDRB',\n- #'STRB',\n'MUL',\n'SMUL',\n'MUL',\n@@ -523,12 +531,10 @@ instrnames = [\n'CPS',\n'CBZ',\n'CBNZ',\n- 'STRH',\n- #'LDRH',\n'LEAVEX',\n'ENTERX',\n- 'TB',\n- 'LDREX',\n+ 'TBB',\n+ 'TBH',\n'ORN',\n'PKH',\n'LSL',\n@@ -546,7 +552,6 @@ instrnames = [\n'DMB',\n'DSB',\n'ISB',\n- #'LDRSB',\n'USAD8',\n'USADA8',\n'PLD',\n@@ -731,6 +736,7 @@ instrnames = [\n'SETEND',\n'RFE',\n'SRS',\n+ 'HINT',\n]\nins_index = 85\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -31,7 +31,7 @@ def addAnalysisModules(vw):\nvw.addImpApi('windows','amd64')\nvw.addStructureModule('ntdll', 'vstruct.defs.windows.win_6_1_amd64.ntdll')\n- elif arch == 'arm':\n+ elif arch in ('arm', 'thumb2'):\nvw.addImpApi('windows','arm')\nvw.addConstModule('vstruct.constants.ntstatus')\n@@ -57,7 +57,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch == 'arm':\n+ elif arch in ('arm', 'thumb2'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n# See if we got lucky and got arg/local hints from symbols\n@@ -79,7 +79,7 @@ def addAnalysisModules(vw):\n# add va set for tracking thunk_bx function(s)\nvw.addVaSet('thunk_bx', ( ('fva', vivisect.VASET_ADDRESS), ) )\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.thunk_bx\")\n- elif arch == 'arm':\n+ elif arch in ('arm', 'thumb2'):\nvw.addVaSet('thunk_reg', ( ('fva', vivisect.VASET_ADDRESS), ('reg', vivisect.VASET_INTEGER), ))\nvw.addFuncAnalysisModule('vivisect.analysis.arm.thunk_reg')\nvw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\n@@ -100,7 +100,7 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch == 'arm':\n+ elif arch in ('arm', 'thumb2'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n# Find import thunks\n@@ -128,7 +128,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch == 'arm':\n+ elif arch in ('arm', 'thumb2'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n@@ -143,7 +143,7 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\n- if arch == 'arm':\n+ if arch in ('arm', 'thumb2'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.impapi\")\n@@ -156,7 +156,7 @@ def addAnalysisModules(vw):\n#vw.addAnalysisModule(\"vivisect.analysis.generic.pointertables\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.emucode\")\n- if arch == 'arm':\n+ if arch in ('arm', 'thumb2'):\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -217,7 +217,6 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\n#except:\n# sys.excepthook(*sys.exc_info())\n-\nclass ThumbWorkspaceEmulator(ArmWorkspaceEmulator):\ndef __init__(self, vw, logwrite=False, logread=False):\nArmWorkspaceEmulator.__init__(self, vw, logwrite, logread)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -83,6 +83,7 @@ archcalls = {\n'i386':'cdecl',\n'amd64':'sysvamd64call',\n'arm':'armcall',\n+ 'thumb':'armcall',\n}\ndef loadElfIntoWorkspace(vw, elf, filename=None):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
thumb support wrapped into ELF parser and analysis modules (thumb-architecture, not the thumb part of arm... ie. Cortex-M series processors)
|
718,770 |
30.08.2018 10:37:20
| 14,400 |
0463eb98f631747fc0807a5ac4bdce1a0fb6507c
|
basics of Thumb switchcases (TBH/TBB) analysis wrapped in. still refinement necessary. perhaps migrate this analysis into getbranches(emu) if that does the trick...
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -3,6 +3,7 @@ import sys\nimport vivisect\nimport vivisect.impemu as viv_imp\nimport vivisect.impemu.monitor as viv_monitor\n+import vivisect.analysis.generic.codeblocks as viv_cb\nimport envi\nimport envi.archs.arm as e_arm\n@@ -24,6 +25,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nself.strictops = False\nself.returns = False\nself.infloops = []\n+ self.switchcases = 0\ndef prehook(self, emu, op, starteip):\n@@ -51,8 +53,14 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nif hasattr(op.opers, 'imm'):\nself.retbytes = op.opers[0].imm\n- if op.opcode == INS_TB:\n- analyzeTB(emu, op, starteip, self)\n+ # ARM gives us nice switchcase handling instructions\n+ ##### FIXME: wrap TB-handling into getBranches(emu) which is called by checkBranches during emulation\n+ if op.opcode in (INS_TBH, INS_TBB):\n+ if emu.vw.getVaSetRow('SwitchCases', op.va) == None:\n+ base, tbl = analyzeTB(emu, op, starteip, self)\n+ count = len(tbl)\n+ self.switchcases += 1\n+ emu.vw.setVaSetRow('SwitchCases', (op.va, op.va, count) )\nif op.opcode == INS_MOV:\nif len(op.opers) >= 2:\n@@ -95,9 +103,6 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nemu.setFlag(PSR_T_bit, self.last_tmode)\n-def analyzeTB(emu, op, starteip, amon):\n- print \"TB at 0x%x\" % starteip\n-\nargnames = {\n0: ('r0', 0),\n1: ('r1', 1),\n@@ -140,16 +145,13 @@ def buildFunctionApi(vw, fva, emu, emumon):\nreturn api\ndef analyzeFunction(vw, fva):\n- #raw_input( \"= 0x%x viv.analysis.arm.emulation... =\" % (fva))\n#print( \"= 0x%x viv.analysis.arm.emulation... =\" % (fva))\nemu = vw.getEmulator()\nemumon = AnalysisMonitor(vw, fva)\n-\nemu.setEmulationMonitor(emumon)\nloc = vw.getLocation(fva)\n-\nif loc != None:\nlva, lsz, lt, lti = loc\nif lt == LOC_OP:\n@@ -186,5 +188,89 @@ def analyzeFunction(vw, fva):\n# handle infinite loops (actually, while 1;)\n+ # switch-cases may have updated codeflow. reanalyze\n+ viv_cb.analyzeFunction(vw, fva)\n+\n+\n# TODO: incorporate some of emucode's analysis but for function analysis... if it makes sense.\n+\n+\n+def analyzeTB(emu, op, starteip, amon):\n+ ######################### FIXME: ADD THIS TO getBranches(emu)\n+ ### DEBUGGING\n+ #raw_input(\"\\n\\n\\nPRESS ENTER TO START TB: 0x%x\" % op.va)\n+ print \"\\n\\nTB at 0x%x\" % starteip\n+ tsize = op.opers[0].tsize\n+ tbl = []\n+ basereg = op.opers[0].base_reg\n+ if basereg != REG_PC:\n+ base = emu.getRegister(basereg)\n+ else:\n+ base = op.opers[0].va\n+\n+ print(\"\\nbase: 0x%x\" % base)\n+ val0 = emu.readMemValue(base, tsize)\n+\n+ if val0 > 0x100 + base:\n+ print \"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\"\n+\n+ va = base\n+ while va < base + val0:\n+ nextoff = emu.readMemValue(va, tsize) * 2\n+ print \"0x%x: -> 0x%x\" % (va, nextoff + base)\n+ if nextoff == 0:\n+ print \"Terminating TB at 0-offset\"\n+ break\n+\n+ if nextoff > 0x500:\n+ print \"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nextoff\n+ break\n+\n+ loc = emu.vw.getLocation(va)\n+ if loc != None:\n+ print \"Terminating TB at Location/Reference\"\n+ print \"%x, %d, %x, %r\" % loc\n+ break\n+\n+ tbl.append((va, nextoff))\n+ va += tsize\n+ #sys.stderr.write('.')\n+\n+ print \"%s: \\n\\t\"%op.mnem + '\\n\\t'.join(['0x%x (0x%x)' % (x, base + x) for v,x in tbl])\n+\n+ ###\n+ # for workspace emulation analysis, let's check the index register for sanity.\n+ idxreg = op.opers[0].offset_reg\n+ idx = emu.getRegister(idxreg)\n+ if idx > 0x40000000:\n+ emu.setRegister(idxreg, 0) # args handed in can be replaced with index 0\n+\n+ jmptblbase = op.opers[0]._getOperBase(emu)\n+ jmptblval = emu.getOperAddr(op, 0)\n+ jmptbltgt = (emu.getOperValue(op, 0) * 2) + base\n+ print \"0x%x: %r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\" % (op.va, op, jmptblbase, jmptblval, jmptbltgt)\n+ #raw_input(\"PRESS ENTER TO CONTINUE\")\n+\n+ # make numbers and xrefs and names\n+ emu.vw.addXref(op.va, base, REF_DATA)\n+\n+ case = 0\n+ for ova, nextoff in tbl:\n+ nexttgt = base + nextoff\n+ emu.vw.makeNumber(ova, 2)\n+ # check for loc first?\n+ emu.vw.makeCode(nexttgt)\n+ # check xrefs fist?\n+ emu.vw.addXref(op.va, nexttgt, REF_CODE)\n+\n+ curname = emu.vw.getName(nexttgt)\n+ if curname == None:\n+ emu.vw.makeName(nexttgt, \"case_%x_%x_%x\" % (case, op.va, nexttgt))\n+ else:\n+ emu.vw.vprint(\"case_%x_%x_%x conflicts with existing name: %r\" % (case, op.va, nexttgt, curname))\n+\n+ case += 1\n+\n+ return base, tbl\n+\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/emucode.py",
"new_path": "vivisect/analysis/generic/emucode.py",
"diff": "@@ -87,7 +87,8 @@ class watcher(viv_imp_monitor.EmulationMonitor):\nva, size, ltype, linfo = loc\nif ltype != vivisect.LOC_OP:\nemu.stopEmu()\n- raise Exception(\"HIT %d AT %.8x\" % (ltype, va))\n+ raise Exception(\"HIT LOCTYPE %d AT %.8x\" % (ltype, va))\n+\ncnt = self.mndist.get(op.mnem, 0)\nself.mndist[ op.mnem ] = cnt+1\nself.insn_count += 1\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
basics of Thumb switchcases (TBH/TBB) analysis wrapped in. still refinement necessary. perhaps migrate this analysis into getbranches(emu) if that does the trick...
|
718,770 |
30.08.2018 10:42:04
| 14,400 |
cbf66e67319ec8b5101bb639cf12fb29a052f81e
|
searchopcodes is a viv cli tool which allows more flexible searching either within a function or in the entire workspace for numbers or text or regex.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/cli.py",
"new_path": "vivisect/cli.py",
"diff": "The vivisect CLI.\n\"\"\"\n+import shlex\nimport pprint\nimport socket\nfrom getopt import getopt\n@@ -12,6 +13,7 @@ import vivisect.vamp as viv_vamp\nimport vivisect.impemu as viv_imp\nimport vivisect.vector as viv_vector\nimport vivisect.reports as viv_reports\n+import vivisect.tools.graphutil as viv_graph\n# FIXME modular arch specific commands!\nimport vivisect.symboliks as viv_symb\n@@ -28,9 +30,12 @@ import vdb\nimport envi\nimport envi.cli as e_cli\n+import envi.memory as e_mem\nimport envi.expression as e_expr\n+import envi.memcanvas as e_canvas\nimport envi.memcanvas.renderers as e_render\n+from vqt.main import vqtevent\nfrom vivisect.const import *\nclass VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\n@@ -217,6 +222,164 @@ class VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\n\"\"\"\npass\n+ def do_searchopcodes(self, line):\n+ '''\n+ search opcodes/function for a pattern\n+\n+ search [-f <funcva>] [options] <pattern>\n+ -f [fva] - focus on one function\n+ -c - search comments\n+ -o - search operands\n+ -t - search text\n+ -M <color> - mark opcodes (default = orange)\n+ -R - pattern is REGEX (otherwise just text)\n+\n+ '''\n+ parser = e_cli.VOptionParser()\n+ parser.add_option('-f', action='store', dest='funcva', type='long')\n+ parser.add_option('-c', action='store_true', dest='searchComments')\n+ parser.add_option('-o', action='store_true', dest='searchOperands')\n+ parser.add_option('-t', action='store_true', dest='searchText')\n+ parser.add_option('-M', action='store', dest='markColor', default='orange')\n+ parser.add_option('-R', action='store_true', dest='is_regex')\n+\n+ argv = shlex.split(line)\n+ try:\n+ options, args = parser.parse_args(argv)\n+ except Exception as e:\n+ self.vprint(repr(e))\n+ return self.do_help('searchopcodes')\n+\n+ pattern = ' '.join(args)\n+ if len(pattern) == 0:\n+ self.vprint('you must specify a pattern')\n+ return self.do_help('search')\n+\n+ vw = self\n+\n+ # generate our interesting va list\n+ valist = []\n+ if options.funcva:\n+ # setup valist from function data\n+ try:\n+ fva = int(args[0], 0)\n+ graph = viv_graph.buildFunctionGraph(vw, fva)\n+ except Exception, e:\n+ self.vprint(repr(e))\n+ return\n+\n+ for nva, node in graph.getNodes():\n+ va = nva\n+ endva = va + node.get('cbsize')\n+ while va < endva:\n+ lva, lsz, ltype, ltinfo = vw.getLocation(va)\n+ valist.append(va)\n+ va += lsz\n+\n+ else:\n+ # the whole workspace is our oyster\n+ valist = [va for va, lvsz, ltype, ltinfo in vw.getLocations(LOC_OP)]\n+\n+ res = []\n+ canv = e_canvas.StringMemoryCanvas(vw)\n+\n+ try:\n+ defaultSearchAll = True\n+ for va in valist:\n+ addthis = False\n+ op = vw.parseOpcode(va)\n+ #print op\n+ # search comment\n+ if options.searchComments:\n+ defaultSearchAll = False\n+ cmt = vw.getComment(va)\n+ if cmt != None:\n+ #print \"\\t %r\" % cmt\n+ if options.is_regex:\n+ if len(re.findall(pattern, cmt)):\n+ addthis = True\n+\n+ else:\n+ if pattern in cmt:\n+ addthis = True\n+\n+ # search operands\n+ if options.searchOperands:\n+ defaultSearchAll = False\n+ for opidx in range(len(op.opers)):\n+ # we're writing to a temp canvas, so clear it before each test\n+ canv.clearCanvas()\n+ oper = op.opers[opidx]\n+ oper.render(canv, op, opidx)\n+ operepr = canv.strval\n+ #print \"\\t %r\" % operepr\n+ if options.is_regex:\n+ if len(re.findall(pattern, operepr)):\n+ addthis = True\n+\n+ else:\n+ if pattern in operepr:\n+ addthis = True\n+\n+ # if we're doing non-regex, let's test against real numbers (instead of converting to hex and back)\n+ numpattrn = pattern\n+ try:\n+ numpattrn = int(numpattrn, 0)\n+ except:\n+ pass\n+\n+ #print \"\\t %r\" % vars(oper).values()\n+ if numpattrn in vars(oper).values():\n+ addthis = True\n+\n+ # search full text\n+ if options.searchText or defaultSearchAll:\n+ canv.clearCanvas()\n+ op.render(canv)\n+ oprepr = canv.strval\n+ #print \"\\t %r\" % oprepr\n+ if options.is_regex:\n+ if len(re.findall(pattern, oprepr)):\n+ addthis = True\n+\n+ else:\n+ if pattern in oprepr:\n+ addthis = True\n+\n+ # only want one listing of each va, no matter how many times it matches\n+ if addthis:\n+ res.append(va)\n+\n+ except Exception, e:\n+ import sys\n+ sys.excepthook(*sys.exc_info())\n+\n+ if len(res) == 0:\n+ self.vprint('pattern not found: %s (%s)' % (pattern.encode('hex'), repr(pattern)))\n+ return\n+\n+ # set the color for each finding\n+ color = options.markColor\n+ colormap = { va : color for va in res }\n+ if vw._viv_gui != None:\n+ vqtevent('viv:colormap', colormap)\n+\n+ self.vprint('matches for: %s (%s)' % (pattern.encode('hex'), repr(pattern)))\n+ for va in res:\n+ mbase,msize,mperm,mfile = self.memobj.getMemoryMap(va)\n+ pname = e_mem.reprPerms(mperm)\n+ sname = self.reprPointer(va)\n+\n+ op = vw.parseOpcode(va)\n+ self.canvas.renderMemory(va, len(op))\n+ cmt = self.getComment(va)\n+ if cmt != None:\n+ self.canvas.addText('\\t\\t; %s' % cmt)\n+\n+ self.canvas.addText('\\n')\n+\n+ self.vprint('done (%d results).' % len(res))\n+\ndef do_imports(self, line):\n\"\"\"\nShow the imports in the workspace (or potentially just one file)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
searchopcodes is a viv cli tool which allows more flexible searching either within a function or in the entire workspace for numbers or text or regex.
|
718,770 |
30.08.2018 10:43:43
| 14,400 |
df2fd0eed374a6f6a972c598d8e68082d0239392
|
don't segv on exceptions within Qt-called functions. i'm still unsure why the Qt5 version crashes for the Qt4 version would handle the exceptions gracefully and keep going.
|
[
{
"change_type": "MODIFY",
"old_path": "vqt/main.py",
"new_path": "vqt/main.py",
"diff": "@@ -163,7 +163,10 @@ def workerThread():\nif func == None:\nreturn\n+ try:\nfunc(*args,**kwargs)\n+ except:\n+ sys.excepthook(*sys.exc_info())\nexcept Exception, e:\nprint('vqt worker warning: %s' % e)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
don't segv on exceptions within Qt-called functions. i'm still unsure why the Qt5 version crashes for the Qt4 version would handle the exceptions gracefully and keep going.
|
718,770 |
30.08.2018 12:05:54
| 14,400 |
ecc52b80f98568b9db8854f22326e5e85b184d81
|
clean up some print statements, and add name to branch table.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -200,7 +200,7 @@ def analyzeTB(emu, op, starteip, amon):\n######################### FIXME: ADD THIS TO getBranches(emu)\n### DEBUGGING\n#raw_input(\"\\n\\n\\nPRESS ENTER TO START TB: 0x%x\" % op.va)\n- print \"\\n\\nTB at 0x%x\" % starteip\n+ if emu.vw.verbose: print \"\\n\\nTB at 0x%x\" % starteip\ntsize = op.opers[0].tsize\ntbl = []\nbasereg = op.opers[0].base_reg\n@@ -209,7 +209,7 @@ def analyzeTB(emu, op, starteip, amon):\nelse:\nbase = op.opers[0].va\n- print(\"\\nbase: 0x%x\" % base)\n+ if emu.vw.verbose: print(\"\\nbase: 0x%x\" % base)\nval0 = emu.readMemValue(base, tsize)\nif val0 > 0x100 + base:\n@@ -218,25 +218,26 @@ def analyzeTB(emu, op, starteip, amon):\nva = base\nwhile va < base + val0:\nnextoff = emu.readMemValue(va, tsize) * 2\n- print \"0x%x: -> 0x%x\" % (va, nextoff + base)\n+ if emu.vw.verbose: print \"0x%x: -> 0x%x\" % (va, nextoff + base)\nif nextoff == 0:\n- print \"Terminating TB at 0-offset\"\n+ if emu.vw.verbose: print \"Terminating TB at 0-offset\"\nbreak\nif nextoff > 0x500:\n- print \"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nextoff\n+ if emu.vw.verbose: print \"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nextoff\nbreak\nloc = emu.vw.getLocation(va)\nif loc != None:\n- print \"Terminating TB at Location/Reference\"\n- print \"%x, %d, %x, %r\" % loc\n+ if emu.vw.verbose: print \"Terminating TB at Location/Reference\"\n+ if emu.vw.verbose: print \"%x, %d, %x, %r\" % loc\nbreak\ntbl.append((va, nextoff))\nva += tsize\n#sys.stderr.write('.')\n+ if emu.vw.verbose:\nprint \"%s: \\n\\t\"%op.mnem + '\\n\\t'.join(['0x%x (0x%x)' % (x, base + x) for v,x in tbl])\n###\n@@ -249,11 +250,13 @@ def analyzeTB(emu, op, starteip, amon):\njmptblbase = op.opers[0]._getOperBase(emu)\njmptblval = emu.getOperAddr(op, 0)\njmptbltgt = (emu.getOperValue(op, 0) * 2) + base\n+ if emu.vw.verbose:\nprint \"0x%x: %r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\" % (op.va, op, jmptblbase, jmptblval, jmptbltgt)\n#raw_input(\"PRESS ENTER TO CONTINUE\")\n# make numbers and xrefs and names\nemu.vw.addXref(op.va, base, REF_DATA)\n+ emu.vw.makeName(op.va, 'br_tbl_%x' % op.va)\ncase = 0\nfor ova, nextoff in tbl:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
clean up some print statements, and add name to branch table.
|
718,770 |
31.08.2018 09:39:21
| 14,400 |
c23335ffdfde8cfe5389ada890acdbb0dfc327ee
|
dramatic improvements on SIMD decoding. still work to be done.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -527,6 +527,7 @@ instrnames = [\n'YIELD',\n'WFE',\n'WFI',\n+ 'WFR',\n'SEV',\n'CPS',\n'CBZ',\n@@ -664,11 +665,6 @@ instrnames = [\n'UXTH',\n'SDIV',\n'UDIV',\n- 'NOP',\n- 'YIELD',\n- 'WFE',\n- 'WFI',\n- 'SEV',\n'SWP',\n'SWPB',\n'SEL',\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -562,11 +562,24 @@ def cps16(va, value):\n)\nreturn COND_AL,opers, (IF_IE, IF_ID)[im]\n-def itblock(va, val):\n+it_hints_others = (\n+ (INS_NOP, 'nop'),\n+ (INS_YIELD, 'yield'),\n+ (INS_WFR, 'wfr'),\n+ (INS_WFI, 'wfi'),\n+ (INS_SEV, 'sev'),\n+ )\n+\n+def it_hints(va, val):\nmask = val & 0xf\nfirstcond = (val>>4) & 0xf\n+ if mask != 0:\n+ # this is the IT instruction\nreturn COND_AL,(ThumbITOper(mask, firstcond),), None\n+ opcode, mnem = it_hints_others[firstcond]\n+\n+ return COND_AL, (), 0, opcode, mnem\nit_strs_0 = ['']\n@@ -858,6 +871,25 @@ def shift_or_ext_32(va, val1, val2):\nrm = (val2 & 0xf)\nflags = 0\n+ if (op1 & 0b1000): # page 245\n+ if not (op2 & 0b1100):\n+ # parallel addition/subtraction: signed\n+ raise InvalidInstruction(\n+ mesg=\"shift_or_ext_32 implementme: parallel add/sub signed\",\n+ bytez=struct.pack(\"<H\", val1)+struct.pack(\"<H\", val2), va=va)\n+\n+ elif not (op2 & 0b1000):\n+ # parallel addition/subtraction: unsigned\n+ raise InvalidInstruction(\n+ mesg=\"shift_or_ext_32 implementme: parallel add/sub unsigned\",\n+ bytez=struct.pack(\"<H\", val1)+struct.pack(\"<H\", val2), va=va)\n+\n+ elif (op1 & 0b1100) == 0b1000 and (op2 & 0b1100) == 0b1000:\n+ # misc instructions\n+ raise InvalidInstruction(\n+ mesg=\"shift_or_ext_32 implementme: misc instructions\",\n+ bytez=struct.pack(\"<H\", val1)+struct.pack(\"<H\", val2), va=va)\n+\nif (op2):\nif op1 > 5:\nraise InvalidInstruction(\n@@ -914,15 +946,97 @@ def shift_or_ext_32(va, val1, val2):\nreturn COND_AL, opcode, mnem, opers, flags, 0\n+parallel_misc_info = (\n+ {\n+ 0b000: (INS_UADD8, 'uadd8', IF_THUMB32),\n+ 0b001: (INS_UADD16, 'uadd16', IF_THUMB32),\n+ 0b010: (INS_UASX, 'uasx', IF_THUMB32),\n+ 0b110: (INS_USAX, 'usax', IF_THUMB32),\n+ 0b101: (INS_USUB16, 'usub16', IF_THUMB32),\n+ 0b100: (INS_USUB8, 'usub8', IF_THUMB32),\n+\n+ 0b1000: (INS_UQADD8, 'uqadd8', IF_THUMB32),\n+ 0b1001: (INS_UQADD16, 'uqadd16', IF_THUMB32),\n+ 0b1010: (INS_UQASX, 'uqasx', IF_THUMB32),\n+ 0b1110: (INS_UQSAX, 'uqsax', IF_THUMB32),\n+ 0b1101: (INS_UQSUB16, 'uqsub16', IF_THUMB32),\n+ 0b1100: (INS_UQSUB8, 'uqsub8', IF_THUMB32),\n+\n+ 0b10000: (INS_UHADD8, 'uhadd8', IF_THUMB32),\n+ 0b10001: (INS_UHADD16, 'uhadd16', IF_THUMB32),\n+ 0b10010: (INS_UHASX, 'uhasx', IF_THUMB32),\n+ 0b10110: (INS_UHSAX, 'uhsax', IF_THUMB32),\n+ 0b10101: (INS_UHSUB16, 'uhsub16', IF_THUMB32),\n+ 0b10100: (INS_UHSUB8, 'uhsub8', IF_THUMB32),\n+ },\n+ {\n+ 0b000: (INS_SADD8, 'sadd8', IF_THUMB32),\n+ 0b001: (INS_SADD16, 'sadd16', IF_THUMB32),\n+ 0b010: (INS_SASX, 'sasx', IF_THUMB32),\n+ 0b110: (INS_SSAX, 'ssax', IF_THUMB32),\n+ 0b101: (INS_SSUB16, 'ssub16', IF_THUMB32),\n+ 0b100: (INS_SSUB8, 'ssub8', IF_THUMB32),\n+\n+ 0b1000: (INS_QADD8, 'qadd8', IF_THUMB32),\n+ 0b1001: (INS_QADD16, 'qadd16', IF_THUMB32),\n+ 0b1010: (INS_QASX, 'qasx', IF_THUMB32),\n+ 0b1110: (INS_QSAX, 'qsax', IF_THUMB32),\n+ 0b1101: (INS_QSUB16, 'qsub16', IF_THUMB32),\n+ 0b1100: (INS_QSUB8, 'qsub8', IF_THUMB32),\n+\n+ 0b10000: (INS_SHADD8, 'shadd8', IF_THUMB32),\n+ 0b10001: (INS_SHADD16, 'shadd16', IF_THUMB32),\n+ 0b10010: (INS_SHASX, 'shasx', IF_THUMB32),\n+ 0b10110: (INS_SHSAX, 'shsax', IF_THUMB32),\n+ 0b10101: (INS_SHSUB16, 'shsub16', IF_THUMB32),\n+ 0b10100: (INS_SHSUB8, 'shsub8', IF_THUMB32),\n+ },\n+ {\n+ 0b00000: (INS_QADD, 'qadd', IF_THUMB32),\n+ 0b01000: (INS_QDADD, 'qdadd', IF_THUMB32),\n+ 0b10000: (INS_QADD, 'qsub', IF_THUMB32),\n+ 0b11000: (INS_QDADD, 'qdsub', IF_THUMB32),\n+\n+ 0b00001: (INS_REV, 'rev', IF_THUMB32),\n+ 0b01001: (INS_REV16, 'rev16', IF_THUMB32),\n+ 0b10001: (INS_RBIT, 'rbit', IF_THUMB32), # rd, rm\n+ 0b11001: (INS_REVSH, 'revsh', IF_THUMB32),\n+\n+ 0b00010: (INS_SEL, 'sel', IF_THUMB32), # rd, rn, rm\n+ 0b00011: (INS_CLZ, 'clz', IF_THUMB32),\n+\n+ },\n+ )\n-def pdp_32(va, val1, val2):\n- # saturated instructions\n- raise Exception(\"Implement Me: pdp32: Saturated Instrs\")\n- pass\n+def parallel_misc_32(va, val1, val2):\n+\n+ # signed/unsigned parallel instructions\n+ opidx = (val1 >> 4) & 7\n+ opidx |= (val2 >> 1) & 0x18\n+ signed_misc = (val2 >> 6) & 3\n+\n+ pardata = parallel_misc_info[signed_misc].get(opidx)\n+\n+ if pardata == None:\n+ return shift_or_ext_32(va, val1, val2)\n+\n+ opcode, mnem, flags = pardata\n+ rn = (val1 & 0xf)\n+ rd = (val2 >> 8) & 0xf\n+ rm = (val2 & 0xf)\n+\n+ opers = (\n+ ArmRegOper(rd),\n+ ArmRegOper(rn),\n+ ArmRegOper(rm),\n+ )\n- return COND_AL, None, None, None, None, None\n+ return COND_AL, opcode, mnem, opers, flags, 0\ndef ubfx_32(va, val1, val2):\n+ if val2 & 0x8000:\n+ return branch_misc(va, val1, val2)\n+\nrd = (val2>>8) & 0xf\nrn = val1 & 0xf\nimm3 = (val2>>12) & 0x7\n@@ -939,10 +1053,10 @@ def ubfx_32(va, val1, val2):\nreturn COND_AL, None, None, opers, None, 0\ndef dp_bin_imm_32(va, val1, val2): # p232\n- flags = IF_THUMB32\nif val2 & 0x8000:\nreturn branch_misc(va, val1, val2)\n+ flags = IF_THUMB32\nRd = (val2 >> 8) & 0xf\nimm4 = val1 & 0xf\n@@ -971,10 +1085,10 @@ def dp_bin_imm_32(va, val1, val2): # p232\nreturn COND_AL, None, None, opers, flags, 0\ndef dp_bfi_imm_32(va, val1, val2): # p232\n- flags = IF_THUMB32\nif val2 & 0x8000:\nreturn branch_misc(va, val1, val2)\n+ flags = IF_THUMB32\nRd = (val2 >> 8) & 0xf\nimm4 = val1 & 0xf\n@@ -1280,14 +1394,70 @@ def smul_32(va, val1, val2):\nrd = (val2 >> 8) & 0xf\nnm = (val2 >> 4) & 0x3\n- mnem = ('smulbb','smulbt','smultb','smultt')[nm]\n+ opcode, mnem = (\n+ (INS_SMULBB, 'smulbb'),\n+ (INS_SMULBT, 'smulbt'),\n+ (INS_SMULTB, 'smultb'),\n+ (INS_SMULTT, 'smultt'))[nm]\nopers = (\nArmRegOper(rd, va=va),\nArmRegOper(rn, va=va),\nArmRegOper(rm, va=va),\n)\n- return COND_AL, None, mnem, opers, None, 0\n+ return COND_AL, opcode, mnem, opers, None, 0\n+\n+\n+smulls_info = {\n+ 0: {0x0: (INS_SMULL, 'smull',) },\n+ 1: {0xf: (INS_SDIV, 'sdiv',) },\n+ 2: {0x0: (INS_UMULL, 'umull',) },\n+ 3: {0xf: (INS_UDIV, 'udiv',) },\n+ 4: {0x0: (INS_SMLAL, 'smlal',),\n+ 0x8: (INS_SMLAL, 'smlalbb',),\n+ 0x9: (INS_SMLAL, 'smlalbt',),\n+ 0xa: (INS_SMLAL, 'smlaltb',),\n+ 0xb: (INS_SMLAL, 'smlaltt',),\n+ 0xc: (INS_SMLALD, 'smlald',),\n+ 0xd: (INS_SMLALDX, 'smlaldx',),\n+ },\n+ 5: {0xc: (INS_SMLSLD, 'smlsld',),\n+ 0xd: (INS_SMLSLDX, 'smlsldx',),\n+ },\n+ 6: {0x0: (INS_UMLAL, 'umlal',),\n+ 0x6: (INS_UMAAL, 'umaal',),\n+ },\n+ }\n+\n+def smull_32(va, val1, val2):\n+ rn = val1 & 0xf\n+ rm = val2 & 0xf\n+ rdhi = (val2 >> 8) & 0xf\n+ rdlo = (val2 >> 12) & 0xf\n+\n+\n+ op1 = (val1 >> 4) & 0x7\n+ op2 = (val2 >> 4) & 0xf\n+\n+ secondary = smulls_info.get(op1)\n+ if secondary == None:\n+ raise envi.InvalidInstruction( #FIXME!!!!\n+ mesg=\"smull invalid decode: op1\",\n+ bytez=bytez[offset:offset+4], va=va)\n+\n+ secout = secondary.get(op2)\n+ if secout == None:\n+ raise envi.InvalidInstruction( #FIXME!!!!\n+ mesg=\"smull invalid decode: op2\",\n+ bytez=bytez[offset:offset+4], va=va)\n+\n+ opers = (\n+ ArmRegOper(rdhi, va=va),\n+ ArmRegOper(rdlo, va=va),\n+ ArmRegOper(rn, va=va),\n+ ArmRegOper(rm, va=va),\n+ )\n+ return COND_AL, opcode, mnem, opers, None, 0\ndef tb_ldrex_32(va, val1, val2):\nop3 = (val2 >> 4) & 0xf\n@@ -1459,12 +1629,19 @@ def coproc_simd_32(va, val1, val2):\n#print bin(coproc), bin(op1),bin(op)\nif op1 & 0b110000 == 0b110000:\n+ print(\"AdvSIMD from CoprocSIMD. How did we get here? This should be impossible!\")\nreturn adv_simd_32(va, val1, val2)\n+ if op1 & 0b111110 == 0:\n+ bytez = struct.pack(\"<HH\", val1, val2)\n+ raise envi.InvalidInstruction(\n+ mesg=\"CoprocSIMD: UNDEFINED instructions\",\n+ bytez=bytez, va=va)\n+\nif coproc & 0b1110 != 0b1010: # apparently coproc 10 and 11 are not allowed...\nif op1 == 0b000100:\n# mcrr/mcrr2 (a8-476)\n- mnem = ('mcrr','mcrr2')[(val1>12)&1]\n+ mnem, opcode = (('mcrr', INS_MCRR),('mcrr2', INS_MCRR2))[(val1>12)&1]\nRt2 = val1 & 0xf\nRt = (val2>>12) & 0xf\n@@ -1478,11 +1655,10 @@ def coproc_simd_32(va, val1, val2):\nArmRegOper(Rt2, va=va),\nArmCoprocRegOper(CRm),\n)\n- opcode = IENC_COPROC_RREG_XFER<<16\nelif op1 == 0b000101:\n# mrrc/mrrc2 (a8-492)\n- mnem = ('mcrr','mcrr2')[(val1>12)&1]\n+ mnem, opcode = (('mrrc', INS_MRRC),('mrrc2',INS_MRRC2))[(val1>12)&1]\nRt2 = val1 & 0xf\nRt = (val2>>12) & 0xf\n@@ -1496,12 +1672,11 @@ def coproc_simd_32(va, val1, val2):\nArmRegOper(Rt2, va=va),\nArmCoprocRegOper(CRm),\n)\n- opcode = IENC_COPROC_RREG_XFER<<16\n- elif op1 & 0b100000 == 0:\n+ elif op1 & 0b100000 == 0 and not (op1 & 0b111010 == 0):\n# stc/stc2 (a8-660)\n# ldc/ldc2 immediate/literal (if Rn == 0b1111) (a8-390/392)\n- mnem = ('stc','ldc','stc2','ldc2')[((val1>>11)&2) | (op1 & 1)]\n+ mnem, opcode = (('stc', INS_STC),('ldc', INS_LDC),('stc2', INS_STC2),('ldc2', INS_LDC2))[((val1>>11)&2) | (op1 & 1)]\npudwl = (val1>>4) & 0x1f\nRn = (val1) & 0xf\n@@ -1519,8 +1694,6 @@ def coproc_simd_32(va, val1, val2):\nArmImmOffsetOper(Rn, offset*4, va, pubwl=pudwl),\n)\n- opcode = (IENC_COPROC_LOAD << 16)\n-\nelif op1 & 0b110000 == 0b100000 and op == 0:\n# cdp/cdp2 (a8-356)\nopc1 = (val1>>4) & 0xf\n@@ -1549,7 +1722,7 @@ def coproc_simd_32(va, val1, val2):\nRd = (val2>>12) & 0xf\nopc2 = (val2>>5) & 0x7\nCRm = val2 & 0xf\n- mnem = ('mcr','mrc','mcr2','mrc2')[load | two]\n+ mnem, opcode = (('mcr', INS_MCR),('mrc', INS_MRC),('mcr2', INS_MCR2),('mrc2', INS_MRC2))[load | two]\nopers = (\nArmCoprocOper(coproc),\n@@ -1560,20 +1733,35 @@ def coproc_simd_32(va, val1, val2):\nArmCoprocOpcodeOper(opc2),\n)\n- opcode = (IENC_COPROC_REG_XFER << 16)\n+ else:\n+ bytez = struct.pack(\"<HH\", val1, val2)\n+ raise envi.InvalidInstruction(\n+ mesg=\"CoprocSIMD: Fell of the end of decoding (coproc not 0xa or 0xb\",\n+ bytez=bytez, va=va)\nelse:\n- # coproc = 0b101x\n+ # coproc = 0b101x - ARM7A/M p251\n# FIXME: REMOVE WHEN DONE IMPLEMENTING\nopcode = 0\niflags = 0\nopers = []\n- if op1 & 0b111110 == 0b000100:\n+ if op1 & 0b110000 == 0b100000:\n+ if op == 0:\n+ # fp dp (a7-270)\n+ return fp_dp(va, val1, val2)\n+\n+ else:\n+ # adv simd fp (a7-276)\n+ return adv_xfer_arm_ext_32(va, val1, val2)\n+\n+ elif op1 & 0b111110 == 0b000100:\n# adv simd fp (A7-277)\n+ print(\"AdvSIMD from CoprocSIMD... do we actually end up here?\")\nreturn adv_simd_32(va, val1, val2)\n- elif op1 & 0b100000 == 0:\n+ elif op1 & 0b100000 == 0 and not (op1 & 0b111010 == 0):\n+ # extension register load/store instructions\nRn = val1 & 0xf\n# adv simd fp (a7-272)\n@@ -1581,14 +1769,16 @@ def coproc_simd_32(va, val1, val2):\nif op1 & 0b11110 == 0b00100:\n# 64 bit transverse between ARM core and extension registers (a7-277)\n+ bytez = struct.pack(\"<HH\", val1, val2)\nraise envi.InvalidInstruction( #FIXME!!!!\nmesg=\"IMPLEMENT: 64-bit transverse between ARM core and extension registers\",\n- bytez=bytez[offset:offset+4], va=va)\n+ bytez=bytez, va=va)\n# EXPECT TO NOT REACH HERE UNLESS WE MEAN BUSINESS. otherwise this needs to be in an else:\nif (op1 & 0b11010) in (0b10, 0b11010):\n- raise InvalidInstruction(mesg=\"INVALID ENCODING\", bytez=bytez[offset:offset+4], va=va)\n+ bytez = struct.pack(\"<HH\", val1, val2)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING\", bytez=bytez, va=va)\nl = op1 & 1 # vldm or vstm\nindiv = (op1 & 0b10010) == 0b10000\n@@ -1634,27 +1824,17 @@ def coproc_simd_32(va, val1, val2):\nVRd = rctx.getRegisterIndex(rbase % d)\nopers = (\nArmRegOper(VRd, va=va, oflags=oflags),\n- ArmImmOffsetOper(Rn, imm32, va=va, pubwl=pudwl),\n+ ArmImmOffsetOper(Rn, imm8, va=va, pubwl=pudwl),\n)\nelse:\nopers = (\nArmRegOper(Rn, va=va, oflags=oflags),\n- ArmExtRegListOper(d, imm32>>size, size),\n+ ArmExtRegListOper(d, (2*imm8)>>size, size),\n)\n-\n- elif op1 & 0b110000 == 0b100000:\n- if op == 0:\n- # fp dp (a7-270)\n- mnem = 'UNIMPL: FP DP' # FIXME!!!\n- return fp_dp(va, val1, val2)\n-\nelse:\n- # adv simd fp (a7-276)\n- mnem = 'UNIMPL: adv simd' # FIXME\n- #print \"->adv_xfer_arm_ext_32\"\n- return adv_xfer_arm_ext_32(va, val1, val2)\n- #return adv_simd_32(va, val1, val2)\n+ bytez = struct.pack(\"<HH\", val1, val2)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_32\", bytez=bytez, va=va)\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n@@ -1697,6 +1877,10 @@ def adv_xfer_arm_ext_32(va, val1, val2):\n# p.A8-956\nmnem, opcode = 'vmsr', INS_VMSR\nopers = ()\n+ else:\n+ bytez = struct.pack(\"<I\", val)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_32: l=0. c=0, a != (0, 7)\", bytez=bytez, va=va)\n+\nelse: # c == 1\nif (a & 0b100) == 0:\n# p.A8-940\n@@ -1708,6 +1892,7 @@ def adv_xfer_arm_ext_32(va, val1, val2):\n# p.A8-886\nmnem, opcode = 'vdup', INS_VDUP\nopers = ()\n+\nelse: # l == 1\nif c == 0:\nif a == 0:\n@@ -1718,6 +1903,10 @@ def adv_xfer_arm_ext_32(va, val1, val2):\n# p.A8-954 & B9-2012\nmnem, opcode = 'vmrs', INS_VMRS\nopers = ()\n+ else:\n+ bytez = struct.pack(\"<I\", val)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_32: l=1. c=0, a != (0, 7)\", bytez=bytez, va=va)\n+\nelse: # c == 1\n# p.A8-942\nmnem, opcode = 'vmov', INS_VMOV\n@@ -1853,12 +2042,12 @@ thumb_base = [\n('11011111', (INS_BCC,'bfukt', pc_imm8, envi.IF_BRANCH|0)),\n# Software Interrupt\n('11011111', (INS_SWI,'svc', imm8, 0)), # SWI <blahblah>\n- ('1011111100000000', (INS_HINT,'nopHint', imm8, 0)),\n- ('1011111100010000', (INS_HINT,'yieldHint', imm8, 0)),\n- ('1011111100100000', (INS_HINT,'wfrHint', imm8, 0)),\n- ('1011111100110000', (INS_HINT,'wfiHint', imm8, 0)),\n- ('1011111101000000', (INS_HINT,'sevHint', imm8, 0)),\n- ('10111111', (INS_IT, 'it', itblock, envi.IF_COND)),\n+ ('1011111100000000', (INS_NOP, 'nop', it_hints, 0)),\n+ ('1011111100010000', (INS_YIELD,'yield', it_hints, 0)),\n+ ('1011111100100000', (INS_WFR, 'wfr', it_hints, 0)),\n+ ('1011111100110000', (INS_WFI, 'wfi', it_hints, 0)),\n+ ('1011111101000000', (INS_SEV, 'sev', it_hints, 0)),\n+ ('10111111', (INS_IT, 'it', it_hints, envi.IF_COND)),\n]\nthumb1_extension = [\n@@ -1963,7 +2152,7 @@ thumb2_extension = [\n('11110000001', (INS_BIC, 'bic', dp_mod_imm_32, IF_THUMB32)),\n('11110000010', (INS_ORR, 'orr', dp_mod_imm_32, IF_THUMB32)),\n('11110000011', (INS_ORN, 'orn', dp_mod_imm_32, IF_THUMB32)), # mvn if rn=1111\n- ('11110000110', (INS_BLX, 'blx', branch_misc, IF_THUMB32)),\n+ ('11110000110', (INS_BLX, 'blx', branch_misc, IF_THUMB32)), # necessary\n('11110000100', (INS_EOR, 'eor', dp_mod_imm_32, IF_THUMB32)), # teq if rd=1111 and s=1\n('11110001000', (INS_ADD, 'add', dp_mod_imm_32, IF_THUMB32)), # cmn if rd=1111 and s=1\n('11110001010', (INS_ADC, 'adc', dp_mod_imm_32, IF_THUMB32)),\n@@ -1980,6 +2169,8 @@ thumb2_extension = [\n('11110101011', (INS_SBC, 'sbc', dp_mod_imm_32, IF_THUMB32)),\n('11110101101', (INS_SUB, 'sub', dp_mod_imm_32, IF_THUMB32)), # cmp if rd=1111 and s=1\n('11110101110', (INS_RSB, 'rsb', dp_mod_imm_32, IF_THUMB32)),\n+\n+ # data processing (plain binary immediate)\n('1111001000', (INS_ADD, 'add', dp_bin_imm_32, IF_THUMB32)), # adr if rn=1111\n('1111001001', (INS_MOVW, 'movw', dp_bin_imm_32, IF_THUMB32)),\n('1111001010', (INS_SUB, 'sub', dp_bin_imm_32, IF_THUMB32)), # adr if rn=1111\n@@ -2003,7 +2194,9 @@ thumb2_extension = [\n('11110111100', (INS_USAT, 'usat', dp_bin_imm_32, IF_THUMB32)),\n('11110111101', (INS_USAT, 'usat', dp_bin_imm_32, IF_THUMB32)), # usat16 if val2=0000xxxx00xxxxxx\n('11110111110', (INS_UBFX, 'ubfx', ubfx_32, IF_THUMB32)),\n- ('11110111111', (None, 'branchmisc', branch_misc, IF_THUMB32)),\n+ ('11110111111', (None, 'branchmisc', branch_misc, IF_THUMB32)), # necessary\n+\n+ # stores, loads, etc...\n('111110000000', (INS_STR, 'str', ldr_puw_32, IF_B | IF_THUMB32)),\n('111110000001', (None, 'ldrb_memhints32', ldrb_memhints_32, IF_THUMB32)),\n('111110000010', (INS_STR, 'str', ldr_puw_32, IF_H | IF_THUMB32)),\n@@ -2023,52 +2216,26 @@ thumb2_extension = [\n# data-processing (register)\n('111110100', (None, 'shift_or_extend', shift_or_ext_32, IF_THUMB32)),\n- #('111110101', (None, 'parallel_misc', parallel_misc_32, IF_THUMB32)),\n- ('111110101001', (INS_UADD16, 'uadd16', pdp_32, IF_THUMB32)),\n- ('111110101010', (INS_UASX, 'uasx', pdp_32, IF_THUMB32)),\n- ('111110101110', (INS_USAX, 'usax', pdp_32, IF_THUMB32)),\n- ('111110101101', (INS_USUB16, 'usub16', pdp_32, IF_THUMB32)),\n- ('111110101000', (INS_UADD8, 'uadd8', pdp_32, IF_THUMB32)),\n- ('111110101100', (INS_USUB8, 'usub8', pdp_32, IF_THUMB32)),\n- ('111110101001', (INS_UADD16, 'uadd16', pdp_32, IF_THUMB32)),\n- ('111110101001', (INS_UADD16, 'uadd16', pdp_32, IF_THUMB32)),\n- ('111110101001', (INS_UADD16, 'uadd16', pdp_32, IF_THUMB32)),\n- ('111110101001', (INS_UADD16, 'uadd16', pdp_32, IF_THUMB32)),\n- ('111110101001', (INS_UADD16, 'uadd16', pdp_32, IF_THUMB32)),\n+ ('111110101', (None, 'parallel_misc', parallel_misc_32, IF_THUMB32)),\n+\n+ # multiply/mul-accumulate/absdiff\n('111110110000', (INS_MLA, 'mla', mla_32, IF_THUMB32)),\n- ('111110110001', (INS_SMUL, 'smul', smul_32, IF_THUMB32)),\n- #('11111', (85,'branchmisc', branch_misc, IF_THUMB32)),\n- #('11111', (85,'SOMETHING WICKED THIS WAY', dp_bin_imm_32, IF_THUMB32)),\n+ ('111110110001', (INS_SMUL, 'smul', smul_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+\n+ # long multiply/long mul-accumulate/divide\n+ ('111110111000', (INS_SMULL, 'smull', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111001', (INS_SDIV, 'sdiv', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111010', (INS_UMULL, 'umull', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111011', (INS_UDIV, 'udiv', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111100', (INS_SMLAL, 'smlal', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111101', (INS_SMLSLD, 'smlsld', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111110', (INS_UMLAL, 'umlal', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n+ ('111110111111', (INS_SMULL, 'smull', smull_32, IF_THUMB32)), # stopped on page 249 of ARM A and M\n('11100', (INS_B, 'b', pc_imm11, envi.IF_BRANCH|envi.IF_NOFALL)), # B <imm11>\n- # blx is covered by special exceptions in dp_bin_imm_32 and dp_mod_imm_32\n- #('11110', (INS_BL, 'bl', branch_misc, envi.IF_CALL | IF_THUMB32)), # BL/BLX <addr25>\n]\n-''' whoa... they changed it all up.\n- ('11110010000', (85,'and', dp_bin_imm_32, IF_W | IF_THUMB32)), # tst if rd=1111 and s=1\n- ('11110010001', (85,'bic', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110010010', (85,'orr', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110010011', (85,'orn', dp_bin_imm_32, IF_W | IF_THUMB32)), # mvn if rn=1111\n- ('11110010100', (85,'eor', dp_bin_imm_32, IF_W | IF_THUMB32)), # teq if rd=1111 and s=1\n- ('11110010110', (85,'movt', dp_bin_imm_32, IF_W | IF_THUMB32)), # teq if rd=1111 and s=1\n- ('11110011000', (85,'add', dp_bin_imm_32, IF_W | IF_THUMB32)), # cmn if rd=1111 and s=1\n- ('11110011010', (85,'adc', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110011011', (85,'sbc', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110011101', (85,'sub', dp_bin_imm_32, IF_W | IF_THUMB32)), # cmp if rd=1111 and s=1\n- ('11110011110', (85,'rsb', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110110000', (85,'and', dp_bin_imm_32, IF_W | IF_THUMB32)), # tst if rd=1111 and s=1\n- ('11110110001', (85,'bic', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110110010', (85,'orr', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110110011', (85,'orn', dp_bin_imm_32, IF_W | IF_THUMB32)), # mvn if rn=1111\n- ('11110110100', (85,'eor', dp_bin_imm_32, IF_W | IF_THUMB32)), # teq if rd=1111 and s=1\n- ('11110110110', (85,'movt', dp_bin_imm_32, IF_W | IF_THUMB32)), # teq if rd=1111 and s=1\n- ('11110111000', (85,'add', dp_bin_imm_32, IF_W | IF_THUMB32)), # cmn if rd=1111 and s=1\n- ('11110111010', (85,'adc', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110111011', (85,'sbc', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110111101', (85,'sub', dp_bin_imm_32, IF_W | IF_THUMB32)), # cmp if rd=1111 and s=1\n- ('11110111110', (85,'rsb', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- ('11110111111', (85,'', dp_bin_imm_32, IF_W | IF_THUMB32)),\n- '''\n+\n+\nthumb_table = list(thumb_base)\nthumb_table.extend(thumb1_extension)\n@@ -2152,7 +2319,12 @@ class ThumbDisasm:\n# print \"OPLEN: \", oplen\nelse:\n- cond, olist, nflags = opermkr(va+4, val)\n+ opnuggets = opermkr(va+4, val)\n+ if len(opnuggets) == 5:\n+ cond, olist, nflags, opcode, mnem = opnuggets\n+ else:\n+ cond, olist, nflags = opnuggets\n+\nif nflags != None:\nflags = nflags\n#print \"FLAGS: \", repr(olist), repr(flags)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
dramatic improvements on SIMD decoding. still work to be done.
|
718,770 |
01.09.2018 00:47:51
| 14,400 |
8a7eb1d54c3f30a6663b0aae694b25f71ab692ea
|
more bufixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1922,8 +1922,8 @@ vmul_mnems = (\n(None, None),\n('vfnms', INS_VFNMS),\n('vfnma', INS_VFNMA),\n- ('vfms', INS_VFMS),\n('vfma', INS_VFMA),\n+ ('vfms', INS_VFMS),\n)\ndef p_fp_dp(opval, va):\nval1 = opval >> 16\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
more bufixes
|
718,770 |
06.09.2018 00:05:01
| 14,400 |
a7eee3ba37f953c0381f11811d87a508980b2329
|
lots of arm/thumb disasm and emulation bugfixes/improvements
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -470,7 +470,7 @@ STRB (imm) & (reg)\nSTRH (imm) & (reg)\n'''\n-swap_mnem = ((\"swp\", INS_SWP), (\"swpb\", INS_SWPB),)\n+swap_mnem = ((\"swp\", INS_SWP, 4), (\"swpb\", INS_SWPB, 1),)\nstrex_mnem = ((\"strex\", INS_STREX), (\"ldrex\", INS_LDREX)) # FIXME: full instruction then suffix\nstrex_flags = (0, IF_D, IF_B, IF_H)\nstrh_mnem = ((\"str\",INS_STR, IF_H,2),(\"ldr\",INS_LDR, IF_H,2),) # IF_H\n@@ -489,11 +489,11 @@ def p_extra_load_store(opval, va, psize=4):\nif opval&0x0fb000f0==0x01000090:# swp/swpb\nidx = (pubwl>>2)&1\nopcode = INS_SWP\n- mnem, opcode = swap_mnem[idx]\n+ mnem, opcode, tsize = swap_mnem[idx]\nolist = (\nArmRegOper(Rd, va=va),\nArmRegOper(Rm, va=va),\n- ArmImmOffsetOper(Rn, 0, va, pubwl, psize=psize),\n+ ArmImmOffsetOper(Rn, 0, va, pubwl, psize=psize, tsize=tsize),\n)\nelif opval&0x0f800ff0==0x01800f90:# strex/ldrex\nidx = pubwl&1\n@@ -534,7 +534,7 @@ def p_extra_load_store(opval, va, psize=4):\niflags |= IF_T\nolist = (\nArmRegOper(Rd, va=va),\n- ArmRegOffsetOper(Rn, Rm, va, pubwl, psize=psize, force_tsize=2),\n+ ArmRegOffsetOper(Rn, Rm, va, pubwl, psize=psize, tsize=2),\n)\nelif opval&0x0e4000f0==0x004000b0:# strh/ldrh immoffset\nidx = pubwl&1\n@@ -543,7 +543,7 @@ def p_extra_load_store(opval, va, psize=4):\niflags |= IF_T\nolist = (\nArmRegOper(Rd, va=va),\n- ArmImmOffsetOper(Rn,(Rs<<4)+Rm, va, pubwl, psize=psize),\n+ ArmImmOffsetOper(Rn,(Rs<<4)+Rm, va, pubwl, psize=psize, tsize=tsize),\n)\nelif opval&0x0e5000d0==0x005000d0:# ldrsh/b immoffset\nidx = (opval>>5)&1\n@@ -553,7 +553,7 @@ def p_extra_load_store(opval, va, psize=4):\niflags |= IF_T\nolist = (\nArmRegOper(Rd, va=va),\n- ArmImmOffsetOper(Rn, (Rs<<4)+Rm, va, pubwl, psize=psize),\n+ ArmImmOffsetOper(Rn, (Rs<<4)+Rm, va, pubwl, psize=psize, tsize=tsize),\n)\nelif opval&0x0e5000d0==0x001000d0:# ldrsh/b regoffset\nidx = (opval>>5)&1\n@@ -563,7 +563,7 @@ def p_extra_load_store(opval, va, psize=4):\niflags |= IF_T\nolist = (\nArmRegOper(Rd, va=va),\n- ArmRegOffsetOper(Rn, Rm, va, pubwl, psize=psize, force_tsize=tsize),\n+ ArmRegOffsetOper(Rn, Rm, va, pubwl, psize=psize, tsize=tsize),\n)\nelif opval&0x0e5000d0==0x000000d0:# ldrd/strd regoffset\n# 000pu0w0-Rn--Rt-SBZ-1101-Rm- ldrd regoffset\n@@ -580,7 +580,7 @@ def p_extra_load_store(opval, va, psize=4):\nolist = (\nArmRegOper(Rd, va=va),\nArmRegOper(Rd+1, va=va),\n- ArmRegOffsetOper(Rn, Rm, va, pubwl, psize=psize),\n+ ArmRegOffsetOper(Rn, Rm, va, pubwl, psize=psize, tsize=8),\n)\nelif opval&0x0e5000d0==0x004000d0:# ldrd/strd immoffset\nif (Rd == 14) or (Rd % 2 != 0):\n@@ -593,7 +593,7 @@ def p_extra_load_store(opval, va, psize=4):\nolist = (\nArmRegOper(Rd, va=va),\nArmRegOper(Rd+1, va=va),\n- ArmImmOffsetOper(Rn, (Rs<<4)+Rm, va, pubwl, psize=psize),\n+ ArmImmOffsetOper(Rn, (Rs<<4)+Rm, va, pubwl, psize=psize, tsize=8),\n)\nelse:\nraise envi.InvalidInstruction(\n@@ -884,10 +884,15 @@ def p_load_imm_off(opval, va, psize=4):\nimm = opval & 0xfff\nmnem, opcode = ldr_mnem[pubwl&1]\niflags = 0\n+\n+ tsize = 4\nif pubwl & 4: # B\niflags = IF_B\n+ tsize = 1\n+\nif (pubwl & 0x12) == 2:\niflags |= IF_T\n+\nif Rd == REG_PC:\niflags |= envi.IF_BRANCH\n@@ -904,7 +909,7 @@ def p_load_imm_off(opval, va, psize=4):\nelse:\nolist = (\nArmRegOper(Rd, va=va),\n- ArmImmOffsetOper(Rn, imm, va, pubwl=pubwl, psize=psize) # u=-/+, b=word/byte\n+ ArmImmOffsetOper(Rn, imm, va, pubwl=pubwl, psize=psize, tsize=tsize) # u=-/+, b=word/byte\n)\nreturn (opcode, mnem, olist, iflags, 0)\n@@ -1565,9 +1570,10 @@ def p_vstr(opval, va):\nsimdflags = (IFS_32, IFS_64)[sz]\nrbase = (\"s%d\",\"d%d\")[sz]\n+ tsize = 4 + (4*sz)\nopers = (\nArmRegOper(rctx.getRegisterIndex(rbase % vd)),\n- ArmImmOffsetOper(rn, imm, va, pubwl=pudwl)\n+ ArmImmOffsetOper(rn, imm, va, pubwl=pudwl, tsize=tsize)\n)\nreturn INS_VSTR, 'vstr', opers, 0, 0\n@@ -1622,9 +1628,10 @@ def p_vldr(opval, va):\nsimdflags = (IFS_32, IFS_64)[sz]\nrbase = (\"s%d\",\"d%d\")[sz]\n+ tsize = 4 + (4*sz)\nopers = (\nArmRegOper(rctx.getRegisterIndex(rbase % vd)),\n- ArmImmOffsetOper(rn, imm, va, pubwl=pudwl)\n+ ArmImmOffsetOper(rn, imm, va, pubwl=pudwl, tsize=tsize)\n)\nreturn INS_VLDR, 'vldr', opers, 0, simdflags\n@@ -4346,17 +4353,17 @@ class ArmScaledOffsetOper(ArmOperand):\nclass ArmRegOffsetOper(ArmOperand):\n''' register offset operand. see \"addressing mode 2 - load and store word or unsigned byte - register *\"\ndereference address mode using the combination of two register values '''\n- def __init__(self, base_reg, offset_reg, va, pubwl=PUxWL_DFLT, psize=4, force_tsize=None):\n+ def __init__(self, base_reg, offset_reg, va, pubwl=PUxWL_DFLT, psize=4, tsize=None):\nself.base_reg = base_reg\nself.offset_reg = offset_reg\nself.pubwl = pubwl\nself.psize = psize\n- if force_tsize == None:\n+ if tsize == None:\nb = (self.pubwl >> 2) & 1\nself.tsize = (4,1)[b]\nelse:\n- self.tsize = force_tsize\n+ self.tsize = tsize\ndef __eq__(self, oper):\nif not isinstance(oper, self.__class__):\n@@ -4449,7 +4456,7 @@ class ArmImmOffsetOper(ArmOperand):\npossibly with indexing, pre/post for faster rolling through arrays and such\nif the base_reg is PC, we'll dig in and hopefully grab the data being referenced.\n'''\n- def __init__(self, base_reg, offset, va, pubwl=PUxWL_DFLT, psize=4):\n+ def __init__(self, base_reg, offset, va, pubwl=PUxWL_DFLT, psize=4, tsize=None):\n'''\npsize is pointer-size, since we want to increment base_reg that size when indexing\ntsize is the target size (4 or 1 bytes)\n@@ -4460,8 +4467,11 @@ class ArmImmOffsetOper(ArmOperand):\nself.psize = psize\nself.va = va\n+ if tsize == None:\nb = (pubwl >> 2) & 1\nself.tsize = (4,1)[b]\n+ else:\n+ self.tsize = tsize\ndef __eq__(self, oper):\nif not isinstance(oper, self.__class__):\n@@ -4504,8 +4514,6 @@ class ArmImmOffsetOper(ArmOperand):\ndef getOperAddr(self, op, emu=None):\n# there are certain circumstances where we can survive without an emulator\n- pubwl = self.pubwl >> 3\n- u = pubwl & 1\n# if we don't have an emulator, we must be PC-based since we know it\nif self.base_reg == REG_PC:\nbase = self.va\n@@ -4514,6 +4522,8 @@ class ArmImmOffsetOper(ArmOperand):\nelse:\nbase = emu.getRegister(self.base_reg)\n+ pubwl = self.pubwl >> 3\n+ u = pubwl & 1\nif u:\naddr = (base + self.offset) & e_bits.u_maxes[self.psize]\nelse:\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -171,6 +171,14 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nflags &= ~which\nself.setCPSR(flags)\n+ def setFpFlag(self, which, state):\n+ flags = self.getFPSCR()\n+ if state:\n+ flags |= which\n+ else:\n+ flags &= ~which\n+ self.setCPSR(flags)\n+\ndef getFlag(self, which): # FIXME: CPSR?\n#if (flags_reg == None):\n# flags_reg = proc_modes[self.getProcMode()][5]\n@@ -257,7 +265,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\npc = self.getProgramCounter()\nx = pc+op.size\n- # should we set this to the odd address or even during thumb? (debugger). ANS: Even. All addresses are Even. Track Mode elsewhere.\nself.setProgramCounter(x)\nfinally:\nself.setMeta('forrealz', False)\n@@ -286,6 +293,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n'''\nreturn self._rctx_vals[REG_CPSR]\n+ def getFPSCR(self):\n+ '''\n+ return the Current Floating Point Status/Control Register.\n+ '''\n+ return self._rctx_vals[REG_FPSCR]\n+\ndef getAPSR(self):\n'''\nreturn the Current Program Status Register.\n@@ -718,9 +731,29 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nraise Exception(\"0x%x: %r Something went wrong... opers = %r \" % (op.va, op, op.opers))\n- #\n- #raise Exception(\"implement me: vmov\")\n+ def i_vstr(self, op):\n+ src = self.getOperValue(op, 1)\n+ self.setOperValue(op, 0, src)\n+\n+ def i_vcmpe(self, op):\n+ src1 = self.getOperValue(op, 0)\n+ src2 = self.getOperValue(op, 1)\n+ val = src2 - src1\n+ print \"vcmpe %r %r %r\" % (src1, src2, val)\n+ fpsrc = self.getRegister(REG_FPSCR)\n+\n+ # taken from VFCompare() from arch ref manual p80\n+ if src1 == src2:\n+ n, z, c, v = 0, 1, 1, 0\n+ elif src1 < src2:\n+ n, z, c, v = 1, 0, 0, 0\n+ else:\n+ n, z, c, v = 0, 0, 1, 0\n+ self.setFpFlag(PSR_N_bit, n)\n+ self.setFpFlag(PSR_Z_bit, z)\n+ self.setFpFlag(PSR_C_bit, c)\n+ self.setFpFlag(PSR_V_bit, v)\ndef i_ldm(self, op):\nif len(op.opers) == 2:\n@@ -857,6 +890,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_vldr = i_mov\n+ ''' this one is not favored\ndef i_it(self, op):\nif self.itcount:\nraise Exception(\"IT block within an IT block!\")\n@@ -866,7 +900,32 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.itcount = oper.getCondInstrCount()\nself.itflags = oper.getFlags()\nprint \"IT flags need to be set such that each bit means YES or NO\"\n+ '''\n+\n+ # TESTME: IT functionality\n+ def i_it(self, op):\n+ if self.itcount:\n+ raise Exception(\"IT block within an IT block!\")\n+\n+ self.itcount, self.ittype, self.itmask = op.opers[0].getCondData()\n+ condcheck = conditionals[self.ittype]\n+ self.itva = op.va\n+\n+ i_ite = i_it\n+ i_itt = i_it\n+ i_itee = i_it\n+ i_itet = i_it\n+ i_itte = i_it\n+ i_ittt = i_it\n+ i_iteee = i_it\n+ i_iteet = i_it\n+ i_itete = i_it\n+ i_itett = i_it\n+ i_ittee = i_it\n+ i_ittet = i_it\n+ i_ittte = i_it\n+ i_itttt = i_it\ndef i_bfi(self, op):\nlsb = self.getOperValue(op, 2)\n@@ -900,10 +959,11 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\noper = self.getOperValue(op, 1)\nbsize = op.opers[1].tsize * 8\nlzcnt = 0\n- for x in range(tsize):\n+ for x in range(bsize):\nif oper & 0x80000000:\nbreak\nlzcnt += 1\n+ oper <<= 1\nself.setOperValue(op, 0, lzcnt)\n@@ -1641,13 +1701,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_isb = i_nop\n-#TODO: IT EQ\n- def i_it(self, op):\n- self.itcount, self.ittype, self.itmask = op.opers[0].getCondData()\n- condcheck = conditionals[self.ittype]\n- self.itva = op.va\n-\n-\nopcode_dist = \\\n[('and', 4083),#\n('stm', 1120),#\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/regs.py",
"new_path": "envi/archs/arm/regs.py",
"diff": "@@ -183,7 +183,7 @@ arm_status_metas = [\n(\"M\", REG_FLAGS, PSR_M, 5, \"Processor Mode\"),\n]\n-e_reg.addLocalStatusMetas(l, arm_metas, arm_status_metas, \"CPSC\")\n+e_reg.addLocalStatusMetas(l, arm_metas, arm_status_metas, \"CPSR\")\ne_reg.addLocalMetas(l, arm_metas)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -575,7 +575,12 @@ def it_hints(va, val):\nfirstcond = (val>>4) & 0xf\nif mask != 0:\n# this is the IT instruction\n- return COND_AL,(ThumbITOper(mask, firstcond),), None\n+ itoper = ThumbITOper(mask, firstcond)\n+ count, cond, data = itoper.getCondData()\n+ nextfew = it_strs[count][data]\n+ mnem = 'it' + nextfew\n+\n+ return COND_AL,(itoper,), 0, None, mnem\nopcode, mnem = it_hints_others[firstcond]\n@@ -1261,7 +1266,7 @@ def ldrb_memhints_32(va, val1, val2):\nimm12 = val2 & 0xfff\nopers = (\nArmRegOper(rt),\n- ArmImmOffsetOper(rn, imm12, va),\n+ ArmImmOffsetOper(rn, imm12, va, tsize=1),\n)\nreturn COND_AL, opcode, mnem, opers, flags, 0\n@@ -1283,7 +1288,8 @@ def ldrb_memhints_32(va, val1, val2):\npubwl = ((val2 >> 6) & 0x18) | ((val2 >> 7) & 2)\nopers = (\nArmRegOper(rt),\n- ArmImmOffsetOper(rn, imm8, va, pubwl)\n+ #ArmImmOffsetOper(rn, imm8, va, pubwl) # FIXME: deprecated\n+ ArmImmOffsetOper(rn, imm8, va, tsize=1)\n)\nreturn COND_AL, opcode, mnem, opers, flags, 0\n@@ -1344,7 +1350,7 @@ def ldrd_imm_32(va, val1, val2):\noper0 = ArmRegOper(rt, va=va)\noper1 = ArmRegOper(rt2, va=va)\n- oper2 = ArmImmOffsetOper(rn, imm8<<2, va=va, pubwl=pubwl)\n+ oper2 = ArmImmOffsetOper(rn, imm8<<2, va=va, pubwl=pubwl, tsize=8)\nopers = (oper0, oper1, oper2)\nflags = 0\n@@ -1822,9 +1828,11 @@ def coproc_simd_32(va, val1, val2):\nif indiv:\nrbase = ('s%d', 'd%d')[size]\nVRd = rctx.getRegisterIndex(rbase % d)\n+ tsize = 4 + (size*4)\n+\nopers = (\nArmRegOper(VRd, va=va, oflags=oflags),\n- ArmImmOffsetOper(Rn, imm8, va=va, pubwl=pudwl),\n+ ArmImmOffsetOper(Rn, imm8, va=va, pubwl=pudwl, tsize=tsize),\n)\nelse:\n@@ -1867,6 +1875,7 @@ def adv_xfer_arm_ext_32(va, val1, val2):\nsimdflags = 0\nopers = None\n+ #print \"adv_xfer_arm_ext_32 a=%d l=%d c=%d b=%d\" % (a,l,c,b)\nif l == 0:\nif c == 0:\nif a == 0:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -44,8 +44,13 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\n# do we want to hand this off to makeCode?\nemu.vw.addLocation(starteip, len(op), vivisect.LOC_OP, op.iflags)\n+ elif loctup[2] != LOC_OP:\n+ if self.verbose: print \"ARG! emulation found opcode in an existing NON-OPCODE location (0x%x): 0x%x: %s\" % (loctup[0], op.va, op)\n+ emu.stopEmu()\n+\nelif loctup[0] != starteip:\nif self.verbose: print \"ARG! emulation found opcode in a location at the wrong address (0x%x): 0x%x: %s\" % (loctup[0], op.va, op)\n+ emu.stopEmu()\nif op.iflags & envi.IF_RET:\nself.returns = True\n@@ -145,8 +150,7 @@ def buildFunctionApi(vw, fva, emu, emumon):\nreturn api\ndef analyzeFunction(vw, fva):\n- #print( \"= 0x%x viv.analysis.arm.emulation... =\" % (fva))\n-\n+ #print(\"++ Arm EMU fmod: 0x%x\" % fva)\nemu = vw.getEmulator()\nemumon = AnalysisMonitor(vw, fva)\nemu.setEmulationMonitor(emumon)\n@@ -190,6 +194,7 @@ def analyzeFunction(vw, fva):\n# switch-cases may have updated codeflow. reanalyze\nviv_cb.analyzeFunction(vw, fva)\n+ #print(\"-- Arm EMU fmod: 0x%x\" % fva)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -3,6 +3,7 @@ import envi\nimport vivisect\nimport vivisect.impemu.monitor as viv_monitor\n+from envi.archs.arm.regs import PSR_T_bit\nfrom vivisect import LOC_STRING, LOC_UNI, REF_DATA\nMAX_INIT_OPCODES = 30\n@@ -81,11 +82,19 @@ def analyzeFunction(vw, fva, prepend=False):\nsuccess = 0\ntva = fva\nemu = vw.getEmulator()\n+ emu._prep(tva)\nfor x in range(MAX_INIT_OPCODES):\n- op = vw.parseOpcode(tva)\n+ op = emu.parseOpcode(tva)\n+\n+ tmode = emu.getFlag(PSR_T_bit)\n+\nemu.executeOpcode(op)\n+ newtmode = emu.getFlag(PSR_T_bit)\n+ if newtmode != tmode:\n+ emu.setFlag(PSR_T_bit, tmode)\n+\nif op.iflags & (envi.IF_BRANCH | envi.IF_COND) == (envi.IF_BRANCH | envi.IF_COND):\nbreak\n@@ -109,6 +118,9 @@ def analyzeFunction(vw, fva, prepend=False):\nbreak\ntva += len(op)\n+ if op.isReturn():\n+ #print \"thunk_reg: returning before finding PIE data\"\n+ break\nif not success:\nreturn\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -324,7 +324,11 @@ class WorkspaceEmulator:\nop = self.parseOpcode(starteip)\nself.op = op\nif self.emumon:\n+ try:\nself.emumon.prehook(self, op, starteip)\n+ except Exception, e:\n+ print(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon prehook)\" % (funcva, starteip, op, e))\n+\nif self.emustop:\nreturn\n@@ -336,7 +340,11 @@ class WorkspaceEmulator:\nendeip = self.getProgramCounter()\nif self.emumon:\n+ try:\nself.emumon.posthook(self, op, endeip)\n+ except Exception, e:\n+ print(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon posthook)\" % (funcva, starteip, op, e))\n+\nif self.emustop:\nreturn\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -72,35 +72,81 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif not self.checkCall(starteip, endeip, op):\nself.checkBranches(starteip, endeip, op)\n- def runFunction(self, funcva, stopva=None, maxhit=None, maxloop=None, tmode=None):\n- \"\"\"\n- This is a utility function specific to WorkspaceEmulation (and impemu) that\n- will emulate, but only inside the given function. You may specify a stopva\n- to return once that location is hit.\n- \"\"\"\n-\n+ def _prep(self, funcva, tmode=None):\nif tmode != None:\n# we're forcing thumb or arm mode... update the flag\nself.setFlag(PSR_T_bit, tmode)\n+ if verbose: print \"funcva thumb==%d (forced): 0x%x\" % (tmode, funcva)\nelif funcva & 3:\n+ # if the va isn't 4-byte aligned, it's gotta be thumb\nself.setFlag(PSR_T_bit, 1)\nfuncva &= -2\n- if verbose: print \"funcva is THUMB: 0x%x\" % funcva\n+ if verbose: print \"funcva is THUMB(addr): 0x%x\" % funcva\nelse:\nloc = self.vw.getLocation(funcva)\nif loc != None:\n+ # if we have a opcode location, use it's iflags to determine mode\nlva, lsz, lt, lti = loc\nif (lti & envi.ARCH_MASK) == envi.ARCH_THUMB:\nself.setFlag(PSR_T_bit, 1)\n+ if verbose: print \"funcva is THUMB(loc): 0x%x\" % funcva\n+ elif verbose: print \"funcva is ARM(loc): 0x%x\" % funcva\nelse:\n- if verbose: print \"ArmWorkspaceEmulator: Nothing specified, defaulting to ARM\"\n+ # otherwise, let's use some heuristics to guess.\n+ armthumb = 0\n+ armop = None\n+ thumbop = None\n+ try:\n+ thumbop = self.parseOpcode(funcva | 1)\n+ armthumb -= 1\n+ if thumbop.mnem == 'push':\n+ armthumb -= 5\n+ elif thumbop.mnem == 'ldr':\n+ armthumb -= 2\n+\n+ except InvalidInstruction, e:\n+ pass\n+\n+\n+ try:\n+ armop = self.parseOpcode(funcva)\n+ armthumb += 1\n+ if armop.mnem == 'push':\n+ armthumb += 5\n+ elif armop.mnem == 'ldr':\n+ armthumb += 2\n+\n+ except InvalidInstruction, e:\n+ pass\n+\n+\n+ if arm == None and thumb == None:\n+ # we didn't have a single push in either direction\n+ print(\"TOTAL FAILURE TO DETERMINE THUMB MODE\")\n+ raise Exception(\"Neither architecture parsed the first opcode\")\n+\n+ elif armthumb < 0:\n+ self.setFlag(PSR_T_bit, 1)\n+ if verbose: print \"ArmWorkspaceEmulator: Heuristically Determined funcva is THUMB: 0x%x\" % funcva\n+ else:\n+ #if verbose: print \"ArmWorkspaceEmulator: Nothing specified, defaulting to ARM: 0x%x\" % funcva\n+ if verbose: print \"ArmWorkspaceEmulator: Heuristically Determined funcva is ARM: 0x%x\" % funcva\nself.funcva = funcva\n+\n+ def runFunction(self, funcva, stopva=None, maxhit=None, maxloop=None, tmode=None):\n+ \"\"\"\n+ This is a utility function specific to WorkspaceEmulation (and impemu) that\n+ will emulate, but only inside the given function. You may specify a stopva\n+ to return once that location is hit.\n+ \"\"\"\n+ self._prep(funcva, tmode)\n+\n# Let the current (should be base also) path know where we are starting\nvg_path.setNodeProp(self.curpath, 'bva', funcva)\n@@ -155,8 +201,10 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.op = op\nif self.emumon:\n-\n+ try:\nself.emumon.prehook(self, op, starteip)\n+ except Exception, e:\n+ print(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon prehook)\" % (funcva, starteip, op, e))\nif self.emustop:\nreturn\n@@ -168,7 +216,10 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nendeip = self.getProgramCounter()\nif self.emumon:\n+ try:\nself.emumon.posthook(self, op, endeip)\n+ except Exception, e:\n+ print(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon posthook)\" % (funcva, starteip, op, e))\nif self.emustop:\nreturn\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
lots of arm/thumb disasm and emulation bugfixes/improvements
|
718,770 |
07.09.2018 17:44:41
| 14,400 |
07e6c653b0613b05b4a91e77f172b4baeb362d1a
|
arm small bugfixes and cleanups.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -223,7 +223,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nnote: differs from the IMemory interface by checking loclist\n'''\nif arch == envi.ARCH_DEFAULT:\n- arch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[self.getFlag(PSR_T_bit)]\n+ tmode = self.getFlag(PSR_T_bit)\n+ arch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[tmode]\noff, b = self.getByteDef(va)\nreturn self.imem_archs[ (arch & envi.ARCH_MASK) >> 16 ].archParseOpcode(b, off, va)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/calling.py",
"new_path": "vivisect/analysis/i386/calling.py",
"diff": "@@ -53,7 +53,7 @@ class AnalysisMonitor(viv_imp_monitor.AnalysisMonitor):\nviv_imp_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n# Do return related stuff before we execute the opcode\n- if op.iflags & envi.IF_RET:\n+ if op.isReturn():\nif len(op.opers):\nself.retbytes = op.opers[0].imm\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -51,7 +51,7 @@ class WorkspaceEmulator:\nself._safe_mem = True # Should we be forgiving about memory accesses?\nself._func_only = True # is this emulator meant to stay in one function scope?\n- self.strictops = True # shoudl we bail on emulation if unsupported instruction encountered\n+ self.strictops = True # should we bail on emulation if unsupported instruction encountered\n# Map in all the memory associated with the workspace\nfor va, size, perms, fname in vw.getMemoryMaps():\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -39,11 +39,11 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\n'''\nop = self.opcache.get(va)\n+ if op == None:\ntmode = self.getFlag(PSR_T_bit)\nif arch == envi.ARCH_DEFAULT:\narch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[tmode]\n- if op == None:\nop = envi.archs.arm.emu.ArmEmulator.parseOpcode(self, va, arch=arch)\nself.opcache[va] = op\nreturn op\n@@ -237,7 +237,6 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nfor bva,bpath in blist:\ntodo.append((bva, esnap, bpath))\nbreak\n- else:\n# check if we've blx'd to a different thumb state. if so,\n# be sure to return to the original tmode before continuing emulation pass\nnewtmode = self.getFlag(PSR_T_bit)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arm small bugfixes and cleanups.
|
718,770 |
22.09.2018 23:56:21
| 14,400 |
4d3e65aa09195fcd7a9f1a4ca127f5f5357e9684
|
bugfixes to unittests
|
[
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -41,10 +41,8 @@ instrs = [\n'tests':(('r3',0xfefefefe),('PSR_Q',0),('PSR_N',0),('PSR_Z',0),('PSR_V',0),('PSR_C',0)) }\n)),\n(REV_ALL_ARM, '08309fe5', 0xbfb00000, 'ldr r3, [#0xbfb00010]', 0, (\n- {#'setup':(('r0',0xaa),('PSR_C',0),('r3',0x1a)),\n+ {\n'tests':(('r3',0xfefefefe),('PSR_Q',0),('PSR_N',0),('PSR_Z',0),('PSR_V',0),('PSR_C',0)) },\n- # {'setup':(('r0',0xaa),('PSR_C',0),('r3',0x1a)),\n- # 'tests':(('r3',0xfefefefe),('PSR_Q',0),('PSR_N',0),('PSR_Z',0),('PSR_V',0),('PSR_C',0)) }\n)),\n(REV_ALL_ARM, '08309be4', 0xbfb00000, 'ldr r3, [r11], #0x8', 0, ()),\n@@ -879,7 +877,18 @@ instrs = [\n(REV_ALL_ARM, '434fb0e1', 0x4560, 'asrs r4, r3, #0x1e', 0, ()),\n(REV_ALL_ARM, '5345a0e1', 0x4560, 'asr r4, r3, r5', 0, ()),\n(REV_ALL_ARM, '5345b0e1', 0x4560, 'asrs r4, r3, r5', 0, ()),\n- (REV_ALL_ARM, '1f32cfe7', 0x4560, 'bfc r3, #0x04, #0x0f', 0, ()),\n+ (REV_ALL_ARM, '1f32cfe7', 0x4560, 'bfc r3, #0x04, #0x0f', 0, (\n+ {'setup':(('r3',0xaaaaaaaa),),\n+ 'tests':(('r3',0b10101010101010000000000000001010),) },\n+ )),\n+ (REV_ALL_ARM, '6ff31f40', 0x4561, 'bfc.w r0, #0x10, #0x10', 0, (\n+ {'setup':(('r0',0xaaaaaaaa),),\n+ 'tests':(('r0',0b1010101010101010),) },\n+ )),\n+ (REV_ALL_ARM, '6ff30e01', 0x4561, 'bfc.w r1, #0x00, #0x0f', 0, (\n+ {'setup':(('r1',0xaaaaaaaa),),\n+ 'tests':(('r1',0b10101010101010101000000000000000),) },\n+ )),\n(REV_ALL_ARM, '1432cfe7', 0x4560, 'bfi r3, r4, #0x04, #0x0f', 0, ()),\n(REV_ALL_ARM, 'fff053f5', 0x4560, 'pld [r3, #-0xff]', 0, ()),\n(REV_ALL_ARM, 'fff0d3f5', 0x4560, 'pld [r3, #0xff]', 0, ()),\n@@ -1268,16 +1277,26 @@ instrs = [\n(REV_ALL_ARM, 'f4efec2f', 0x4561, 'vext.8 q9, q10, q14, #0x0f', 0, ()),\n(REV_ALL_ARM, 'e4404ff4', 0x4561, 'lsrs r4, r4', 0, ()),\n- (REV_ALL_ARM, 'ab066ff0', 0x2, 'mvn.w r6, #171', 0, ()),\n- (REV_ALL_ARM, '9800d6f8', 0x6, 'ldr.w r0, [r6, #152]', 0, ()),\n- (REV_ALL_ARM, '407f10f4', 0xa, 'tst.w r0, #768', 0, ()),\n- (REV_ALL_ARM, '40704ff4', 0xe, 'mov.w r0, #768', 0, ()),\n-\n- (REV_ALL_ARM, '4ff4e440', 0x1, 'lsrs r4, r4', 0, ()),\n- (REV_ALL_ARM, '6ff0ab06', 0x2, 'mvn.w r6, #171', 0, ()),\n- (REV_ALL_ARM, 'd6f89800', 0x6, 'ldr.w r0, [r6, #152]', 0, ()),\n- (REV_ALL_ARM, '10f4407f', 0xa, 'tst.w r0, #768', 0, ()),\n- (REV_ALL_ARM, '4ff44070', 0xe, 'mov.w r0, #768', 0, ()),\n+ (REV_ALL_ARM, 'ab066ff0', 0x2, 'lsls r3, r5, #0x1a', 0, ()),\n+ (REV_ALL_ARM, '9800d6f8', 0x6, 'lsls r0, r3, #0x02', 0, ()),\n+ (REV_ALL_ARM, '407f10f4', 0xa, 'ldrb r0, [r0, #0x1d]', 0, ()),\n+ #(REV_ALL_ARM, '407f10f4', 0xa, 'tst.w r0, #768', 0, ()),\n+ (REV_ALL_ARM, '40704ff4', 0xe, 'strb r0, [r0, #0x1]', 0, ()),\n+ #(REV_ALL_ARM, '40704ff4', 0xe, 'mov.w r0, #768', 0, ()),\n+ (REV_ALL_ARM, 'd6f89800', 0x6, 'ldr.w r0, [r6, #0x98]', 0, ()),\n+ (REV_ALL_ARM, '980096e5', 0x4, 'ldr r0, [r6, #0x98]', 0, ()), # arm\n+ #(REV_ALL_ARM, '9800d6f8', 0x6, 'ldr.w r0, [r6, #152]', 0, ()),\n+ (REV_ALL_ARM, '407f', 0xa, 'ldrb r0, [r0, #0x1d]', 0, ()),\n+ (REV_ALL_ARM, '10f0011f', 0xa, 'tst.w r0, #0x10001', 0, ()),\n+ #(REV_ALL_ARM, '407f10f4', 0xa, 'tst.w r0, #768', 0, ()),\n+ (REV_ALL_ARM, '40704ff4', 0xe, 'strb r0, [r0, #0x1]', 0, ()),\n+ #(REV_ALL_ARM, '40704ff4', 0xe, 'mov.w r0, #768', 0, ()),\n+\n+ (REV_ALL_ARM, '4ff4e440', 0x1, 'mov.w r0, #0x7200', 0, ()),\n+ (REV_ALL_ARM, '6ff0ab06', 0x2, 'mvn.w r6, #0xab', 0, ()),\n+ (REV_ALL_ARM, 'd6f89800', 0x6, 'ldr.w r0, [r6, #0x98]', 0, ()),\n+ (REV_ALL_ARM, '10f4407f', 0xa, 'tst.w r0, #0x300', 0, ()),\n+ (REV_ALL_ARM, '4ff44070', 0xe, 'mov.w r0, #0x300', 0, ()),\n]\ninstrs.extend(advsimdtests)\n@@ -1330,7 +1349,7 @@ class ArmInstructionSet(unittest.TestCase):\ndef test_BigEndian(self):\nam = arm.ArmModule()\n- am.setEndian(ENDIAN_MSB)\n+ am.setEndian(envi.ENDIAN_MSB)\nop = am.archParseOpcode('e321f0d3'.decode('hex'))\nself.assertEqual('msr CPSR_c, #0xd3', repr(op))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfixes to unittests
|
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