author
int64 658
755k
| date
stringlengths 19
19
| timezone
int64 -46,800
43.2k
| hash
stringlengths 40
40
| message
stringlengths 5
490
| mods
list | language
stringclasses 20
values | license
stringclasses 3
values | repo
stringlengths 5
68
| original_message
stringlengths 12
491
|
|---|---|---|---|---|---|---|---|---|---|
718,770 |
04.12.2019 10:02:09
| 18,000 |
ab1a0da80e73ad863a0e3fd29c09a41360991d77
|
remove unnecessary symidx==0 checks
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -611,9 +611,6 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nif arch in ('arm', 'thumb', 'thumb16'):\nif rtype == Elf.R_ARM_JUMP_SLOT:\nsymidx = r.getSymTabIndex()\n- if symidx == 0:\n- continue\n-\nsym = elf.getDynSymbol(symidx)\nptr = sym.st_value\n@@ -640,9 +637,6 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nelif rtype == Elf.R_ARM_GLOB_DAT:\nsymidx = r.getSymTabIndex()\n- if symidx == 0:\n- continue\n-\nsym = elf.getDynSymbol(symidx)\nptr = sym.st_value\n@@ -666,9 +660,6 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nelif rtype == Elf.R_ARM_ABS32:\nsymidx = r.getSymTabIndex()\n- if symidx == 0:\n- continue\n-\nsym = elf.getDynSymbol(symidx)\nptr = sym.st_value\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
remove unnecessary symidx==0 checks
|
718,770 |
06.12.2019 15:13:13
| 18,000 |
7e7bea7e79f1a195a780dfd6da344f037de4b597
|
i found the missing 'e'!
|
[
{
"change_type": "MODIFY",
"old_path": "Elf/elf_lookup.py",
"new_path": "Elf/elf_lookup.py",
"diff": "@@ -632,7 +632,7 @@ st_other_visibility = {\nSTV_DEFAULT:\"Symbol visibility specified by binding type\",\nSTV_INTERNAL:\"Symbol visibility is reserved\",\nSTV_HIDDEN:\"Symbol is not visible to other objects\",\n- STV_PROTECTED:\"Symbol is visibl by other objects, but cannot be preempted\"\n+ STV_PROTECTED:\"Symbol is visible by other objects, but cannot be preempted\"\n}\nDT_NULL = 0\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
i found the missing 'e'!
|
718,770 |
07.12.2019 00:03:11
| 18,000 |
d4988fd198ff5d9d1761e59c000c46990bb5b97b
|
have Vivisect use the locations database for memory navigation. also, fix FuncGraph so it renders directly to a location the first time, not the start of the function.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -342,6 +342,7 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\nafter every change.\n'''\nself._last_viewpt = self.mem_canvas.page().mainFrame().scrollPosition()\n+ # FIXME: history should track this as well and return to the same place\nself.clearText()\nself.fva = None\nself._renderMemory()\n@@ -489,6 +490,18 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\n#self.parentWidget().delEventCore(self)\n#return e_mem_qt.VQMemoryWindow.closeEvent(self, event)\n+ def _getLocVa(self, addr):\n+ '''\n+ since we have a location database, let's use that to make sure we get a\n+ real location if it exists. otherwise, we end up in no-man's land,\n+ since we rely on labels, which only exist for the base of a location.\n+ '''\n+ loc = self.vw.getLocation(addr)\n+ if loc is None:\n+ return addr\n+\n+ return loc[L_VA]\n+\n@idlethread\ndef _renderMemory(self):\ntry:\n@@ -503,12 +516,10 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\nself.mem_canvas.addText('Invalid Address: %s (%s)' % (expr, e))\nreturn\n- fva = self.vw.getFunction(addr)\n- if fva == self.fva:\n- self.mem_canvas.page().mainFrame().scrollToAnchor('viv:0x%.8x' % addr)\n- self.updateWindowTitle()\n- return\n+ # get a location anchor if one exists\n+ addr = self._getLocVa(addr)\n+ fva = self.vw.getFunction(addr)\nif fva == None:\nself.vw.vprint('0x%.8x is not in a function!' % addr)\nreturn\n@@ -517,6 +528,11 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\nself.renderFunctionGraph(fva)\nself.updateWindowTitle()\n+ if fva == self.fva:\n+ self.mem_canvas.page().mainFrame().scrollToAnchor('viv:0x%.8x' % addr)\n+ self.updateWindowTitle()\n+ return\n+\nself._renderDoneSignal.emit()\nexcept Exception, e:\nprint e\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "@@ -407,6 +407,24 @@ class VQVivMemoryView(e_mem_qt.VQMemoryWindow, viv_base.VivEventCore):\nreturn title\n+ def _getRenderVaSize(self):\n+ '''\n+ Vivisect steps in and attempts to map to locations when they exist.\n+\n+ since we have a location database, let's use that to make sure we get a\n+ real location if it exists. otherwise, we end up in no-man's land,\n+ since we rely on labels, which only exist for the base of a location.\n+ '''\n+ addr, size = e_mem_qt.VQMemoryWindow._getRenderVaSize(self)\n+ if addr is None:\n+ return addr, size\n+\n+ loc = self.vw.getLocation(addr)\n+ if loc is None:\n+ return addr, size\n+\n+ return loc[L_VA], size\n+\ndef initMemoryCanvas(self, memobj, syms=None):\nreturn VQVivMemoryCanvas(memobj, syms=syms, parent=self)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
have Vivisect use the locations database for memory navigation. also, fix FuncGraph so it renders directly to a location the first time, not the start of the function.
|
718,770 |
07.12.2019 01:14:39
| 18,000 |
2297f909f0f358d4bbeaa60ba99860c39d1c7363
|
cleaner/smoother in-function nav changes.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -520,18 +520,19 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\naddr = self._getLocVa(addr)\nfva = self.vw.getFunction(addr)\n+ if fva == self.fva:\n+ self.mem_canvas.page().mainFrame().scrollToAnchor('viv:0x%.8x' % addr)\n+ self.updateWindowTitle()\n+ return\n+\nif fva == None:\nself.vw.vprint('0x%.8x is not in a function!' % addr)\nreturn\nself.clearText()\nself.renderFunctionGraph(fva)\n- self.updateWindowTitle()\n-\n- if fva == self.fva:\nself.mem_canvas.page().mainFrame().scrollToAnchor('viv:0x%.8x' % addr)\nself.updateWindowTitle()\n- return\nself._renderDoneSignal.emit()\nexcept Exception, e:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleaner/smoother in-function nav changes.
|
718,770 |
09.12.2019 09:53:16
| 18,000 |
e83bb08d1dba5cc4c5415bbe69d4f4a6bf69ccd9
|
updates per good catch!
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "@@ -57,7 +57,6 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\nself.addHotKey('ctrl+meta+S', 'viv:make:struct:multi')\nself.addHotKey('U', 'viv:undefine')\nself.addHotKey('ctrl+p', 'viv:preview:instr')\n- self.addHotKey('ctrl+s', 'viv:save')\nself.addHotKey('B', 'viv:bookmark')\nself.addHotKey('ctrl+1', 'viv:make:number:one')\nself.addHotKey('ctrl+2', 'viv:make:number:two')\n@@ -287,13 +286,6 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\nif self._canv_curva is not None:\nself.vw.previewCode(self._canv_curva)\n- @firethread\n- @vq_hotkey.hotkey('viv:save')\n- def _hotkey_save(self, fullsave=False):\n- self.vw.vprint('Saving workspace...')\n- self.vw.saveWorkspace(fullsave=fullsave)\n- self.vw.vprint('complete!')\n-\ndef getVaTag(self, va):\nloc = self.mem.getLocation(va)\nif loc != None:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updates per @rakuyo. good catch!
|
718,770 |
13.12.2019 00:21:31
| 18,000 |
057767964a84f14b82fcd33954d6b98f27fc3c4d
|
unit tests for static32 and static64
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tests/testelf.py",
"new_path": "vivisect/tests/testelf.py",
"diff": "@@ -15,8 +15,10 @@ from vivisect.tests import linux_amd64_ls_data\nfrom vivisect.tests import linux_amd64_chown_data\nfrom vivisect.tests import linux_amd64_libc_2_27_data\nfrom vivisect.tests import linux_amd64_libstdc_data\n+from vivisect.tests import linux_amd64_static_data\nfrom vivisect.tests import linux_i386_libc_2_13_data\nfrom vivisect.tests import linux_i386_libstdc_data\n+from vivisect.tests import linux_i386_static_data\nfrom vivisect.tests import linux_arm_sh_data\nfrom vivisect.tests import qnx_arm_ksh_data\nfrom vivisect.tests import openbsd_amd64_ls_data\n@@ -26,8 +28,10 @@ data = (\n(\"linux_amd64_chown\", linux_amd64_chown_data.chown_data, ('linux', 'amd64', 'chown'),),\n(\"linux_amd64_libc\", linux_amd64_libc_2_27_data.libc_data, ('linux', 'amd64', 'libc-2.27.so'),),\n(\"linux_amd64_libstdc\", linux_amd64_libstdc_data.libstdc_data, ('linux', 'amd64', 'libstdc++.so.6.0.25'),),\n+ #(\"linux_amd64_static\", linux_amd64_static_data.static64_data, ('linux', 'amd64', 'static64.llvm.elf'),),\n(\"linux_i386_libc\", linux_i386_libc_2_13_data.libc_data, ('linux', 'i386', 'libc-2.13.so'),),\n(\"linux_i386_libstdc\", linux_i386_libstdc_data.libstdc_data, ('linux', 'i386', 'libstdc++.so.6.0.25'),),\n+ #(\"linux_i386_static\", linux_i386_static_data.static32_data, ('linux', 'i386', 'static32.llvm.elf'),),\n(\"linux_arm_sh\", linux_arm_sh_data.sh_data, ('linux', 'arm', 'sh'),),\n(\"qnx_arm_ksh\", qnx_arm_ksh_data.ksh_data, ('qnx', 'arm', 'ksh'),),\n(\"openbsd_amd64_ls\", openbsd_amd64_ls_data.ls_amd64_data, ('openbsd', 'ls.amd64'),),\n@@ -138,4 +142,11 @@ class ELFTests(unittest.TestCase):\n# while they are seldom in hard targets, this is a weakness we should correct.\npass\n+ def test_minimal(self):\n+ for path in ('linux/amd64/static64.llvm.elf', 'linux/i386/static32.llvm.elf'):\n+ logger.warn(\"======== %r ========\", name)\n+ fn = helpers.getTestPath(*path)\n+ e = Elf.Elf(file(fn))\n+ vw = viv_cli.VivCli()\n+ vw.loadFromFile(fn)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
unit tests for static32 and static64
|
718,770 |
13.12.2019 19:12:32
| 18,000 |
eb5a04afe342ea81592c29acae0582e41c5179c4
|
temp fix until indirect jmp code is merged.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tests/testelf.py",
"new_path": "vivisect/tests/testelf.py",
"diff": "@@ -15,10 +15,8 @@ from vivisect.tests import linux_amd64_ls_data\nfrom vivisect.tests import linux_amd64_chown_data\nfrom vivisect.tests import linux_amd64_libc_2_27_data\nfrom vivisect.tests import linux_amd64_libstdc_data\n-from vivisect.tests import linux_amd64_static_data\nfrom vivisect.tests import linux_i386_libc_2_13_data\nfrom vivisect.tests import linux_i386_libstdc_data\n-from vivisect.tests import linux_i386_static_data\nfrom vivisect.tests import linux_arm_sh_data\nfrom vivisect.tests import qnx_arm_ksh_data\nfrom vivisect.tests import openbsd_amd64_ls_data\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
temp fix until @rakuyo's indirect jmp code is merged.
|
718,770 |
13.12.2019 20:48:21
| 18,000 |
6a30387c7a550505ed15b2f0e4744660f5e0b88b
|
stay on target!
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/tests/testelf.py",
"new_path": "vivisect/tests/testelf.py",
"diff": "@@ -141,7 +141,7 @@ class ELFTests(unittest.TestCase):\npass\ndef test_minimal(self):\n- for path in ('linux/amd64/static64.llvm.elf', 'linux/i386/static32.llvm.elf'):\n+ for path in (('linux','amd64','static64.llvm.elf'), ('linux','i386','static32.llvm.elf')):\nlogger.warn(\"======== %r ========\", path)\nfn = helpers.getTestPath(*path)\ne = Elf.Elf(file(fn))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
stay on target!
|
718,770 |
03.01.2020 17:10:27
| 18,000 |
9a73ba62bd96b9aaf47925304a3b50f77c7470c9
|
reset to (almost) the beginning. new approach.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -347,7 +347,7 @@ class Operand:\npwn on purpose to cut down on memory use and constructor CPU cost.\n\"\"\"\n- def getOperValue(self, op, emu=None, codeflow=False):\n+ def getOperValue(self, op, emu=None):\n\"\"\"\nGet the current value for the operand. If needed, use\nthe given emulator/workspace/trace to resolve things like\n@@ -571,7 +571,7 @@ class Opcode:\nret.append(name)\nreturn \" \".join(ret)\n- def getOperValue(self, idx, emu=None, codeflow=False):\n+ def getOperValue(self, idx, emu=None):\noper = self.opers[idx]\nreturn oper.getOperValue(self, emu=emu)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1486,16 +1486,16 @@ class ArmRegOper(ArmOperand):\ndef isDeref(self):\nreturn False\n- def getOperValue(self, op, emu=None, codeflow=False):\n- if self.reg == REG_PC and not codeflow:\n+ def getOperValue(self, op, emu=None):\n+ if self.reg == REG_PC:\nreturn self.va\n- if emu == None:\n+ if emu is None:\nreturn None\nreturn emu.getRegister(self.reg)\ndef setOperValue(self, op, emu=None, val=None):\n- if emu == None:\n+ if emu is None:\nreturn None\nemu.setRegister(self.reg, val)\n@@ -1505,7 +1505,6 @@ class ArmRegOper(ArmOperand):\nif self.oflags & OF_W:\nmcanv.addText(\"!\")\n-\ndef repr(self, op):\nrname = arm_regs[self.reg][0]\nif self.oflags & OF_W:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1165,7 +1165,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nself.addXref(va, tova, REF_CODE, bflags)\n# Check the instruction for static d-refs\n- for oidx, o in enumerate(op.opers):\n+ for o in op.opers:\n# FIXME it would be nice if we could just do this one time\n# in the emulation pass (or hint emulation that some have already\n# been done.\n@@ -1201,7 +1201,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nself.makeNumber(ref, o.tsize)\nelse:\n- ref = op.getOperValue(oidx, codeflow=True)\n+ ref = o.getOperValue(op)\nif brdone.get(ref, False):\ncontinue\nif ref is not None and type(ref) in (int, long) and self.isValidPointer(ref):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -716,6 +716,7 @@ class VivCodeFlowContext(e_codeflow.CodeFlowContext):\nbranches = [br for br in branches if not self._mem.isLocType(br[0],LOC_IMPORT)]\nself._mem.makeOpcode(op.va, op=op)\n+ # FIXME: future home of makeOpcode branch/xref analysis\nreturn branches\nreturn ()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
reset to (almost) the beginning. new approach.
|
718,770 |
03.01.2020 17:36:51
| 18,000 |
be1db0769e149f5e25d27df09e7908c88fd9a05e
|
generic overarching change.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -553,6 +553,14 @@ class Opcode:\n\"\"\"\nreturn ()\n+ def genRefOpers(self, emu=None):\n+ \"\"\"\n+ Search through operands and yield potential references for further\n+ analysis.\n+ \"\"\"\n+ for oidx, o in enumerate(self.opers):\n+ yield (oidx, o)\n+\ndef render(self, mcanv):\n\"\"\"\nRender this opcode to the memory canvas passed in. This is used for both\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1165,10 +1165,13 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nself.addXref(va, tova, REF_CODE, bflags)\n# Check the instruction for static d-refs\n- for o in op.opers:\n+ for oidx, o in op.genRefOpers(emu=None):\n# FIXME it would be nice if we could just do this one time\n# in the emulation pass (or hint emulation that some have already\n# been done.\n+ # unfortunately, emulation pass only occurs for code identified\n+ # within a marked function.\n+ # future fix: move this all into VivCodeFlowContext.\n# Does the operand touch memory ?\nif o.isDeref():\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
generic overarching change.
|
718,770 |
03.01.2020 17:49:47
| 18,000 |
f34e9fb2f075431b66b90fe96a619ba1023ce764
|
ARM updates to avoid making XREFS to PC+8
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -554,10 +554,12 @@ class Opcode:\nreturn ()\ndef genRefOpers(self, emu=None):\n- \"\"\"\n- Search through operands and yield potential references for further\n- analysis.\n- \"\"\"\n+ '''\n+ Operand generator, yielding an (oper-index, operand) tuple from this\n+ Opcode... but only for operands which make sense for XREF analysis.\n+ Override when architecture makes use of odd operands like the program\n+ counter, which returns a real value even without an emulator.\n+ '''\nfor oidx, o in enumerate(self.opers):\nyield (oidx, o)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -1335,6 +1335,18 @@ class ArmOpcode(envi.Opcode):\ndef __len__(self):\nreturn int(self.size)\n+ def genRefOpers(self, emu=None):\n+ '''\n+ Operand generator, yielding an (oper-index, operand) tuple from this\n+ Opcode... but only for operands which make sense for XREF analysis.\n+ Override when architecture makes use of odd operands like the program\n+ counter, which returns a real value even without an emulator.\n+ '''\n+ for oidx, o in enumerate(self.opers):\n+ if o.isReg() and o.reg == REG_PC:\n+ continue\n+ yield (oidx, o)\n+\ndef getBranches(self, emu=None):\n\"\"\"\nReturn a list of tuples. Each tuple contains the target VA of the\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
ARM updates to avoid making XREFS to PC+8
|
718,765 |
07.02.2020 11:53:45
| 18,000 |
75913fc2e46a5cf8c1b39ce7ab30dfe71c938ef7
|
add running kill list
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": "py3kill.txt",
"diff": "+Unify vdbbin and vivbin\n+Move workspace events over to a enum\n+Maybe just redo notifier entirely\n+\n+`__init__.py`:\n+test addLibraryDependency\n+test getLibraryDependency\n+addRelocation does not obey file defs\n+\n+\n+test getSymByAddr\n+Fix fixmes in getSymByAddr\n+test getSymHint\n+\n+makeFunction -- remove meta\n+\n+getXrefsTo -- burn fixme and make xrefs use MapLookup\n+\n+implement delMemoryMap\n+implement VWE_DELMMAP\n+\n+\n+getLocation doesn't use the range parameter\n+\n+test PE/petool.py and add features\n+\n+add better iterator for vs version info stuff\n+\n+test the things in bits\n+\n+who uses radixtree?\n+\n+# FIXME: use getBytesDef (and implement a dummy wrapper in VTrace for getBytesDef)\n+\n+vivisect/cli.py\n+do_symboliks --> actually use watchaddr\n+\n+\n+RIP OUT ENVI/CONFIG\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
add running kill list
|
718,770 |
24.02.2020 01:30:11
| 18,000 |
d7aedcd910e0f7c8925fdd44ac9fe9b02071445e
|
bugfix: bx<cc> shouldn't be IF_NOFALL.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -414,7 +414,7 @@ def p_misc1(opval, va): #\nRm = opval & 0xf\nolist = ( ArmRegOper(Rm, va=va), )\nif Rm == REG_LR:\n- iflags |= envi.IF_RET | envi.IF_NOFALL\n+ iflags |= envi.IF_RET\nelse:\niflags |= envi.IF_BRANCH\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: bx<cc> shouldn't be IF_NOFALL.
|
718,770 |
18.03.2020 14:15:15
| 14,400 |
a770cf496cd076353da96b295e5e5811a1bf5ef7
|
extra logging for makeFunctionThunk()
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1449,6 +1449,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nUsage: vw.makeFunctionThunk(0xvavavava, \"kernel32.CreateProcessA\")\n\"\"\"\n+ logger.info('makeFunctionThunk(0x%x, %r, addVa=%r)', fva, thname, addVa)\nself.checkNoRetApi(thname, fva)\nself.setFunctionMeta(fva, \"Thunk\", thname)\nn = self.getName(fva)\n@@ -1458,9 +1459,11 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nname = \"%s_%.8x\" % (base,fva)\nelse:\nname = base\n- self.makeName(fva, name, makeuniq=True)\n+ newname = self.makeName(fva, name, makeuniq=True)\n+ logger.debug('makeFunctionThunk: makeName(0x%x, %r, makeuniq=True): returned %r', fva, name, newname)\napi = self.getImpApi(thname)\n+ logger.debug('makeFunctionThunk: getImpApi(%r): %r', thname, api)\nif api:\n# Set any argument names that are None\nrettype,retname,callconv,callname,callargs = api\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
extra logging for makeFunctionThunk()
|
718,770 |
18.03.2020 16:52:44
| 14,400 |
b3bd7cf85d09489a970ca84ffe8e8826f2d045e7
|
wow, making up for overlapping arg names (stolen from windows, btw)
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impapi/posix/i386.py",
"new_path": "vivisect/impapi/posix/i386.py",
"diff": "@@ -40,7 +40,7 @@ api = {\n'plt__memccpy':( 'int', None, 'cdecl', '*._memccpy', (('int', None), ('int', None), ('int', None), ('int', None)) ),\n'plt__memicmp':( 'int', None, 'cdecl', '*._memicmp', (('int', None), ('int', None), ('int', None)) ),\n'plt__snprintf':( 'int', None, 'cdecl', '*._snprintf', (('int', None), ('int', None), ('int', None)) ),\n- 'plt__snwprintf':( 'int', None, 'cdecl', '*._snwprintf', (('void *', 'ptr'), ('int', None), ('void *', 'ptr')) ),\n+ 'plt__snwprintf':( 'int', None, 'cdecl', '*._snwprintf', (('void *', 'buffer'), ('int', 'count'), ('void *', 'fmt')) ),\n'plt__splitpath':( 'int', None, 'cdecl', '*._splitpath', (('int', None), ('int', None), ('int', None), ('int', None), ('int', None)) ),\n'plt__strcmpi':( 'int', None, 'cdecl', '*._strcmpi', (('int', None), ('int', None)) ),\n'plt__stricmp':( 'int', None, 'cdecl', '*._stricmp', (('int', None), ('int', None)) ),\n@@ -94,7 +94,7 @@ api = {\n'plt_memchr':( 'int', None, 'cdecl', '*.memchr', (('int', None), ('int', None), ('int', None)) ),\n'plt_memcmp':( 'int', None, 'cdecl', '*.memcmp', (('int', None), ('int', None), ('int', None)) ),\n'plt_memcpy':( 'int', None, 'cdecl', '*.memcpy', (('int', None), ('int', None), ('int', None)) ),\n- 'plt_memmove':( 'int', None, 'cdecl', '*.memmove', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt_memmove':( 'int', None, 'cdecl', '*.memmove', (('void *', 'dst'), ('void *', 'src'), ('int', 'count')) ),\n'plt_memset':( 'int', None, 'cdecl', '*.memset', (('int', None), ('int', None), ('int', None)) ),\n'plt_pow':( 'int', None, 'cdecl', '*.pow', () ),\n'plt_qsort':( 'int', None, 'stdcall', '*.qsort', ( ('void *', 'funcptr'), ('int', None), ('int', None), ('void *', 'funcptr'), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None)) ),\n@@ -129,7 +129,7 @@ api = {\n'plt_wcscat':( 'int', None, 'cdecl', '*.wcscat', (('int', None), ('void *', 'ptr')) ),\n'plt_wcschr':( 'int', None, 'cdecl', '*.wcschr', (('void *', 'ptr'), ('int', None)) ),\n'plt_wcscmp':( 'int', None, 'cdecl', '*.wcscmp', (('void *', 'ptr'), ('int', None)) ),\n- 'plt_wcscpy':( 'int', None, 'cdecl', '*.wcscpy', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt_wcscpy':( 'int', None, 'cdecl', '*.wcscpy', (('void *', 'dst'), ('void *', 'src')) ),\n'plt_wcscspn':( 'int', None, 'cdecl', '*.wcscspn', (('void *', 'ptr'), ('int', None)) ),\n'plt_wcslen':( 'int', None, 'cdecl', '*.wcslen', (('void *', 'ptr'),) ),\n'plt_wcsncat':( 'int', None, 'cdecl', '*.wcsncat', (('void *', 'ptr'), ('int', None), ('int', None)) ),\n@@ -154,12 +154,12 @@ api = {\n'plt_lstrcat':( 'int', None, 'stdcall', '*.lstrcat', (('int', None), ('int', None)) ),\n'plt_lstrcata':( 'int', None, 'stdcall', '*.lstrcatA', (('int', None), ('int', None)) ),\n'plt_lstrcatw':( 'int', None, 'stdcall', '*.lstrcatW', (('int', None), ('void *', 'ptr')) ),\n- 'plt_lstrcmp':( 'int', None, 'stdcall', '*.lstrcmp', (('void *', 'ptr'), ('int', None)) ),\n- 'plt_lstrcmpa':( 'int', None, 'stdcall', '*.lstrcmpA', (('void *', 'ptr'), ('int', None)) ),\n- 'plt_lstrcmpw':( 'int', None, 'stdcall', '*.lstrcmpW', (('void *', 'ptr'), ('void *', 'ptr')) ),\n- 'plt_lstrcmpi':( 'int', None, 'stdcall', '*.lstrcmpi', (('int', None), ('int', None)) ),\n- 'plt_lstrcmpia':( 'int', None, 'stdcall', '*.lstrcmpiA', (('int', None), ('int', None)) ),\n- 'plt_lstrcmpiw':( 'int', None, 'stdcall', '*.lstrcmpiW', (('int', None), ('int', None)) ),\n+ 'plt_lstrcmp':( 'int', None, 'stdcall', '*.lstrcmp', (('void *', 'str1'), ('void *', 'str2')) ),\n+ 'plt_lstrcmpa':( 'int', None, 'stdcall', '*.lstrcmpA', (('void *', 'str1'), ('void *', 'str2')) ),\n+ 'plt_lstrcmpw':( 'int', None, 'stdcall', '*.lstrcmpW', (('void *', 'str1'), ('void *', 'str2')) ),\n+ 'plt_lstrcmpi':( 'int', None, 'stdcall', '*.lstrcmpi', (('void *', 'str1'), ('void *', 'str2')) ),\n+ 'plt_lstrcmpia':( 'int', None, 'stdcall', '*.lstrcmpiA', (('void *', 'str1'), ('void *', 'str2')) ),\n+ 'plt_lstrcmpiw':( 'int', None, 'stdcall', '*.lstrcmpiW', (('void *', 'str1'), ('void *', 'str2')) ),\n'plt_lstrcpy':( 'int', None, 'stdcall', '*.lstrcpy', (('int', None), ('int', None)) ),\n'plt_lstrcpya':( 'int', None, 'stdcall', '*.lstrcpyA', (('int', None), ('int', None)) ),\n'plt_lstrcpyw':( 'int', None, 'stdcall', '*.lstrcpyW', (('int', None), ('int', None)) ),\n@@ -174,7 +174,7 @@ api = {\n'plt__getmonths':( 'int', None, 'cdecl', '*._Getmonths', () ),\n'plt__gettnames':( 'int', None, 'cdecl', '*._Gettnames', () ),\n'plt__huge':( 'int', None, 'cdecl', '*._HUGE', () ),\n- 'plt__strftime':( 'int', None, 'cdecl', '*._Strftime', (('void *', 'ptr'), ('int', None), ('void *', 'ptr'), ('int', None), ('int', None)) ),\n+ 'plt__strftime':( 'int', None, 'cdecl', '*._Strftime', (('void *', 's'), ('int', 'max'), ('void *', 'fmt'), ('int', 'tm'), ('int', None)) ),\n'plt__xcptfilter':( 'int', None, 'cdecl', '*._XcptFilter', (('int', None), ('int', None)) ),\n'plt___cppxcptfilter':( 'int', None, 'cdecl', '*.__CppXcptFilter', (('int', None), ('int', None)) ),\n'plt___cxxcallunwinddtor':( 'int', None, 'cdecl', '*.__CxxCallUnwindDtor', (('void *', 'funcptr'), ('int', None)) ),\n@@ -201,11 +201,11 @@ api = {\n'plt___argv':( 'int', None, 'cdecl', '*.__argv', () ),\n'plt___badioinfo':( 'int', None, 'cdecl', '*.__badioinfo', () ),\n'plt___buffer_overrun':( 'int', None, 'cdecl', '*.__buffer_overrun', () ),\n- 'plt___crtcomparestringa':( 'int', None, 'cdecl', '*.__crtCompareStringA', (('int', None), ('int', None), ('void *', 'ptr'), ('int', None), ('void *', 'ptr'), ('int', None), ('int', None)) ),\n- 'plt___crtcomparestringw':( 'int', None, 'cdecl', '*.__crtCompareStringW', (('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None), ('int', None)) ),\n+ 'plt___crtcomparestringa':( 'int', None, 'cdecl', '*.__crtCompareStringA', (('int', 'Locale'), ('int', 'dwCmpFlags'), ('void *', 'lpString1'), ('int', 'cchCount1'), ('void *', 'lpString2'), ('int', 'cchCount2'), ('int', 'code_page')) ),\n+ 'plt___crtcomparestringw':( 'int', None, 'cdecl', '*.__crtCompareStringW', (('int', 'Locale'), ('int', 'dwCmpFlags'), ('void *', 'lpString1'), ('int', 'cchCount1'), ('void *', 'lpString2'), ('int', 'cchCount2'), ('int', 'code_page')) ),\n'plt___crtgetlocaleinfow':( 'int', None, 'cdecl', '*.__crtGetLocaleInfoW', (('int', None), ('int', None), ('int', None), ('int', None), ('int', None)) ),\n'plt___crtgetstringtypew':( 'int', None, 'cdecl', '*.__crtGetStringTypeW', (('int', None), ('int', None), ('int', None), ('void *', 'ptr'), ('int', None), ('int', None)) ),\n- 'plt___crtlcmapstringa':( 'int', None, 'cdecl', '*.__crtLCMapStringA', (('int', None), ('int', None), ('void *', 'ptr'), ('int', None), ('void *', 'ptr'), ('int', None), ('int', None), ('int', None)) ),\n+ 'plt___crtlcmapstringa':( 'int', None, 'cdecl', '*.__crtLCMapStringA', (('int', 'LocalName'), ('int', 'dwMapFlags'), ('void *', 'lpSrcStr'), ('int', 'cchSrc'), ('void *', 'lpDstStr''), ('int', 'cchDst'), ('int', 'code_page'), ('int', 'bError')) ),\n'plt___crtlcmapstringw':( 'int', None, 'cdecl', '*.__crtLCMapStringW', (('int', None), ('int', None), ('int', None), ('int', None), ('void *', 'ptr'), ('int', None), ('int', None)) ),\n'plt___dllonexit':( 'int', None, 'cdecl', '*.__dllonexit', (('int', None), ('int', None), ('int', None)) ),\n'plt___doserrno':( 'int', None, 'cdecl', '*.__doserrno', () ),\n@@ -472,7 +472,7 @@ api = {\n'plt__longjmpex':( 'int', None, 'cdecl', '*._longjmpex', (('int', None), ('int', None)) ),\n'plt__lrotl':( 'int', None, 'cdecl', '*._lrotl', (('int', None), ('int', None)) ),\n'plt__lrotr':( 'int', None, 'cdecl', '*._lrotr', (('int', None), ('int', None)) ),\n- 'plt__lsearch':( 'int', None, 'cdecl', '*._lsearch', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None), ('int', None), ('void *', 'funcptr')) ),\n+ 'plt__lsearch':( 'int', None, 'cdecl', '*._lsearch', (('void *', 'key'), ('void *', 'base'), ('int', 'nmemb'), ('int', 'size'), ('void *', 'cmpptr')) ),\n'plt__lseek':( 'int', None, 'cdecl', '*._lseek', (('int', None), ('int', None), ('int', None)) ),\n'plt__lseeki64':( 'int', None, 'cdecl', '*._lseeki64', (('int', None), ('int', None), ('int', None), ('int', None)) ),\n'plt__ltoa':( 'int', None, 'cdecl', '*._ltoa', (('int', None), ('void *', 'obj'), ('int', None)) ),\n@@ -492,35 +492,35 @@ api = {\n'plt__mbctoupper':( 'int', None, 'cdecl', '*._mbctoupper', (('int', None),) ),\n'plt__mbctype':( 'int', None, 'cdecl', '*._mbctype', () ),\n'plt__mbsbtype':( 'int', None, 'cdecl', '*._mbsbtype', (('int', None), ('int', None)) ),\n- 'plt__mbscat':( 'int', None, 'cdecl', '*._mbscat', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__mbscat':( 'int', None, 'cdecl', '*._mbscat', (('void *', 'mbstr1'), ('void *', 'mbstr2')) ),\n'plt__mbschr':( 'int', None, 'cdecl', '*._mbschr', (('int', None), ('int', None)) ),\n'plt__mbscmp':( 'int', None, 'cdecl', '*._mbscmp', (('int', None), ('int', None)) ),\n- 'plt__mbscoll':( 'int', None, 'cdecl', '*._mbscoll', (('void *', 'ptr'), ('void *', 'ptr')) ),\n- 'plt__mbscpy':( 'int', None, 'cdecl', '*._mbscpy', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__mbscoll':( 'int', None, 'cdecl', '*._mbscoll', (('void *', 'mbstr1'), ('void *', 'mbstr2')) ),\n+ 'plt__mbscpy':( 'int', None, 'cdecl', '*._mbscpy', (('void *', 'mbstr1'), ('void *', 'mbstr2')) ),\n'plt__mbscspn':( 'int', None, 'cdecl', '*._mbscspn', (('int', None), ('int', None)) ),\n'plt__mbsdec':( 'int', None, 'cdecl', '*._mbsdec', (('int', None), ('int', None)) ),\n'plt__mbsdup':( 'int', None, 'cdecl', '*._mbsdup', (('void *', 'ptr'),) ),\n- 'plt__mbsicmp':( 'int', None, 'cdecl', '*._mbsicmp', (('void *', 'ptr'), ('void *', 'ptr')) ),\n- 'plt__mbsicoll':( 'int', None, 'cdecl', '*._mbsicoll', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__mbsicmp':( 'int', None, 'cdecl', '*._mbsicmp', (('void *', 'mbstr1'), ('void *', 'mbstr2')) ),\n+ 'plt__mbsicoll':( 'int', None, 'cdecl', '*._mbsicoll', (('void *', 'mbstr1'), ('void *', 'mbstr2')) ),\n'plt__mbsinc':( 'int', None, 'cdecl', '*._mbsinc', (('int', None),) ),\n'plt__mbslen':( 'int', None, 'cdecl', '*._mbslen', (('int', None),) ),\n'plt__mbslwr':( 'int', None, 'cdecl', '*._mbslwr', (('void *', 'ptr'),) ),\n'plt__mbsnbcat':( 'int', None, 'cdecl', '*._mbsnbcat', (('int', None), ('int', None), ('int', None)) ),\n'plt__mbsnbcmp':( 'int', None, 'cdecl', '*._mbsnbcmp', (('int', None), ('int', None), ('int', None)) ),\n'plt__mbsnbcnt':( 'int', None, 'cdecl', '*._mbsnbcnt', (('int', None), ('int', None)) ),\n- 'plt__mbsnbcoll':( 'int', None, 'cdecl', '*._mbsnbcoll', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt__mbsnbcoll':( 'int', None, 'cdecl', '*._mbsnbcoll', (('void *', 'mbstr1'), ('void *', 'mbstr2'), ('int', 'count')) ),\n'plt__mbsnbcpy':( 'int', None, 'cdecl', '*._mbsnbcpy', (('int', None), ('void *', 'ptr'), ('int', None)) ),\n'plt__mbsnbicmp':( 'int', None, 'cdecl', '*._mbsnbicmp', (('int', None), ('int', None), ('int', None)) ),\n- 'plt__mbsnbicoll':( 'int', None, 'cdecl', '*._mbsnbicoll', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt__mbsnbicoll':( 'int', None, 'cdecl', '*._mbsnbicoll', (('void *', 'mbstr1'), ('void *', 'mbstr2'), ('int', 'count')) ),\n'plt__mbsnbset':( 'int', None, 'cdecl', '*._mbsnbset', (('int', None), ('int', None), ('int', None)) ),\n'plt__mbsncat':( 'int', None, 'cdecl', '*._mbsncat', (('void *', 'ptr'), ('int', None), ('int', None)) ),\n'plt__mbsnccnt':( 'int', None, 'cdecl', '*._mbsnccnt', (('int', None), ('int', None)) ),\n'plt__mbsncmp':( 'int', None, 'cdecl', '*._mbsncmp', (('int', None), ('int', None), ('int', None)) ),\n- 'plt__mbsncoll':( 'int', None, 'cdecl', '*._mbsncoll', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt__mbsncoll':( 'int', None, 'cdecl', '*._mbsncoll', (('void *', 'mbstr1'), ('void *', 'mbstr2'), ('int', 'count')) ),\n'plt__mbsncpy':( 'int', None, 'cdecl', '*._mbsncpy', (('int', None), ('void *', 'ptr'), ('int', None)) ),\n'plt__mbsnextc':( 'int', None, 'cdecl', '*._mbsnextc', (('int', None),) ),\n'plt__mbsnicmp':( 'int', None, 'cdecl', '*._mbsnicmp', (('int', None), ('int', None), ('int', None)) ),\n- 'plt__mbsnicoll':( 'int', None, 'cdecl', '*._mbsnicoll', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt__mbsnicoll':( 'int', None, 'cdecl', '*._mbsnicoll', (('void *', 'mbstr1'), ('void *', 'mbstr2'), ('int', 'count')) ),\n'plt__mbsninc':( 'int', None, 'cdecl', '*._mbsninc', (('int', None), ('int', None)) ),\n'plt__mbsnset':( 'int', None, 'cdecl', '*._mbsnset', (('int', None), ('int', None), ('int', None)) ),\n'plt__mbspbrk':( 'int', None, 'cdecl', '*._mbspbrk', (('int', None), ('int', None)) ),\n@@ -529,7 +529,7 @@ api = {\n'plt__mbsset':( 'int', None, 'cdecl', '*._mbsset', (('int', None), ('int', None)) ),\n'plt__mbsspn':( 'int', None, 'cdecl', '*._mbsspn', (('int', None), ('int', None)) ),\n'plt__mbsspnp':( 'int', None, 'cdecl', '*._mbsspnp', (('int', None), ('int', None)) ),\n- 'plt__mbsstr':( 'int', None, 'cdecl', '*._mbsstr', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__mbsstr':( 'int', None, 'cdecl', '*._mbsstr', (('void *', 'mbstr1'), ('void *', 'mbstrkey')) ),\n'plt__mbstok':( 'int', None, 'cdecl', '*._mbstok', (('int', None), ('int', None)) ),\n'plt__mbstrlen':( 'int', None, 'cdecl', '*._mbstrlen', (('int', None),) ),\n'plt__mbsupr':( 'int', None, 'cdecl', '*._mbsupr', (('void *', 'ptr'),) ),\n@@ -573,7 +573,7 @@ api = {\n'plt__scalb':( 'int', None, 'cdecl', '*._scalb', (('int', None), ('int', None), ('int', None)) ),\n'plt__scprintf':( 'int', None, 'cdecl', '*._scprintf', (('int', None),) ),\n'plt__scwprintf':( 'int', None, 'cdecl', '*._scwprintf', (('int', None),) ),\n- 'plt__searchenv':( 'int', None, 'cdecl', '*._searchenv', (('void *', 'ptr'), ('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__searchenv':( 'int', None, 'cdecl', '*._searchenv', (('void *', 'name'), ('void *', 'env_var'), ('void *', 'buffer')) ),\n'plt__seh_longjmp_unwind':( 'int', None, 'stdcall', '*._seh_longjmp_unwind', (('int', None),) ),\n'plt__set_sse2_enable':( 'int', None, 'cdecl', '*._set_SSE2_enable', (('int', None),) ),\n'plt__set_error_mode':( 'int', None, 'cdecl', '*._set_error_mode', (('int', None),) ),\n@@ -611,11 +611,11 @@ api = {\n'plt__strdup':( 'int', None, 'cdecl', '*._strdup', (('void *', 'ptr'),) ),\n'plt__strerror':( 'int', None, 'cdecl', '*._strerror', (('int', None),) ),\n'plt__stricmp':( 'int', None, 'cdecl', '*._stricmp', (('int', None), ('void *', 'ptr')) ),\n- 'plt__stricoll':( 'int', None, 'cdecl', '*._stricoll', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__stricoll':( 'int', None, 'cdecl', '*._stricoll', (('void *', 'str1'), ('void *', 'str2')) ),\n'plt__strlwr':( 'int', None, 'cdecl', '*._strlwr', (('void *', 'ptr'),) ),\n- 'plt__strncoll':( 'int', None, 'cdecl', '*._strncoll', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt__strncoll':( 'int', None, 'cdecl', '*._strncoll', (('void *', 'str1'), ('void *', 'str2'), ('int', None)) ),\n'plt__strnicmp':( 'int', None, 'cdecl', '*._strnicmp', (('int', None), ('void *', 'ptr'), ('int', None)) ),\n- 'plt__strnicoll':( 'int', None, 'cdecl', '*._strnicoll', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt__strnicoll':( 'int', None, 'cdecl', '*._strnicoll', (('void *', 'str1'), ('void *', 'str2'), ('int', None)) ),\n'plt__strnset':( 'int', None, 'cdecl', '*._strnset', (('int', None), ('int', None), ('int', None)) ),\n'plt__strrev':( 'int', None, 'cdecl', '*._strrev', (('int', None),) ),\n'plt__strset':( 'int', None, 'cdecl', '*._strset', (('int', None), ('int', None)) ),\n@@ -628,7 +628,7 @@ api = {\n'plt__sys_nerr':( 'int', None, 'bfastcall', '*._sys_nerr', (('int', None),) ),\n'plt__tell':( 'int', None, 'cdecl', '*._tell', (('int', None),) ),\n'plt__telli64':( 'int', None, 'cdecl', '*._telli64', (('int', None),) ),\n- 'plt__tempnam':( 'int', None, 'cdecl', '*._tempnam', (('void *', 'ptr'), ('void *', 'ptr')) ),\n+ 'plt__tempnam':( 'int', None, 'cdecl', '*._tempnam', (('void *', 'dir'), ('void *', 'pfx')) ),\n'plt__time64':( 'int', None, 'cdecl', '*._time64', (('void *', 'ptr'),) ),\n'plt__timezone':( 'int', None, 'bfastcall', '*._timezone', (('int', None),) ),\n'plt__tolower':( 'int', None, 'cdecl', '*._tolower', (('int', None),) ),\n@@ -712,7 +712,7 @@ api = {\n'plt__wrename':( 'int', None, 'cdecl', '*._wrename', (('int', None), ('int', None)) ),\n'plt__write':( 'int', None, 'cdecl', '*._write', (('int', None), ('void *', 'ptr'), ('DWORD', None)) ),\n'plt__wrmdir':( 'int', None, 'cdecl', '*._wrmdir', (('int', None),) ),\n- 'plt__wsearchenv':( 'int', None, 'cdecl', '*._wsearchenv', (('void *', 'ptr'), ('int', None), ('void *', 'ptr')) ),\n+ 'plt__wsearchenv':( 'int', None, 'cdecl', '*._wsearchenv', (('void *', 'filename'), ('void *', 'varname'), ('void *', 'size')) ),\n'plt__wsetlocale':( 'int', None, 'cdecl', '*._wsetlocale', (('int', None), ('void *', 'ptr')) ),\n'plt__wsopen':( 'int', None, 'cdecl', '*._wsopen', (('StringW', None), ('int', None), ('int', None), ('int', None)) ),\n'plt__wspawnl':( 'int', None, 'cdecl', '*._wspawnl', (('int', None), ('void *', 'obj')) ),\n@@ -838,12 +838,12 @@ api = {\n'plt_malloc':( 'int', None, 'cdecl', '*.malloc', (('DWORD', None),) ),\n'plt_mblen':( 'int', None, 'cdecl', '*.mblen', (('int', None), ('int', None)) ),\n'plt_mbstowcs':( 'int', None, 'cdecl', '*.mbstowcs', (('int', None), ('void *', 'ptr'), ('int', None)) ),\n- 'plt_mbtowc':( 'int', None, 'cdecl', '*.mbtowc', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n+ 'plt_mbtowc':( 'int', None, 'cdecl', '*.mbtowc', (('void *', 'dst'), ('void *', 'src'), ('int', 'max')) ),\n'plt_memchr':( 'int', None, 'cdecl', '*.memchr', (('int', None), ('int', None), ('int', None)) ),\n'plt_memcmp':( 'int', None, 'cdecl', '*.memcmp', (('void *', 'ptr'), ('int', None), ('int', None)) ),\n- 'plt_memcpy':( 'int', None, 'cdecl', '*.memcpy', (('void *', 'ptr'), ('void *', 'ptr'), ('int', None)) ),\n- 'plt_memmove':( 'int', None, 'cdecl', '*.memmove', (('int', None), ('void *', 'ptr'), ('int', None)) ),\n- 'plt_memset':( 'int', None, 'cdecl', '*.memset', (('void *', 'ptr'), ('int', None), ('int', None)) ),\n+ 'plt_memcpy':( 'int', None, 'cdecl', '*.memcpy', (('void *', 'dst'), ('void *', 'src'), ('int', 'count')) ),\n+ 'plt_memmove':( 'int', None, 'cdecl', '*.memmove', (('void *', 'dst'), ('void *', 'src'), ('int', 'count')) ),\n+ 'plt_memset':( 'int', None, 'cdecl', '*.memset', (('void *', 'ptr'), ('int', 'char'), ('int', None)) ),\n'plt_mktime':( 'int', None, 'cdecl', '*.mktime', (('int', None),) ),\n'plt_modf':( 'int', None, 'cdecl', '*.modf', (('int', None), ('int', None)) ),\n'plt_perror':( 'int', None, 'cdecl', '*.perror', (('void *', 'ptr'),) ),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
wow, making up for overlapping arg names (stolen from windows, btw)
|
718,770 |
19.03.2020 20:53:18
| 14,400 |
69946d24dbe7b1eab64ed8a432260a994869115b
|
main code. simple.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1226,8 +1226,15 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n'''\nShow the repr of an instruction in the current canvas *before* making it that\n'''\n+ try:\nop = self.parseOpcode(va, arch)\n+ if op == None:\n+ self.vprint(\"0x%x - None\")\n+ else:\nself.vprint(\"0x%x (%d bytes) %s\" % (va, len(op), repr(op)))\n+ except Exception, e:\n+ self.vprint(\"0x%x - decode exception\" % va)\n+ logger.exception(\"preview opcode exception:\")\n#################################################################\n#\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
main code. simple.
|
718,770 |
19.03.2020 23:01:19
| 14,400 |
3b97ca0ff547c353823b3c386478969f87fefbf5
|
and menu Action protection
|
[
{
"change_type": "MODIFY",
"old_path": "vqt/menubuilder.py",
"new_path": "vqt/menubuilder.py",
"diff": "@@ -3,6 +3,9 @@ try:\nexcept:\nfrom PyQt4.QtGui import *\n+import logging\n+logger = logging.getLogger(__name__)\n+\nclass FieldAdder:\ndef __init__(self, splitchar='.'):\n@@ -84,4 +87,8 @@ class ActionCall:\nself.callback = callback\ndef __call__(self):\n- return self.callback(*self.args, **self.kwargs)\n+ try:\n+ retval = self.callback(*self.args, **self.kwargs)\n+ return retval\n+ except Exception as e:\n+ logger.exception(\"ActionCall: %r\" % self.callback)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
and menu Action protection
|
718,770 |
20.03.2020 09:47:17
| 14,400 |
df3571003567d2071d40cc9e96ebf1ecb9c18364
|
hopefully get travis fixed on first try...
|
[
{
"change_type": "MODIFY",
"old_path": ".travis.yml",
"new_path": ".travis.yml",
"diff": "@@ -15,7 +15,7 @@ python:\ninstall:\n- \"travis_retry sudo apt-get update\"\n- git clone https://github.com/vivisect/vivtestfiles.git /tmp/vivtestfiles\n- - \"travis_retry sudo apt-get -qq install libfreetype6-dev liblcms2-dev python-qt4 ghostscript libffi-dev libjpeg-turbo-progs cmake imagemagick\"\n+ - \"travis_retry sudo apt-get -qq install libfreetype6-dev liblcms2-dev python-pyqt5 ghostscript libffi-dev libjpeg-turbo-progs cmake imagemagick\"\n- pip install msgpack-python\n- pip install cxxfilt\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
hopefully get travis fixed on first try...
|
718,770 |
20.03.2020 11:31:25
| 14,400 |
27203d714ef16b5c57041365ca982c91573f29df
|
try something new.
|
[
{
"change_type": "MODIFY",
"old_path": ".travis.yml",
"new_path": ".travis.yml",
"diff": "@@ -12,6 +12,9 @@ language: python\npython:\n- \"2.7\"\n+virtualenv:\n+ system_site_packages: true\n+\ninstall:\n- \"travis_retry sudo apt-get update\"\n- git clone https://github.com/vivisect/vivtestfiles.git /tmp/vivtestfiles\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
try something new.
|
718,770 |
20.03.2020 14:27:42
| 14,400 |
9c89d7f9b546bbc1504b0d74f784ba22639ce257
|
variable renaming error
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1021,7 +1021,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nlogger.warn(\"complete implementing vcvt\")\nsrcwidth = op.opers[0].getWidth()\n- regcnt = width / 4\n+ regcnt = srcwidth / 4\nfirstOP = None\nif op.simdflags & ifs_first_F32:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
variable renaming error
|
718,770 |
21.03.2020 15:09:22
| 14,400 |
7566b81ca5be23e8a4bc236672dd2afa5bdb9a96
|
remove duplication of Emulator.getMeta/setMeta
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -670,15 +670,6 @@ class Emulator(e_reg.RegisterContext, e_mem.MemoryObject):\n\"\"\"\nself.metadata[name] = value\n- def getMeta(self, name, default=None):\n- return self.metadata.get(name, default)\n-\n- def setMeta(self, name, value):\n- \"\"\"\n- Set a meta key,value pair for this workspace.\n- \"\"\"\n- self.metadata[name] = value\n-\ndef getArchModule(self):\nraise Exception('Emulators *must* implement getArchModule()!')\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
remove duplication of Emulator.getMeta/setMeta
|
718,770 |
21.03.2020 15:30:42
| 14,400 |
5ad9cf853fac5b34c6cf4bf25b96c6c2d95756e8
|
cleanup per
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -5,16 +5,6 @@ import traceback\nimport envi\nimport envi.bits as e_bits\n-from envi.bits import binary\n-\n-#import sys\n-#import struct\n-#import traceback\n-\n-#import envi\n-#import envi.bits as e_bits\n-#from envi.bits import binary\n-\nfrom envi.archs.arm.const import *\nfrom envi.archs.arm.regs import *\n@@ -49,67 +39,68 @@ def addrToName(mcanv, va):\nreturn repr(sym)\nreturn \"0x%.8x\" % va\n+\n# The keys in this table are made of the\n# concat of bits 27-21 and 7-4 (only when\n# ienc == mul!\niencmul_codes = {\n# Basic multiplication opcodes\n- binary(\"000000001001\"): (\"mul\", INS_MUL, (0,4,2), 0),\n- binary(\"000000011001\"): (\"mul\", INS_MUL, (0,4,2), IF_PSR_S),\n- binary(\"000000101001\"): (\"mla\", INS_MLA, (0,4,2,1), 0),\n- binary(\"000000111001\"): (\"mla\", INS_MLA, (0,4,2,1), IF_PSR_S),\n- binary(\"000001101001\"): (\"mls\", INS_MLS, (0,4,2,1), 0),\n- binary(\"000001001001\"): (\"umaal\", INS_UMAAL,(1,0,4,2), 0),\n- binary(\"000010001001\"): (\"umull\", INS_UMULL,(1,0,4,2), 0),\n- binary(\"000010011001\"): (\"umull\", INS_UMULL,(1,0,4,2), IF_PSR_S),\n- binary(\"000010101001\"): (\"umlal\", INS_UMLAL,(1,0,4,2), 0),\n- binary(\"000010111001\"): (\"umlal\", INS_UMLAL,(1,0,4,2), IF_PSR_S),\n- binary(\"000011001001\"): (\"smull\", INS_SMULL,(1,0,4,2), 0),\n- binary(\"000011011001\"): (\"smull\", INS_SMULL,(1,0,4,2), IF_PSR_S),\n- binary(\"000011101001\"): (\"smlal\", INS_SMLAL,(1,0,4,2), 0),\n- binary(\"000011111001\"): (\"smlal\", INS_SMLAL,(1,0,4,2), IF_PSR_S),\n+ 0b000000001001: (\"mul\", INS_MUL, (0, 4, 2), 0),\n+ 0b000000011001: (\"mul\", INS_MUL, (0, 4, 2), IF_PSR_S),\n+ 0b000000101001: (\"mla\", INS_MLA, (0, 4, 2, 1), 0),\n+ 0b000000111001: (\"mla\", INS_MLA, (0, 4, 2, 1), IF_PSR_S),\n+ 0b000001101001: (\"mls\", INS_MLS, (0, 4, 2, 1), 0),\n+ 0b000001001001: (\"umaal\", INS_UMAAL,(1, 0, 4, 2), 0),\n+ 0b000010001001: (\"umull\", INS_UMULL, (1, 0, 4, 2), 0),\n+ 0b000010011001: (\"umull\", INS_UMULL, (1, 0, 4, 2), IF_PSR_S),\n+ 0b000010101001: (\"umlal\", INS_UMLAL, (1, 0, 4, 2), 0),\n+ 0b000010111001: (\"umlal\", INS_UMLAL, (1, 0, 4, 2), IF_PSR_S),\n+ 0b000011001001: (\"smull\", INS_SMULL, (1, 0, 4, 2), 0),\n+ 0b000011011001: (\"smull\", INS_SMULL, (1, 0, 4, 2), IF_PSR_S),\n+ 0b000011101001: (\"smlal\", INS_SMLAL, (1, 0, 4, 2), 0),\n+ 0b000011111001: (\"smlal\", INS_SMLAL, (1, 0, 4, 2), IF_PSR_S),\n# multiplys with <x><y>\n# \"B\n- binary(\"000100001000\"): (\"smlabb\", INS_SMLABB, (0,4,2,1), 0),\n- binary(\"000100001010\"): (\"smlatb\", INS_SMLATB, (0,4,2,1), 0),\n- binary(\"000100001100\"): (\"smlabt\", INS_SMLABT, (0,4,2,1), 0),\n- binary(\"000100001110\"): (\"smlatt\", INS_SMLATT, (0,4,2,1), 0),\n- binary(\"000100101010\"): (\"smulwb\", INS_SMULWB, (0,4,2), 0),\n- binary(\"000100101110\"): (\"smulwt\", INS_SMULWT, (0,4,2), 0),\n- binary(\"000100101000\"): (\"smlawb\", INS_SMLAWB, (0,4,2), 0),\n- binary(\"000100101100\"): (\"smlawt\", INS_SMLAWT, (0,4,2), 0),\n- binary(\"000101001000\"): (\"smlalbb\",INS_SMLALBB, (1,0,4,2), 0),\n- binary(\"000101001010\"): (\"smlaltb\",INS_SMLALTB, (1,0,4,2), 0),\n- binary(\"000101001100\"): (\"smlalbt\",INS_SMLALBT, (1,0,4,2), 0),\n- binary(\"000101001110\"): (\"smlaltt\",INS_SMLALTT, (1,0,4,2), 0),\n- binary(\"000101101000\"): (\"smulbb\", INS_SMULBB, (0,4,2), 0),\n- binary(\"000101101010\"): (\"smultb\", INS_SMULTB, (0,4,2), 0),\n- binary(\"000101101100\"): (\"smulbt\", INS_SMULBT, (0,4,2), 0),\n- binary(\"000101101110\"): (\"smultt\", INS_SMULTT, (0,4,2), 0),\n+ 0b000100001000: (\"smlabb\", INS_SMLABB, (0, 4, 2, 1), 0),\n+ 0b000100001010: (\"smlatb\", INS_SMLATB, (0, 4, 2, 1), 0),\n+ 0b000100001100: (\"smlabt\", INS_SMLABT, (0, 4, 2, 1), 0),\n+ 0b000100001110: (\"smlatt\", INS_SMLATT, (0, 4, 2, 1), 0),\n+ 0b000100101010: (\"smulwb\", INS_SMULWB, (0, 4, 2), 0),\n+ 0b000100101110: (\"smulwt\", INS_SMULWT, (0, 4, 2), 0),\n+ 0b000100101000: (\"smlawb\", INS_SMLAWB, (0, 4, 2), 0),\n+ 0b000100101100: (\"smlawt\", INS_SMLAWT, (0, 4, 2), 0),\n+ 0b000101001000: (\"smlalbb\",INS_SMLALBB, (1, 0, 4, 2), 0),\n+ 0b000101001010: (\"smlaltb\",INS_SMLALTB, (1, 0, 4, 2), 0),\n+ 0b000101001100: (\"smlalbt\",INS_SMLALBT, (1, 0, 4, 2), 0),\n+ 0b000101001110: (\"smlaltt\",INS_SMLALTT, (1, 0, 4, 2), 0),\n+ 0b000101101000: (\"smulbb\", INS_SMULBB, (0, 4, 2), 0),\n+ 0b000101101010: (\"smultb\", INS_SMULTB, (0, 4, 2), 0),\n+ 0b000101101100: (\"smulbt\", INS_SMULBT, (0, 4, 2), 0),\n+ 0b000101101110: (\"smultt\", INS_SMULTT, (0, 4, 2), 0),\n# type 2 multiplys\n- binary(\"011100000001\"): (\"smuad\", INS_SMUAD, (0,4,2), 0),\n- binary(\"011100000011\"): (\"smuadx\", INS_SMUADX, (0,4,2), 0),\n- binary(\"011100000101\"): (\"smusd\", INS_SMUSD, (0,4,2), 0),\n- binary(\"011100000111\"): (\"smusdx\", INS_SMUSDX, (0,4,2), 0),\n- binary(\"011100000001\"): (\"smlad\", INS_SMLAD, (0,4,2,1), 0),\n- binary(\"011100000011\"): (\"smladx\", INS_SMLADX, (0,4,2,1), 0),\n- binary(\"011100000101\"): (\"smlsd\", INS_SMLSD, (0,4,2,1), 0),\n- binary(\"011100000111\"): (\"smlsdx\", INS_SMLSDX, (0,4,2,1), 0),\n- binary(\"011101000001\"): (\"smlald\", INS_SMLALD, (1,0,4,2), 0),\n- binary(\"011101000011\"): (\"smlaldx\",INS_SMLALDX, (1,0,4,2), 0),\n- binary(\"011101000101\"): (\"smlsld\", INS_SMLSLD, (1,0,4,2), 0),\n- binary(\"011101000111\"): (\"smlsldx\",INS_SMLSLDX, (1,0,4,2), 0),\n- binary(\"011101010001\"): (\"smmla\", INS_SMMLA, (0,4,2,1), 0),\n- binary(\"011101010011\"): (\"smmlar\", INS_SMMLAR, (0,4,2,1), 0),\n- binary(\"011101011101\"): (\"smmls\", INS_SMMLS, (0,4,2,1), 0),\n- binary(\"011101011111\"): (\"smmlsr\", INS_SMMLSR, (0,4,2,1), 0),\n+ 0b011100000001: (\"smuad\", INS_SMUAD, (0, 4, 2), 0),\n+ 0b011100000011: (\"smuadx\", INS_SMUADX, (0, 4, 2), 0),\n+ 0b011100000101: (\"smusd\", INS_SMUSD, (0, 4, 2), 0),\n+ 0b011100000111: (\"smusdx\", INS_SMUSDX, (0, 4, 2), 0),\n+ 0b011100000001: (\"smlad\", INS_SMLAD, (0, 4, 2, 1), 0),\n+ 0b011100000011: (\"smladx\", INS_SMLADX, (0, 4, 2, 1), 0),\n+ 0b011100000101: (\"smlsd\", INS_SMLSD, (0, 4, 2, 1), 0),\n+ 0b011100000111: (\"smlsdx\", INS_SMLSDX, (0, 4, 2, 1), 0),\n+ 0b011101000001: (\"smlald\", INS_SMLALD, (1, 0, 4, 2), 0),\n+ 0b011101000011: (\"smlaldx\",INS_SMLALDX, (1, 0, 4, 2), 0),\n+ 0b011101000101: (\"smlsld\", INS_SMLSLD, (1, 0, 4, 2), 0),\n+ 0b011101000111: (\"smlsldx\",INS_SMLSLDX, (1, 0, 4, 2), 0),\n+ 0b011101010001: (\"smmla\", INS_SMMLA, (0, 4, 2, 1), 0),\n+ 0b011101010011: (\"smmlar\", INS_SMMLAR, (0, 4, 2, 1), 0),\n+ 0b011101011101: (\"smmls\", INS_SMMLS, (0, 4, 2, 1), 0),\n+ 0b011101011111: (\"smmlsr\", INS_SMMLSR, (0, 4, 2, 1), 0),\n#note for next two must check that Ra = 1111 otherwise is smmla\n#hard coding values until find better solution\n- #binary(\"011101010001\"): (\"smmul\", (0,4,2), 0),\n- #binary(\"011101010011\"): (\"smmulr\", (0,4,2), 0),\n+ #0b011101010001: (\"smmul\", (0,4,2), 0),\n+ #0b011101010011: (\"smmulr\", (0,4,2), 0),\n}\ndef sh_lsl(num, shval, size=4):\n@@ -689,12 +680,12 @@ multfail = (None, None, None, None)\niencmul_r15_codes = {\n# Basic multiplication opcodes\n- binary(\"011101010001\"): (\"smmul\", INS_SMMUL, (0,4,2), 0),\n- binary(\"011101010011\"): (\"smmulr\", INS_SMMULR, (0,4,2), 0),\n- binary(\"011100000001\"): (\"smuad\", INS_SMUAD, (0,4,2), 0),\n- binary(\"011100000011\"): (\"smuadx\", INS_SMUADX, (0,4,2), 0),\n- binary(\"011100000101\"): (\"smusd\", INS_SMUSD, (0,4,2), 0),\n- binary(\"011100000111\"): (\"smusdx\", INS_SMUSDX, (0,4,2), 0),\n+ 0b011101010001: (\"smmul\", INS_SMMUL, (0,4,2), 0),\n+ 0b011101010011: (\"smmulr\", INS_SMMULR, (0,4,2), 0),\n+ 0b011100000001: (\"smuad\", INS_SMUAD, (0,4,2), 0),\n+ 0b011100000011: (\"smuadx\", INS_SMUADX, (0,4,2), 0),\n+ 0b011100000101: (\"smusd\", INS_SMUSD, (0,4,2), 0),\n+ 0b011100000111: (\"smusdx\", INS_SMUSDX, (0,4,2), 0),\n}\ndef p_mult(opval, va):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup per @rakuyo
|
718,770 |
22.03.2020 23:10:57
| 14,400 |
c5766cdc913216e245df8310bbc3926832d89b9e
|
cleanup (some per
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -489,12 +489,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nnewcarry = (ures != result)\noverflow = e_bits.signed(result, tsize) != sres\n- #print \"=====================\"\n- #print hex(udst), hex(usrc), hex(ures), hex(result)\n- #print hex(sdst), hex(ssrc), hex(sres)\n- #print e_bits.is_signed(result, tsize), not result, newcarry, overflow\n- #print \"ures:\", ures, hex(ures), \" sres:\", sres, hex(sres), \" result:\", result, hex(result), \" signed(result):\", e_bits.signed(result, 4), hex(e_bits.signed(result, 4)), \" C/V:\",newcarry, overflow\n-\nif Sflag:\ncurmode = self.getProcMode()\nif rd == 15:\n@@ -1578,7 +1572,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nSflag = 1\nmask = e_bits.u_maxes[dsize]\n- #print 'cmp', hex(src1), hex(src2)\nres2 = self.AddWithCarry(src1, mask^src2, 1, Sflag, rd=reg, tsize=dsize)\ndef i_cmn(self, op):\n@@ -1589,7 +1582,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreg = op.opers[0].reg\nSflag = 1\n- #print 'cmn', hex(src1), hex(src2)\nres2 = self.AddWithCarry(src1, src2, carry=0, Sflag=Sflag, rd=reg, tsize=dsize)\ni_cmps = i_cmp\n@@ -1841,49 +1833,29 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setOperValue(op, 0, result)\ndef i_tbb(self, op):\n- # TBB and TBH both come here.\n- ### DEBUGGING\n- #raw_input(\"ArmEmulator: TBB\")\n+ '''\n+ table branch (byte) and table branch (halfword)\n+ TBB and TBH both come here.\n+ '''\ntsize = op.opers[0].tsize\ntbl = []\n- '''\n- base = op.opers[0].getOperValue(op, self)\n- val0 = self.readMemValue(base, 4)\n- if val0 > 0x100 + base:\n- print \"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\"\n-\n- va = base\n- while va < val0:\n- tbl.append(self.readMemValue(va, 4))\n- va += tsize\n- print \"tbb: \\n\\t\" + '\\n'.join([hex(x) for x in tbl])\n-\n- ###\n- jmptblval = self.getOperAddr(op, 0)\n- jmptbltgt = self.getOperValue(op, 0) + base\n- print \"0x%x: 0x%r\\njmptblval: 0x%x\\njmptbltgt: 0x%x\" % (op.va, op, jmptblval, jmptbltgt)\n- raw_input(\"PRESS ENTER TO CONTINUE\")\n- return jmptbltgt\n- '''\n- emu = self\nbasereg = op.opers[0].base_reg\nif basereg != REG_PC:\n- base = emu.getRegister(basereg)\n+ base = self.getRegister(basereg)\nelse:\nbase = op.opers[0].va\nlogger.debug(\"TB base = 0%x\", base)\n- #base = op.opers[0].getOperValue(op, emu)\nlogger.debug(\"base: 0x%x\" % base)\n- val0 = emu.readMemValue(base, tsize)\n+ val0 = self.readMemValue(base, tsize)\nif val0 > 0x200 + base:\nlogger.warn(\"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\")\nva = base\nwhile va < base + val0:\n- nexttgt = emu.readMemValue(va, tsize) * 2\n+ nexttgt = self.readMemValue(va, tsize) * 2\nlogger.debug(\"0x%x: -> 0x%x\", va, nexttgt + base)\nif nexttgt == 0:\nlogger.warn(\"Terminating TB at 0-offset\")\n@@ -1893,7 +1865,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nlogger.warn(\"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\", nexttgt)\nbreak\n- loc = emu.vw.getLocation(va)\n+ loc = self.vw.getLocation(va)\nif loc is not None:\nlogger.warn(\"Terminating TB at Location/Reference\")\nlogger.warn(\"%x, %d, %x, %r\", loc)\n@@ -1907,15 +1879,14 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n###\n# for workspace emulation analysis, let's check the index register for sanity.\nidxreg = op.opers[0].offset_reg\n- idx = emu.getRegister(idxreg)\n+ idx = self.getRegister(idxreg)\nif idx > 0x40000000:\n- emu.setRegister(idxreg, 0) # args handed in can be replaced with index 0\n+ self.setRegister(idxreg, 0) # args handed in can be replaced with index 0\njmptblbase = op.opers[0]._getOperBase(emu)\n- jmptblval = emu.getOperAddr(op, 0)\n- jmptbltgt = (emu.getOperValue(op, 0) * 2) + base\n+ jmptblval = self.getOperAddr(op, 0)\n+ jmptbltgt = (self.getOperValue(op, 0) * 2) + base\nlogger.debug(\"0x%x: 0x%r\\njmptblbase: 0x%x\\njmptblval: 0x%x\\njmptbltgt: 0x%x\", op.va, op, jmptblbase, jmptblval, jmptbltgt)\n- #raw_input(\"PRESS ENTER TO CONTINUE\")\nreturn jmptbltgt\ni_tbh = i_tbb\n"
},
{
"change_type": "DELETE",
"old_path": "vivisect/analysis/arm/elfplt.py",
"new_path": null,
"diff": "-\"\"\"\n-If a \"function\" is in the plt it's a wrapper for something in the GOT.\n-Make that apparent.\n-\"\"\"\n-\n-import envi\n-import vivisect\n-\n-import logging\n-logger = logging.getLogger(__name__)\n-\n-def analyze(vw):\n- \"\"\"\n- Do simple linear disassembly of the .plt section if present.\n- \"\"\"\n- for sva,ssize,sname,sfname in vw.getSegments():\n- if sname != \".plt\":\n- continue\n- nextva = sva + ssize\n- while sva < nextva:\n- vw.makeCode(sva)\n- ltup = vw.getLocation(sva)\n- sva += ltup[vivisect.L_SIZE]\n-\n-\n-MAX_INSTR_COUNT = 3\n-\n-def analyzeFunction(vw, funcva):\n- '''\n- Function Analysis Module. This gets run on all functions, so we need to identify that we're\n- in a PLT quickly.\n-\n- Emulates the first few instructions of each PLT function to determine the correct offset\n- into the Global Offset Table. Then tags names, etc...\n- '''\n- seg = vw.getSegment(funcva)\n- if seg == None:\n- return\n-\n- segva, segsize, segname, segfname = seg\n-\n- if segname not in (\".plt\", \".plt.got\"):\n- return\n-\n-\n- emu = vw.getEmulator()\n- emu.setProgramCounter(funcva)\n- offset = 0\n- branch = False\n- for cnt in range(MAX_INSTR_COUNT):\n- op = emu.parseOpcode(funcva + offset)\n- if op.iflags & envi.IF_BRANCH == 0:\n- emu.executeOpcode(op)\n- offset += len(op)\n- continue\n- branch = True\n- break\n-\n- if not branch:\n- return\n-\n- loctup = None\n- oper1 = op.opers[1]\n- opval = oper1.getOperAddr(op, emu=emu)\n- loctup = vw.getLocation(opval)\n-\n- if loctup == None:\n- return\n-\n- if loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT:\n- logger.debug(\"0x%x: \" % funcva, loctup[vivisect.L_LTYPE], ' != ', vivisect.LOC_IMPORT)\n-\n- gotname = vw.getName(opval)\n- tinfo = gotname\n- #vw.makeName(funcva, \"plt_%s\" % fname, filelocal=True)\n- vw.makeFunctionThunk(funcva, tinfo)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "import sys\nimport envi\n-import vivisect\nimport vivisect.impemu.monitor as viv_monitor\nimport logging\n+from vivisect import reprPointer\n+from vivisect.const import REF_DATA\nfrom envi.archs.arm.regs import PSR_T_bit\n-from vivisect import LOC_STRING, LOC_UNI, REF_DATA\nlogger = logging.getLogger(__name__)\nMAX_INIT_OPCODES = 30\n-def reprPointer(vw, va):\n- \"\"\"\n- Do your best to create a humon readable name for the\n- value of this pointer.\n- \"\"\"\n- if va == 0:\n- return \"NULL\"\n-\n- loc = vw.getLocation(va)\n- if loc != None:\n- locva, locsz, lt, ltinfo = loc\n- if lt in (LOC_STRING, LOC_UNI):\n- return vw.reprVa(locva)\n-\n- mbase,msize,mperm,mfile = vw.memobj.getMemoryMap(va)\n- ret = mfile\n- sym = vw.getName(va)\n- if sym != None:\n- ret = sym\n- return ret\nclass AnalysisMonitor(viv_monitor.AnalysisMonitor):\n@@ -39,24 +19,19 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nself.reg = vw.getFunctionMeta(fva, 'PIE_reg')\nself.tracker = {}\n- def prehook(self, emu, op, starteip):\n- viv_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n-\ndef posthook(self, emu, op, starteip):\nviv_monitor.AnalysisMonitor.posthook(self, emu, op, starteip)\nif len(op.opers) > 1:\n- # TODO: future: make this getRegister() for the registers... look for .GOT\noper = op.opers[1]\nif (hasattr(oper, 'reg') and oper.reg == self.reg) \\\nor (hasattr(oper, 'base_reg') and oper.base_reg == self.reg):\n# second operand has the register we're interested in for this function\ntgt = op.getOperValue(0, emu)\n- if tgt == None:\n- logger.warn(\"0x%x: %s tgt == None!\", op.va, op)\n+ if tgt is None:\n+ logger.warn(\"0x%x: %s tgt is None!\", op.va, op)\nreturn\nself.tracker[op.va] = tgt\n- #logger.debug(\"%x %s\", op.va, self.vw.reprVa(tgt))\ndef analyzeFunction(vw, fva):\n@@ -78,7 +53,7 @@ def analyzeFunction(vw, fva):\nbreak\n# if we don't have a segment named \".got\" we fail.\n- if got == None:\n+ if got is None:\nreturn\n# roll through the first few opcodes looking for one to load a register with .got's address\n@@ -111,12 +86,12 @@ def analyzeFunction(vw, fva):\nreg = op.opers[0].reg\nvw.setVaSetRow('thunk_reg', (fva, reg))\n- if vw.getFunctionMeta(fva, 'PIE_reg') == None:\n+ if vw.getFunctionMeta(fva, 'PIE_reg') is None:\nvw.setFunctionMeta(fva, 'PIE_reg', reg)\nvw.setComment(op.va, 'Position Indendent Code Register Set: %s' % \\\nvw.arch._arch_reg.getRegisterName(reg))\n- if vw.getMeta('PIE_GOT') == None:\n+ if vw.getMeta('PIE_GOT') is None:\nvw.setMeta('PIE_GOT', got)\nbreak\n@@ -145,7 +120,7 @@ def analyzeFunction(vw, fva):\nitems.sort()\nfor va, tgt in items:\n# if we already have xrefs, don't make more...\n- if vw.getLocation(tgt) == None:\n+ if vw.getLocation(tgt) is None:\ntry:\nvw.followPointer(tgt)\nexcept envi.SegmentationViolation:\n@@ -168,7 +143,7 @@ def analyzeFunction(vw, fva):\n# set comment. if existing comment, by default, don't... otherwise prepend the info before the existing comment\ncurcmt = vw.getComment(va)\ncmt = \"0x%x: %s\" % (tgt, reprPointer(vw, tgt))\n- if curcmt == None or not len(curcmt):\n+ if curcmt is None or not len(curcmt):\nvw.setComment(va, cmt)\nelif not cmt in curcmt:\ncmt = \"0x%x: %s ;\\n %s\" % (tgt, reprPointer(vw, tgt), curcmt)\n@@ -188,7 +163,7 @@ def analyze(vw):\nexcept:\nlogger.exception('thunk_reg analysis error:')\n-if globals().get('vw') != None:\n+if globals().get('vw') is not None:\nif len(argv) > 1:\nva = vw.parseExpression(argv[1])\nlogger.warn(\"analyzing workspace function %x for thunk_reg\", va)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup (some per @rakuyo)
|
718,765 |
23.03.2020 09:59:18
| 14,400 |
ac82159d07132ba2b8d1a8e5c8a55f985800fc7e
|
More intel coverage
More coverage of various addrmeth's in amd64 and fixing up some sizing issues.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/disasm.py",
"new_path": "envi/archs/amd64/disasm.py",
"diff": "@@ -12,7 +12,8 @@ from envi.archs.i386.disasm import iflag_lookup, operand_range, priv_lookup, \\\nMANDATORY_PREFIXES, PREFIX_REP_MASK\nfrom envi.archs.amd64.regs import *\n-from envi.archs.i386.opconst import OP_REG32AUTO, OP_MEM32AUTO, INS_VEXREQ, OP_NOVEXL\n+from envi.archs.i386.opconst import OP_REG32AUTO, OP_MEM32AUTO, OP_MEM16AUTO, \\\n+ INS_VEXREQ, OP_NOVEXL\nall_tables = opcode86.tables86\n# Pre generate these for fast lookup. Because our REX prefixes have the same relative\n@@ -490,16 +491,18 @@ class Amd64Disasm(e_i386.i386Disasm):\n# If we are a sign extended immediate and not the same as the other operand,\n# do the sign extension during disassembly so nothing else has to worry about it..\nif len(operands) and tsize != operands[-1].tsize:\n- # Check if we are an explicitly signed operand *or* REX.W\n- if operflags & opcode86.OP_SIGNED and prefixes & PREFIX_REX_W:\n+ if operflags & opcode86.OP_SIGNED:\notsize = operands[-1].tsize\noper.imm = e_bits.sign_extend(oper.imm, oper.tsize, otsize)\noper.tsize = otsize\nelse:\nosize, oper = ameth(bytez, offset, tsize, prefixes, operflags)\n- if getattr(oper, \"_is_deref\", False) and operflags & OP_MEM32AUTO:\n+ if getattr(oper, \"_is_deref\", False):\n+ if operflags & OP_MEM32AUTO:\noper.tsize = 4\n+ elif operflags & OP_MEM16AUTO:\n+ oper.tsize = 2\nexcept struct.error:\n# Catch struct unpack errors due to insufficient data length\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "@@ -238,9 +238,9 @@ tbl32_Main = [\n( 0, INS_MOV, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n( 0, INS_MOV, ADDRMETH_G | OPTYPE_b | OP_W, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n( 0, INS_MOV, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n-( 0, INS_MOV, ADDRMETH_E | OPTYPE_w | OP_W, ADDRMETH_S | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+( 0, INS_MOV, ADDRMETH_E | OPTYPE_v | OP_W | OP_MEM16AUTO, ADDRMETH_S | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n( 0, INS_LEA, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, \"lea\", 0, 0, 0),\n-( 0, INS_MOV, ADDRMETH_S | OPTYPE_w | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+( 0, INS_MOV, ADDRMETH_S | OPTYPE_w | OP_W, ADDRMETH_E | OPTYPE_v | OP_R | OP_MEM16AUTO, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n( 0, INS_POP, OP_64AUTO | ADDRMETH_M | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386, \"pop\", 0, 0, 0),\n# 0x90\n(0, INS_NOP, 0, 0, 0, cpu_80386, \"nop\", 0, 0, 0),\n@@ -407,10 +407,10 @@ tbl32_0F = [\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n( 0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n# 0f20\n-( 0, INS_MOV, ADDRMETH_R | OPTYPE_d | OP_W, ADDRMETH_C | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n-( 0, INS_MOV, ADDRMETH_R | OPTYPE_d | OP_W, ADDRMETH_D | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n-( 0, INS_MOV, ADDRMETH_C | OPTYPE_d | OP_W, ADDRMETH_R | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n-( 0, INS_MOV, ADDRMETH_D | OPTYPE_d | OP_W, ADDRMETH_R | OPTYPE_d | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+( 0, INS_MOV, ADDRMETH_R | OPTYPE_q | OP_W, ADDRMETH_C | OPTYPE_q | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+( 0, INS_MOV, ADDRMETH_R | OPTYPE_q | OP_W, ADDRMETH_D | OPTYPE_q | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+( 0, INS_MOV, ADDRMETH_C | OPTYPE_q | OP_W, ADDRMETH_R | OPTYPE_q | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+( 0, INS_MOV, ADDRMETH_D | OPTYPE_q | OP_W, ADDRMETH_R | OPTYPE_q | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/disasm.py",
"new_path": "envi/archs/i386/disasm.py",
"diff": "@@ -8,12 +8,13 @@ import struct\nimport envi\nimport envi.bits as e_bits\n-import opcode86\n-all_tables = opcode86.tables86\n-\n# Grab our register enums etc...\nfrom envi.const import *\nfrom envi.archs.i386.regs import *\n+from envi.archs.i386.opconst import OP_MEM32AUTO, OP_MEM16AUTO\n+\n+import opcode86\n+all_tables = opcode86.tables86\n# Our instruction prefix masks\n# NOTE: table 3-4 (section 3.6) of intel 1 shows how REX/OP_SIZE\n@@ -969,6 +970,11 @@ class i386Disasm:\nelse:\nosize, oper = ameth(bytez, offset, tsize, all_prefixes, operflags)\n+ if getattr(oper, \"_is_deref\", False):\n+ if operflags & OP_MEM32AUTO:\n+ oper.tsize = 4\n+ elif operflags & OP_MEM16AUTO:\n+ oper.tsize = 2\nexcept struct.error as e:\n# Catch struct unpack errors due to insufficient data length\n@@ -1005,7 +1011,8 @@ class i386Disasm:\nif operflags & opcode86.OP_REG:\nif prefixes & PREFIX_OP_SIZE:\noperval |= RMETA_LOW16\n- return i386RegOper(operval, tsize)\n+ width = self._dis_regctx.getRegisterWidth(operval) / 8\n+ return i386RegOper(operval, width)\nelif operflags & opcode86.OP_IMM:\nreturn i386ImmOper(operval, tsize)\nraise Exception(\"Unknown ameth_0! operflags: 0x%.8x\" % operflags)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opcode86.py",
"new_path": "envi/archs/i386/opcode86.py",
"diff": "@@ -154,9 +154,9 @@ tbl32_Main = [\n(0, INS_MOV, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n(0, INS_MOV, ADDRMETH_G | OPTYPE_b | OP_W, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n(0, INS_MOV, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n- (0, INS_MOV, ADDRMETH_E | OPTYPE_w | OP_W, ADDRMETH_S | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+ (0, INS_MOV, ADDRMETH_E | OPTYPE_v | OP_W | OP_MEM16AUTO, ADDRMETH_S | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n(0, INS_LEA, ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_M | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, \"lea\", 0, 0, 0),\n- (0, INS_MOV, ADDRMETH_S | OPTYPE_w | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n+ (0, INS_MOV, ADDRMETH_S | OPTYPE_w | OP_W, ADDRMETH_E | OPTYPE_v | OP_R | OP_MEM16AUTO, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n(0, INS_POP, ADDRMETH_M | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386, \"pop\", 0, 0, 0),\n# 0x90\n(0, INS_NOP, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opconst.py",
"new_path": "envi/archs/i386/opconst.py",
"diff": "@@ -213,7 +213,8 @@ OP_X = 0x004\nOP_64AUTO = 0x008 # operand is in 64bit mode with amd64!\nOP_REG32AUTO = 0x010 # force only *register* to be 32 bit.\nOP_MEM32AUTO = 0x020 # force only *memory* to be 32 bit.\n-OP_NOVEXL = 0x040 # don't apply VEX.L here (even though it's set). TLDR: always 128/xmm reg\n+OP_MEM16AUTO = 0x040 # force only *memory* to be 32 bit.\n+OP_NOVEXL = 0x080 # don't apply VEX.L here (even though it's set). TLDR: always 128/xmm reg\nOP_UNK = 0x000\nOP_REG = 0x100\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_amd64.py",
"new_path": "envi/tests/test_arch_amd64.py",
"diff": "@@ -407,6 +407,32 @@ amd64MultiByteOpcodes = [\n('MAXPD 2', '66450f5f85c4000000', 'maxpd xmm8,oword [r13 + 196]', 'maxpd xmm8,oword [r13 + 196]'),\n('MAXPD 3', '66460f5f04cdc4000000', 'maxpd xmm8,oword [0x000000c4 + r9 * 8]', 'maxpd xmm8,oword [0x000000c4 + r9 * 8]'),\n('MAXPD 4', '66440f5fc1', 'maxpd xmm8,xmm1', 'maxpd xmm8,xmm1'),\n+ ('MOV AMETH_C', '0f20d0', 'mov rax,ctrl2', 'mov rax,ctrl2'),\n+ ('MOV AMETH_C 2', '0f20f1', 'mov rcx,ctrl6', 'mov rcx,ctrl6'),\n+ ('MOV AMETH_C 3', '0f22e2', 'mov ctrl4,rdx', 'mov ctrl4,rdx'),\n+ ('MOV AMETH_C 4', '0f22f8', 'mov ctrl7,rax', 'mov ctrl7,rax'),\n+ ('MOV AMETH_C REX', '440f20c2', 'mov rdx,ctrl8', 'mov rdx,ctrl8'),\n+ ('MOV AMETH_C REX 2', '450f22c1', 'mov ctrl8,r9', 'mov ctrl8,r9'),\n+\n+ ('MOV AMETH_D', '0f21c0', 'mov rax,debug0', 'mov rax,debug0'), # ADDRMETH_D\n+ ('MOV AMETH_D 2', '0f21f9', 'mov rcx,debug7', 'mov rcx,debug7'),\n+ ('MOV AMETH_D 3', '0f23e1', 'mov debug4,rcx', 'mov debug4,rcx'),\n+ ('MOV AMETH_D REX', '410f23c4', 'mov debug0,r12', 'mov debug0,r12'),\n+\n+ ('LEA', '8d4a0c', 'lea ecx,dword [rdx + 12]', 'lea ecx,dword [rdx + 12]'),\n+ ('LEA 2', '488d400c', 'lea rax,qword [rax + 12]', 'lea rax,qword [rax + 12]'),\n+ ('XOR', '4981F4CE260000', 'xor r12,0x000026ce', 'xor r12,0x000026ce'),\n+ ('XOR SIGNED', '4881F19B83FFFF', 'xor rcx,0xffffffffffff839b', 'xor rcx,0xffffffffffff839b'),\n+ ('SIGNED', '83C0F9', 'add eax,0xfffffff9', 'add eax,0xfffffff9'),\n+ ('UNSIGNED', '05f9000000', 'add eax,249', 'add eax,249'),\n+\n+ ('MOV SEGREG 2', '8ce0', 'mov eax,fs', 'mov eax,fs'),\n+ ('MOV SEGREG 3', '8ec6', 'mov es,esi', 'mov es,esi'),\n+ ('MOV SEGREG 4', '488ce7', 'mov rdi,fs', 'mov rdi,fs'),\n+ ('MOV SEGREG 5', '488ed6', 'mov ss,rsi', 'mov ss,rsi'),\n+ ('MOV SEGREG 6', '8E142541414141', 'mov ss,word [0x41414141]', 'mov ss,word [0x41414141]'),\n+ ('MOV SEGREG 7', '8C042541414141', 'mov word [0x41414141],es', 'mov word [0x41414141],es'),\n+\n('WAIT', '9b', 'wait ', 'wait '), # TODO: this needs to be able to change the opcode too\n]\n@@ -1081,7 +1107,7 @@ class Amd64InstructionSet(unittest.TestCase):\nopbytez = '0440'\noprepr = 'add al,64'\nopcheck = {'iflags': 131072, 'prefixes': 0, 'mnem': 'add', 'opcode': 8193, 'size': 2}\n- opercheck = ( {'tsize': 4, 'reg': 524288}, {'tsize': 1, 'imm': 64} )\n+ opercheck = ( {'tsize': 1, 'reg': 524288}, {'tsize': 1, 'imm': 64} )\nself.checkOpcode( opbytez, 0x4000, oprepr, opcheck, opercheck, oprepr )\nopbytez = '0218'\n@@ -1090,12 +1116,6 @@ class Amd64InstructionSet(unittest.TestCase):\nopercheck = ( {'tsize': 1, 'reg': 524291}, {'disp': 0, 'tsize': 1, '_is_deref': True, 'reg': 0} )\nself.checkOpcode( opbytez, 0x4000, oprepr, opcheck, opercheck, oprepr )\n- opbytez = '0f2018'\n- oprepr = 'mov dword [rax],ctrl3'\n- opcheck = {'iflags': 131072, 'va': 16384, 'repr': None, 'prefixes': 0, 'mnem': 'mov', 'opcode': 24577, 'size': 3}\n- opercheck = ( {'disp': 0, 'tsize': 4, '_is_deref': True, 'reg': 0}, {'tsize': 4, 'reg': 59} )\n- self.checkOpcode( opbytez, 0x4000, oprepr, opcheck, opercheck, oprepr )\n-\nfor x in range(0xb0, 0xb8):\nbytez = '41%.2xAAAAAAAA' % x\nop = self._arch.archParseOpcode((bytez).decode('hex'),0,0x1000)\n@@ -1233,13 +1253,13 @@ class Amd64InstructionSet(unittest.TestCase):\nopbytez = '6e'\noprepr = 'outsb dx,byte [rsi]'\nopcheck = {'iflags': 131074, 'va': 16384, 'repr': None, 'prefixes': 0, 'mnem': 'outsb', 'opcode': 57347, 'size': 1}\n- opercheck = [{'tsize': 4, 'reg': 1048578}, {'disp': 0, 'tsize': 1, '_is_deref': True, 'reg': 6}]\n+ opercheck = [{'tsize': 2, 'reg': 1048578}, {'disp': 0, 'tsize': 1, '_is_deref': True, 'reg': 6}]\nself.checkOpcode( opbytez, 0x4000, oprepr, opcheck, opercheck, oprepr )\nopbytez = '6d'\noprepr = 'insd dword [rsi],dx'\nopcheck = {'iflags': 131074, 'va': 16384, 'repr': None, 'prefixes': 0, 'mnem': 'insd', 'opcode': 57346, 'size': 1}\n- opercheck = [{'disp': 0, 'tsize': 4, '_is_deref': True, 'reg': 6}, {'tsize': 4, 'reg': 1048578}]\n+ opercheck = [{'disp': 0, 'tsize': 4, '_is_deref': True, 'reg': 6}, {'tsize': 2, 'reg': 1048578}]\nself.checkOpcode( opbytez, 0x4000, oprepr, opcheck, opercheck, oprepr )\ndef test_envi_amd64_disasm_ImmMem_Operands(self):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_i386.py",
"new_path": "envi/tests/test_arch_i386.py",
"diff": "@@ -179,6 +179,28 @@ i386MultiByteOpcodes = [\n('MOVNTDQ', '660FE73D78563412', 0x40, 'movntdq oword [0x12345678],xmm7', 'movntdq oword [0x12345678],xmm7'),\n('PADDD', '660FFECE', 0x40, 'paddd xmm1,xmm6', 'paddd xmm1,xmm6'),\n+ ('MOV AMETH_C', '0f20d0', 0x40, 'mov eax,ctrl2', 'mov eax,ctrl2'),\n+ ('MOV AMETH_C 2', '0f20f1', 0x40, 'mov ecx,ctrl6', 'mov ecx,ctrl6'),\n+ ('MOV AMETH_C 3', '0f22e2', 0x40, 'mov ctrl4,edx', 'mov ctrl4,edx'),\n+ ('MOV AMETH_C 4', '0f22f8', 0x40, 'mov ctrl7,eax', 'mov ctrl7,eax'),\n+\n+ ('MOV AMETH_D', '0f21c0', 0x40, 'mov eax,debug0', 'mov eax,debug0'),\n+ ('MOV AMETH_D 2', '0f21f9', 0x40, 'mov ecx,debug7', 'mov ecx,debug7'),\n+ ('MOV AMETH_D 3', '0f23e1', 0x40, 'mov debug4,ecx', 'mov debug4,ecx'),\n+\n+ ('MOV SEGREG', '64a130000000', 0x40, 'fs: mov eax,dword [0x00000030]', 'fs: mov eax,dword [0x00000030]'),\n+ ('MOV SEGREG 2', '8ce0', 0x40, 'mov eax,fs', 'mov eax,fs'),\n+ ('MOV SEGREG 3', '8ec6', 0x40, 'mov es,esi', 'mov es,esi'),\n+ ('MOV SEGREG 4', '668ec6', 0x40, 'mov es,si', 'mov es,si'),\n+ ('MOV SEGREG 6', '8E142541414141', 0x40, 'mov ss,word [0x41414141]', 'mov ss,word [0x41414141]'),\n+ ('MOV SEGREG 7', '8C042541414141', 0x40, 'mov word [0x41414141],es', 'mov word [0x41414141],es'),\n+\n+ ('LEA', '8d5a0c', 0x40, 'lea ebx,dword [edx + 12]', 'lea ebx,dword [edx + 12]'),\n+ ('SIGNED', '83C0F9', 0x40, 'add eax,0xfffffff9', 'add eax,0xfffffff9'),\n+ ('MAXPD', '660F5F64C020', 0x40, 'maxpd xmm4,oword [eax + eax * 8 + 32]', 'maxpd xmm4,oword [eax + eax * 8 + 32]'),\n+ ('MAXPD 2', '660f5fa490d0a80000', 0x40, 'maxpd xmm4,oword [eax + edx * 4 + 43216]', 'maxpd xmm4,oword [eax + edx * 4 + 43216]'),\n+ # ('rm4mod2', '', 0x40, '', ''),\n+\n# AES-NI feature set\n('AESENC', '660F38DCEA', 0x40, 'aesenc xmm5,xmm2', 'aesenc xmm5,xmm2'),\n('AESENC (MEM)', '660f38DC3A', 0x40, 'aesenc xmm7,oword [edx]', 'aesenc xmm7,oword [edx]'),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
More intel coverage (#272)
More coverage of various addrmeth's in amd64 and fixing up some sizing issues.
|
718,770 |
23.03.2020 14:52:50
| 14,400 |
b304e8a99e3dc1992e020f243ee53ce13b2a36a1
|
reprPointer work (discussion with and some flake8 stuff.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -7,12 +7,6 @@ from envi import InvalidInstruction\nfrom envi.archs.arm.disasm import *\narmd = ArmDisasm()\n-#thumb_32 = [\n- #binary('11101'),\n- #binary('11110'),\n- #binary('11111'),\n-#]\n-\n#FIXME: check to make sure ldrb/ldrh are handled consistently, wrt: IF_B and IF_H. emulation would like all the same.\n@@ -36,7 +30,6 @@ class simpleops:\ndef __call__(self, va, value):\nret = []\nfor otype, shval, mask in self.operdef:\n- #oval = shmaskval(value, shval, mask)\noper = OperType[otype]((value >> shval) & mask, va=va)\nret.append( oper )\nreturn COND_AL, (ret), None\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/cli.py",
"new_path": "envi/cli.py",
"diff": "@@ -718,11 +718,16 @@ class EnviCli(Cmd):\ntry:\nmbase, msize, mperm, mfile = self.memobj.getMemoryMap(va)\n+ if va == mbase:\nret = mfile\n+ else:\n+ ret = mfile + \" + 0x%x\" % (va - mbase)\n+\nsym = self.symobj.getSymByAddr(va, exact=False)\n- if sym != None:\n- ret = \"%s + %d\" % (repr(sym),va-long(sym))\n- except:\n+ if sym is not None:\n+ ret = \"%s + 0x%x\" % (repr(sym), va-long(sym))\n+\n+ except Exception:\nret = hex(va)\nreturn ret\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -559,6 +559,34 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n\"\"\"\nself.chan_lookup.pop(chanid)\n+ def reprPointer(vw, va):\n+ \"\"\"\n+ Do your best to create a humon readable name for the\n+ value of this pointer.\n+\n+ note: This differs from parent function from envi.cli:\n+ * Locations database is checked\n+ * Strings are returned, not named (partially)\n+ * <function> + 0x<offset> is returned if inside a function\n+ * <filename> + 0x<offset> is returned instead of loc_#####\n+ \"\"\"\n+ if va == 0:\n+ return \"NULL\"\n+\n+ loc = vw.getLocation(va)\n+ if loc is not None:\n+ locva, locsz, lt, ltinfo = loc\n+ if lt in (LOC_STRING, LOC_UNI):\n+ return vw.reprVa(locva)\n+\n+ mbase, msize, mperm, mfile = vw.getMemoryMap(va)\n+ ret = mfile + \" + 0x%x\" % (va - mbase)\n+\n+ sym = vw.getName(va, smart=True)\n+ if sym is not None:\n+ ret = sym\n+ return ret\n+\ndef reprVa(self, va):\n\"\"\"\nA quick way for scripts to get a string for a given virtual address.\n@@ -2150,7 +2178,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nlocation.\n\"\"\"\nva = self.vaByName(name)\n- if va == None:\n+ if va is None:\nraise InvalidLocation(0, \"Unknown Name: %s\" % name)\nreturn self.getLocation(va)\n@@ -2170,23 +2198,30 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\n'''\nname = self.name_by_va.get(va)\n- if name != None or not smart:\n+ if name is not None or not smart:\nreturn name\n+ # TODO: by previous symbol?\n+\n+ # by function\nbaseva = self.getFunction(va)\nbasename = self.name_by_va.get(baseva, None)\n- if basename == None:\n+ # by filename\n+ if basename is None:\nbasename = self.getFileByVa(va)\n- if basename == None:\n+ if basename is None:\nreturn None\nbaseva = self.getFileMeta(basename, 'imagebase')\ndelta = va - baseva\n- pom = ('','+')[delta>=0]\n+ if delta:\n+ pom = ('', '+')[delta>0]\nname = \"%s%s%s\" % (basename, pom, hex(delta))\n+ else:\n+ name = basename\nreturn name\ndef makeName(self, va, name, filelocal=False, makeuniq=False):\n@@ -2703,11 +2738,11 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\ndef getSymByAddr(self, addr, exact=True):\nname = self.getName(addr)\n- if name == None:\n+ if name is None:\nif self.isValidPointer(addr):\nname = \"loc_%.8x\" % addr\n- if name != None:\n+ if name is not None:\n#FIXME fname\n#FIXME functions/segments/etc...\nreturn e_resolv.Symbol(name, addr, 0)\n@@ -2731,6 +2766,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nreturn self.symhints.get((va, idx), None)\n+\nclass VivFileSymbol(e_resolv.FileSymbol):\n# A namespace tracker thingie...\ndef __init__(self, vw, fname, base, size, width=4):\n@@ -2740,6 +2776,7 @@ class VivFileSymbol(e_resolv.FileSymbol):\ndef getSymByName(self, name):\nreturn self.vw.getSymByName(\"%s.%s\" % (self.name, name))\n+\ndef getVivPath(*pathents):\ndname = os.path.dirname(__file__)\ndname = os.path.abspath(dname)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -4,7 +4,6 @@ import vivisect.impemu.monitor as viv_monitor\nimport logging\n-from vivisect import reprPointer\nfrom vivisect.const import REF_DATA\nfrom envi.archs.arm.regs import PSR_T_bit\n@@ -142,11 +141,11 @@ def analyzeFunction(vw, fva):\n# set comment. if existing comment, by default, don't... otherwise prepend the info before the existing comment\ncurcmt = vw.getComment(va)\n- cmt = \"0x%x: %s\" % (tgt, reprPointer(vw, tgt))\n+ cmt = \"0x%x: %s\" % (tgt, vw.reprPointer(tgt))\nif curcmt is None or not len(curcmt):\nvw.setComment(va, cmt)\nelif not cmt in curcmt:\n- cmt = \"0x%x: %s ;\\n %s\" % (tgt, reprPointer(vw, tgt), curcmt)\n+ cmt = \"0x%x: %s ;\\n %s\" % (tgt, vw.reprPointer(tgt), curcmt)\nvw.setComment(va, cmt)\nlogger.debug(\"PIE XREF: %x %s\", va, cmt)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
reprPointer work (discussion with @rakuyo) and some flake8 stuff.
|
718,770 |
25.03.2020 15:36:23
| 14,400 |
ab23fe642f1af3d38c175ecda0b9383f7df568d2
|
cleanup and changed interrupt handling to use a dict instead of a list, enabling easier default handler configuration.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -162,7 +162,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# FIXME: this should be None's, and added in for each real coproc... but this will work for now.\nself.coprocs = [CoProcEmulator(x) for x in xrange(16)]\n- self.int_handlers = [self.default_int_handler for x in range(100)]\n+\n+ self.int_handlers = {}\nenvi.Emulator.__init__(self, ArmModule())\n@@ -562,10 +563,11 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn res\ndef interrupt(self, val):\n- if val >= len(self.int_handlers):\n- logger.critical(\"FIXME: Interrupt Handler %x is not handled\", val)\n+ if val not in self.int_handlers:\n+ pc = self.getProgramCounter()\n+ logger.critical(\"FIXME: Interrupt Handler %x is not handled (at va: 0x%x). Using default handler\", val, pc)\n- handler = self.int_handlers[val]\n+ handler = self.int_handlers.get(val, self.default_int_handler)\nhandler(val, self)\ndef default_int_handler(self, val, emu):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1404,7 +1404,7 @@ def tb_ldrex_32(va, val1, val2):\ntsize = [1, 2, 0, 8][op3&3]\noper0 = ArmRegOper(rt, va=va)\n- oper1 = ArmRegOffsetOper(rn, va=va, tsize=tsize)\n+ oper1 = ArmImmOffsetOper(rn, 0, va=va, tsize=tsize)\nopers = (oper0, oper1)\nelse: # tbb/tbh\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -550,9 +550,14 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nreturn fname\n+armemu = None\ndef applyRelocs(elf, vw, addbase=False, baseaddr=0):\n- # process relocations / strings (relocs use Dynamic Symbols)\n+ '''\n+ process relocations / strings (relocs use Dynamic Symbols)\n+ '''\n+ global armemu # certain ARM relocations allow instructions to determine the relocation\n+\narch = arch_names.get(elf.e_machine)\nrelocs = elf.getRelocs()\nlogger.debug(\"reloc len: %d\", len(relocs))\n@@ -614,6 +619,10 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nif arch in ('arm', 'thumb', 'thumb16'):\n+ # get an emulator spun up for handling of certain relocation types\n+ if armemu is None:\n+ armemu = vw.getEmulator()\n+\nif rtype == Elf.R_ARM_JUMP_SLOT:\nsymidx = r.getSymTabIndex()\nsym = elf.getDynSymbol(symidx)\n@@ -648,8 +657,12 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\n#quick check to make sure we don't provide this symbol\nif ptr:\nlogger.info('R_ARM_GLOB_DAT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\n+ if addbase:\nvw.addRelocation(rlva, vivisect.RTYPE_BASEPTR, ptr)\n+ else:\n+ vw.addRelocation(rlva, vivisect.RTYPE_BASERELOC, ptr)\npname = \"ptr_%s\" % name\n+\nif vw.vaByName(pname) is None:\nvw.makeName(rlva, pname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup and changed interrupt handling to use a dict instead of a list, enabling easier default handler configuration.
|
718,770 |
25.03.2020 15:38:22
| 14,400 |
8527916016147a8b4b2bdccf4ef691ee9523db76
|
added arm/elfplt analysis mod back into repo for now. improved it a bit... working toward improving elf/elfplt analysis mod to make this unnecessary. SAVEGAME
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": "vivisect/analysis/arm/elfplt.py",
"diff": "+\"\"\"\n+If a \"function\" is in the plt it's a wrapper for something in the GOT.\n+Make that apparent.\n+\"\"\"\n+\n+import envi\n+import vivisect\n+\n+import logging\n+logger = logging.getLogger(__name__)\n+\n+def analyze(vw):\n+ \"\"\"\n+ Do simple linear disassembly of the .plt section if present.\n+ \"\"\"\n+ return\n+ for sva,ssize,sname,sfname in vw.getSegments():\n+ if sname != \".plt\":\n+ continue\n+ nextva = sva + ssize\n+ while sva < nextva:\n+ vw.makeCode(sva)\n+ ltup = vw.getLocation(sva)\n+ sva += ltup[vivisect.L_SIZE]\n+\n+\n+MAX_INSTR_COUNT = 3\n+\n+def analyzeFunction(vw, funcva):\n+ '''\n+ Function Analysis Module. This gets run on all functions, so we need to identify that we're\n+ in a PLT quickly.\n+\n+ Emulates the first few instructions of each PLT function to determine the correct offset\n+ into the Global Offset Table. Then tags names, etc...\n+ '''\n+ seg = vw.getSegment(funcva)\n+ if seg == None:\n+ logger.debug(\"no segment for funcva 0x%x\", funcva)\n+ return\n+\n+ segva, segsize, segname, segfname = seg\n+\n+ if segname not in (\".plt\", \".plt.got\"):\n+ logger.debug(\"not in PLT segment for funcva 0x%x (%r)\", funcva, segname)\n+ return\n+\n+\n+ emu = vw.getEmulator()\n+ emu.setProgramCounter(funcva)\n+ offset = 0\n+ branch = False\n+ for cnt in range(MAX_INSTR_COUNT):\n+ op = emu.parseOpcode(funcva + offset)\n+ if op.iflags & envi.IF_BRANCH == 0:\n+ emu.executeOpcode(op)\n+ offset += len(op)\n+ continue\n+ branch = True\n+ break\n+\n+ if not branch:\n+ logger.debug(\"no branch found for funcva 0x%x (after %r instrs)\", funcva, cnt)\n+ return\n+\n+ loctup = None\n+ oper1 = op.opers[1]\n+ opval = oper1.getOperAddr(op, emu=emu)\n+ loctup = vw.getLocation(opval)\n+\n+ if loctup == None:\n+ logger.debug(\"no location found for funcva 0x%x (%r)\", funcva, oper1)\n+ return\n+\n+ if loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT:\n+ logger.debug(\"0x%x: %r != %r (LOC_IMPORT)\", funcva, loctup[vivisect.L_LTYPE], vivisect.LOC_IMPORT)\n+\n+ vw.addXref(op.va, opval, vivisect.REF_DATA)\n+ tva = vw.readMemoryPtr(opval)\n+ if vw.isValidPointer(tva):\n+ vw.addXref(op.va, tva, vivisect.REF_CODE)\n+\n+ gotname = vw.getName(opval)\n+ vw.makeFunctionThunk(funcva, gotname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
added arm/elfplt analysis mod back into repo for now. improved it a bit... working toward improving elf/elfplt analysis mod to make this unnecessary. SAVEGAME
|
718,770 |
27.03.2020 08:43:53
| 14,400 |
4bf9e123a09515f4de9c09cb6349cf8aa873834c
|
bugfix: Constant undefined in vcvt
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -138,6 +138,13 @@ MSB_FMT = [0, 'B', '>H', 0, '>I', 0, 0, 0, '>Q',]\nLSB_FMT_SIGNED = [0, 'b', '<h', 0, '<i', 0, 0, 0, '<q',]\nMSB_FMT_SIGNED = [0, 'b', '>h', 0, '>i', 0, 0, 0, '>q',]\n+# SIMD support\n+OP_F16 = 1\n+OP_F32 = 2\n+OP_F64 = 3\n+OP_S32 = 4\n+OP_U32 = 5\n+\nifs_first_F32 = (IFS_F32_S32 | IFS_F32_U32 | IFS_F32_F64 | IFS_F32_F16)\nifs_second_F32 = (IFS_S32_F32 | IFS_U32_F32 | IFS_F64_F32 | IFS_F16_F32)\nifs_first_S32 = (IFS_S32_F32 | IFS_S32_F64 | IFS_S32_F32)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: Constant undefined in vcvt
|
718,770 |
27.03.2020 08:44:47
| 14,400 |
d58bc773eee6534a8790458c9a815fbf197fb345
|
throw the emulator back into the getBranches() call to getOperValue()
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3929,7 +3929,7 @@ class ArmOpcode(envi.Opcode):\noper = self.opers[-1]\n# check for location being ODD\n- operval = oper.getOperValue(self)\n+ operval = oper.getOperValue(self, emu)\nif self.opcode in (INS_BLX, INS_BX):\nif operval != None and operval & 3:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
throw the emulator back into the getBranches() call to getOperValue()
|
718,770 |
27.03.2020 08:47:09
| 14,400 |
4796360e1ca7ec1ba917e9d12020c9dc73ea7a53
|
updates to the ELF parser (for ARM Relocs)
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -619,9 +619,43 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nif arch in ('arm', 'thumb', 'thumb16'):\n- # get an emulator spun up for handling of certain relocation types\n- if armemu is None:\n- armemu = vw.getEmulator()\n+ # ARM REL entries require an addend that could be stored as a\n+ # number or an instruction!\n+ import envi.archs.arm.const as eaac\n+ if r.vsHasField('addend'):\n+ # this is a RELA object, bringing its own addend field!\n+ addend = r.addend\n+ else:\n+ # otherwise, we have to check the stored value for number or instruction\n+ # if it's an instruction, we have to use the immediate value and then\n+ # figure out if it's negative based on the instruction!\n+ try:\n+ temp = vw.readMemoryPtr(rlva)\n+ if temp & 0xffffff00: # it's not just a little number\n+ op = vw.parseOpcode(rlva)\n+ for oper in op.opers:\n+ if hasattr(oper, 'val'):\n+ addend = oper.val\n+ break\n+\n+ elif hasattr(oper, 'offset'):\n+ addend = oper.offset\n+ break\n+\n+ lastoper = op.opers[-1]\n+ if op.mnem.startswith('sub') or \\\n+ op.mnem in ('ldr', 'str') and \\\n+ hasattr(lastoper, 'pubwl') and \\\n+ not (lastoper.pubwl & eaac.PUxWL_ADD):\n+ addend = -addend\n+ else:\n+ # just a small number\n+ addend = temp\n+ except Exception:\n+ logger.exception(\"ELF: Reloc Addend determination:\")\n+ addend = temp\n+\n+ logger.debug('addend: 0x%x', addend)\nif rtype == Elf.R_ARM_JUMP_SLOT:\nsymidx = r.getSymTabIndex()\n@@ -654,7 +688,13 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nsym = elf.getDynSymbol(symidx)\nptr = sym.st_value\n+ ###\n+ print \"----- %x %r %x\" % (symidx, sym, ptr)\n+ print r.tree()\n+ print sym.tree()\n+\n#quick check to make sure we don't provide this symbol\n+\nif ptr:\nlogger.info('R_ARM_GLOB_DAT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\nif addbase:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
updates to the ELF parser (for ARM Relocs)
|
718,770 |
30.03.2020 07:21:23
| 14,400 |
ecf5fdd15ad0d6443c77ccce1db370f799c734a9
|
elfplt savegame. still sorting out bugs, but example cmln is looking up.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -150,6 +150,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nself.addVaSet('DynamicBranches', (('va', VASET_ADDRESS), ('opcode', VASET_STRING), ('bflags', VASET_INTEGER)))\nself.addVaSet('SwitchCases', (('va', VASET_ADDRESS), ('setup_va', VASET_ADDRESS), ('Cases', VASET_INTEGER)))\nself.addVaSet('PointersFromFile', (('va', VASET_ADDRESS), ('target', VASET_ADDRESS), ('file', VASET_STRING), ('comment', VASET_STRING), ))\n+ self.addVaSet('FuncWrappers', (('va', VASET_ADDRESS), ('wrapped_va', VASET_ADDRESS),))\ndef verbprint(self, msg):\nif self.verbose:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -94,7 +94,7 @@ def addAnalysisModules(vw):\nelif arch in ('arm', 'thumb', 'thumb16'):\nvw.addVaSet('thunk_reg', ( ('fva', vivisect.VASET_ADDRESS), ('reg', vivisect.VASET_INTEGER), ))\nvw.addFuncAnalysisModule('vivisect.analysis.arm.thunk_reg')\n- vw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\n+ #vw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\nvw.addFuncAnalysisModule('vivisect.analysis.arm.renaming')\nvw.addAnalysisModule(\"vivisect.analysis.generic.funcentries\")\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -26,6 +26,8 @@ def analyzePLT(vw, ssva, ssize):\n# make code for every opcode in PLT\nsva = ssva\nnextseg = sva + ssize\n+\n+ branchvas = []\nwhile sva < nextseg:\nif vw.getLocation(sva) is None:\nlogger.info('making code: 0x%x', sva)\n@@ -37,6 +39,12 @@ def analyzePLT(vw, ssva, ssize):\nltup = vw.getLocation(sva)\nif ltup is not None:\n+ op = vw.parseOpcode(ltup[vivisect.L_VA])\n+ if op.iflags & envi.IF_BRANCH and \\\n+ not op.iflags & envi.IF_COND and \\\n+ not op.opers[-1].getOperValue(op) == ssva:\n+ branchvas.append(op.va)\n+\nsva += ltup[vivisect.L_SIZE]\nlogger.debug('incrementing to next va: 0x%x', sva)\nelse:\n@@ -44,18 +52,59 @@ def analyzePLT(vw, ssva, ssize):\nsva += 1 # FIXME: add architectural \"PLT_INSTRUCTION_INCREMENT\" or something like it\n+ if not len(branchvas):\n+ return\n+\n+ # heuristically determine PLT size\n+ heur = {}\n+ lastva = ssva\n+ for vidx in range(1, len(branchvas)):\n+ bva = branchvas[vidx]\n+ delta = bva - lastva\n+ lastva = bva\n+ heur[delta] = heur.get(delta, 0) + 1\n+\n+ heurlist = [(y, x) for x, y in heur.items()]\n+ heurlist.sort()\n+\n+ plt_size = heurlist[-1][1]\n+ logger.debug('plt_size: 0x%x\\n%r', plt_size, heurlist)\n+\n+ # now get start of first real PLT entry (skipping the initial function at .plt)\n+ bridx = 0\n+ brlen = len(branchvas)\n+ while bridx < brlen - 1:\n+ firstbr = branchvas[bridx]\n+ if branchvas[bridx+1] - firstbr == plt_size:\n+ break\n+ bridx += 1\n+\n+ firstva = firstbr - plt_size + 4 # size of ARM opcode\n+ logger.debug('plt first entry: 0x%x\\n%r', firstva, [hex(x) for x in branchvas])\n+\n# scroll through arbitrary length functions and make functions\n- for sva in range(ssva, nextseg, MAGIC_PLT_SIZE):\n+ for sva in range(firstva, nextseg, plt_size):\nlogger.info('making PLT function: 0x%x', sva)\nvw.makeFunction(sva)\nanalyzeFunction(vw, sva)\n+ '''\n+ vw.makeFunction(ssva)\n+ for jmpva in branchvas:\n+ # need to determine isNop()???\n+ op = vw.parseOpcode(jmpva)\n+ sva = jmpva + len(op)\n+\n+ logger.info('making PLT function: 0x%x', sva)\n+ vw.makeFunction(sva)\n+ analyzeFunction(vw, sva)\n+ '''\n+\nMAX_OPS = 10\ndef analyzeFunction(vw, funcva):\n- logger.info('analyzeFunction(vw, 0x%x)', funcva)\n-\n+ # check to make sure we're in the PLT\nseg = vw.getSegment(funcva)\nif seg is None:\nlogger.info('not analyzing 0x%x: no segment found', funcva)\n@@ -68,71 +117,121 @@ def analyzeFunction(vw, funcva):\nreturn\nlogger.info('analyzing PLT function: 0x%x', funcva)\n+ # start off spinning up an emulator to track through the PLT entry\n+ # slight hack, but we don't currently know if thunk_bx exists\n+ gotplt = None\n+ # Thought: This is DT_PLTGOT, although each ELF will/may have their own DT_PLTGOT.\n+ for va, size, name, fname in vw.getSegments():\n+ if name == \".got.plt\":\n+ gotplt = va\n+ break\n+\n+ if gotplt is None:\n+ gotplt = -1\n+\n+ # all architectures should at least have some minimal emulator\n+ emu = vw.getEmulator()\n+ emu.setRegister(e_i386.REG_EBX, gotplt) # every emulator will have a 4th register, and if it's not used, no harm done.\n+\n+ # roll through instructions looking for a branch (pretty quickly)\ncount = 0\nopva = funcva\ntry:\nop = vw.parseOpcode(opva)\nwhile count < MAX_OPS and op.iflags & envi.IF_BRANCH == 0:\n+ emu.executeOpcode(op)\nopva += len(op)\nop = vw.parseOpcode(opva)\n+ logging.debug(\"0x%x: %r\", opva, op)\n+ count += 1\nexcept Exception as e:\nlogger.warn('failure analyzing PLT func 0x%x: %r', funcva, e)\nreturn\n+ # we've reached the branch instruction or we've gone through too many opcodes\nif op.iflags & envi.IF_BRANCH == 0:\nlogger.warn(\"PLT: 0x%x - Could not find a branch!\", funcva)\nreturn\n- # slight hack, but we don't currently know if thunk_bx exists\n- gotplt = None\n- # FIXME: THIS IS DT_PLTGOT!! DT_PLTGOT for each file....\n- for va, size, name, fname in vw.getSegments():\n- if name == \".got.plt\":\n- gotplt = va\n- break\n-\n- if gotplt is None:\n- gotplt = -1\n-\n- # all architectures should at least have some minimal emulator\n- emu = vw.getEmulator()\n- emu.setRegister(e_i386.REG_EBX, gotplt) # every emulator will have a 4th register, and if it's not used, no harm done.\n-\nbranches = op.getBranches(emu)\nif len(branches) != 1:\nlogger.warn('getBranches() returns anomolous results: 0x%x: %r (result: %r)',\nop.va, op, branches)\nreturn\n+ # get opval (the target of the jump, or the taint) and opref (the reference used to find it)\n+ opref = op.opers[-1].getOperAddr(op, emu) # HACK: this assumes the target is the last operand!\nopval, brflags = branches[0]\n+ if opval is None:\n+ logger.warn(\"getBranches(): opval is None!: op = %r branches = %r\", op, branches)\n+ else:\n+ logger.debug('getBranches(): ref: 0x%x brflags: 0x%x', opval, brflags)\n- if vw.getFunction(opval) == opval:\n- # this is a lazy-link/load function, calling the first entry in the PLT\n- logger.info('0x%x is a non-thunk', funcva)\n+ # add the xref to whatever location referenced (assuming the opref hack worked)\n+ if vw.isValidPointer(opref):\n+ vw.addXref(op.va, opref, vivisect.REF_DATA)\n+\n+ # check the taint tracker to determine if it's an import (the opval value is pointless if it is)\n+ taint = emu.getVivTaint(opval)\n+ if taint is not None:\n+ # if it is an import taint\n+ taintva, ttype, loctup = taint\n+ if ttype != 'import':\n+ logger.warn('getBranches(): returned a Taint which is *not* an import: %r', taint)\nreturn\n+ lva, lsz, ltype, ltinfo = loctup\n+ funcname = ltinfo\n+\n+ else:\n+ #dbg_interact(locals(), globals())\n+\nloctup = vw.getLocation(opval)\n+ # check the location type\n+ if loctup is None:\n+ if opval is None:\n+ logger.warn(\"PLT: 0x%x - branch deref not defined: (opval is None!)\", opva)\n+ else:\n+ logger.warn(\"PLT: 0x%x - making function at location 0x%x\", opva, opval)\n+ vw.makeFunction(opval)\n+ return\n+\n+ # in case the architecture cares about the function address...\n+ opval = vw.arch.archModifyFuncAddr(opval, {})\n+\n+ if vw.getFunction(opval) == opval:\n+ # this \"thunk\" actually calls something in the workspace, that exists as a function...\n+ logger.info('0x%x is a non-thunk', funcva)\n+ vw.addXref(op.va, opval, vivisect.REF_CODE)\n+ vw.setVaSetRow('FuncWrappers', (op.va, opval))\n+\nfuncname = vw.getName(opval)\n- if loctup is None:\n- logger.warn(\"PLT: 0x%x - branch deref not defined: 0x%x\", opva, opval)\n+ #if loctup[vivisect.L_LTYPE] == vivisect.LOC_POINTER: # Some AMD64 PLT entries point at nameless relocations that point internally\n+ # tgtva = loctup[vivisect.L_VA]\n+ # ptrva = vw.readMemoryPtr(tgtva)\n+ # ptrname = vw.getName(ptrva)\n+ # logger.info(\"PLT->PTR 0x%x: (0x%x) -> 0x%x -> 0x%x (%r)\" % (funcva, opval, tgtva, ptrva, ptrname))\n+ # if vw.isValidPointer(ptrva):\n+ # if funcname is None:\n+ # funcname = vw._addNamePrefix(ptrname, ptrva, 'ptr', '_')\n+\n+ #elif loctup[vivisect.L_LTYPE] == vivisect.LOC_IMPORT:\n+ if loctup[vivisect.L_LTYPE] == vivisect.LOC_IMPORT:\n+ logger.warn(\"0x%x: (0x%x) FAIL: dest is LOC_IMPORT but missed taint for %r\", funcva, opval, funcname)\nreturn\n- if loctup[vivisect.L_LTYPE] == vivisect.LOC_POINTER: # Some AMD64 PLT entries point at nameless relocations that point internally\n- tgtva = loctup[vivisect.L_VA]\n- ptrva = vw.readMemoryPtr(tgtva)\n- ptrname = vw.getName(ptrva)\n- logger.info(\"PLT->PTR 0x%x: (0x%x) -> 0x%x -> 0x%x (%r)\" % (funcva, opval, tgtva, ptrva, ptrname))\n- if vw.isValidPointer(ptrva):\n- if funcname is None:\n- funcname = vw._addNamePrefix(ptrname, ptrva, 'ptr', '_')\n+ elif loctup[vivisect.L_LTYPE] == vivisect.LOC_OP:\n+ logger.debug(\"0x%x: succeeded finding LOC_OP at the end of the rainbow! (%r)\", funcva, funcname)\n- elif loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT:\n- logger.warn(\"0x%x: (0x%x) %r != %r (%r)\" % (funcva, opval, loctup[vivisect.L_LTYPE], vivisect.LOC_IMPORT, funcname))\n+ if vw.getFunction(opval) == segva:\n+ # this is a lazy-link/load function, calling the first entry in the PLT\n+ logger.debug('skipping lazy-loader function: 0x%x (calls 0x%x)', funcva, opval)\nreturn\n# if we can't resolve a name, don't make it a thunk\nif funcname is None:\n+ logger.warn('0x%x: FAIL: could not resolve name for 0x%x. Skipping.', funcva, opval)\nreturn\n# trim up the name\n@@ -143,3 +242,39 @@ def analyzeFunction(vw, funcva):\nlogger.info('makeFunctionThunk(0x%x, \"plt_%s\")', funcva, funcname)\nvw.makeFunctionThunk(funcva, \"plt_\" + funcname, addVa=False)\n+\n+\n+def dbg_interact(lcls, gbls):\n+ intro = \"Let's interact!\"\n+ try:\n+ import IPython.Shell\n+ ipsh = IPython.Shell.IPShell(argv=[''], user_ns=lcls, user_global_ns=gbls)\n+ print(intro)\n+ ipsh.mainloop()\n+\n+ except ImportError as e:\n+ try:\n+ from IPython.terminal.interactiveshell import TerminalInteractiveShell\n+ ipsh = TerminalInteractiveShell()\n+ ipsh.user_global_ns.update(gbls)\n+ ipsh.user_global_ns.update(lcls)\n+ ipsh.autocall = 2 # don't require parenthesis around *everything*. be smart!\n+ print(intro)\n+ ipsh.mainloop()\n+ except ImportError as e:\n+ try:\n+ from IPython.frontend.terminal.interactiveshell import TerminalInteractiveShell\n+ ipsh = TerminalInteractiveShell()\n+ ipsh.user_global_ns.update(gbls)\n+ ipsh.user_global_ns.update(lcls)\n+ ipsh.autocall = 2 # don't require parenthesis around *everything*. be smart!\n+\n+ print(intro)\n+ ipsh.mainloop()\n+ except ImportError, e:\n+ print(e)\n+ shell = code.InteractiveConsole(gbls)\n+ print(intro)\n+ shell.interact()\n+\n+\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
elfplt savegame. still sorting out bugs, but example cmln is looking up.
|
718,770 |
30.03.2020 23:01:23
| 14,400 |
f7b0a37f29e4ca7ea1f5c0b97a8b05168a1621ec
|
more elfplt tweaks. not done yet.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -49,13 +49,13 @@ def analyzePLT(vw, ssva, ssize):\nlogger.debug('incrementing to next va: 0x%x', sva)\nelse:\nlogger.warn('makeCode(0x%x) failed to make a location (probably failed instruction decode)! incrementing instruction pointer by 1 to continue PLT analysis <fingers crossed>', sva)\n- sva += 1 # FIXME: add architectural \"PLT_INSTRUCTION_INCREMENT\" or something like it\n+ sva += 1\nif not len(branchvas):\nreturn\n- # heuristically determine PLT size\n+ # heuristically determine PLT entry size\nheur = {}\nlastva = ssva\nfor vidx in range(1, len(branchvas)):\n@@ -70,7 +70,7 @@ def analyzePLT(vw, ssva, ssize):\nplt_size = heurlist[-1][1]\nlogger.debug('plt_size: 0x%x\\n%r', plt_size, heurlist)\n- # now get start of first real PLT entry (skipping the initial function at .plt)\n+ # now get start of first real PLT entry\nbridx = 0\nbrlen = len(branchvas)\nwhile bridx < brlen - 1:\n@@ -82,6 +82,10 @@ def analyzePLT(vw, ssva, ssize):\nfirstva = firstbr - plt_size + 4 # size of ARM opcode\nlogger.debug('plt first entry: 0x%x\\n%r', firstva, [hex(x) for x in branchvas])\n+ if bridx != 0:\n+ logger.debug('First function in PLT is not a PLT entry. Found Lazy Loader Trampoline.')\n+ vw.makeName(ssva, 'LazyLoaderTrampoline', filelocal=True)\n+\n# scroll through arbitrary length functions and make functions\nfor sva in range(firstva, nextseg, plt_size):\nlogger.info('making PLT function: 0x%x', sva)\n@@ -169,6 +173,7 @@ def analyzeFunction(vw, funcva):\n# add the xref to whatever location referenced (assuming the opref hack worked)\nif vw.isValidPointer(opref):\n+ logger.debug('reference 0x%x is valid, adding Xref', opref)\nvw.addXref(op.va, opref, vivisect.REF_DATA)\n# check the taint tracker to determine if it's an import (the opval value is pointless if it is)\n@@ -182,6 +187,7 @@ def analyzeFunction(vw, funcva):\nlva, lsz, ltype, ltinfo = loctup\nfuncname = ltinfo\n+ logger.debug('0x%x: LOC_IMPORT: 0x%x: %r', opva, lva, funcname)\nelse:\n#dbg_interact(locals(), globals())\n@@ -197,15 +203,17 @@ def analyzeFunction(vw, funcva):\nreturn\n# in case the architecture cares about the function address...\n- opval = vw.arch.archModifyFuncAddr(opval, {})\n+ aopval, aflags = vw.arch.archModifyFuncAddr(opval, {})\n+ funcname = vw.getName(aopval)\n+ if funcname is None:\n+ funcname = vw.getName(opval)\n- if vw.getFunction(opval) == opval:\n+ if vw.getFunction(aopval) == aopval:\n# this \"thunk\" actually calls something in the workspace, that exists as a function...\n- logger.info('0x%x is a non-thunk', funcva)\n- vw.addXref(op.va, opval, vivisect.REF_CODE)\n+ logger.info('0x%x points to real code (0x%x: %r)', funcva, opval, funcname)\n+ vw.addXref(op.va, aopval, vivisect.REF_CODE)\nvw.setVaSetRow('FuncWrappers', (op.va, opval))\n- funcname = vw.getName(opval)\n#if loctup[vivisect.L_LTYPE] == vivisect.LOC_POINTER: # Some AMD64 PLT entries point at nameless relocations that point internally\n# tgtva = loctup[vivisect.L_VA]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
more elfplt tweaks. not done yet.
|
718,770 |
30.03.2020 23:02:08
| 14,400 |
bb1310de2c429533a2c8c6902a5224d32bd59a12
|
allow makeFunctionThunk() to set filelocal.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1479,7 +1479,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nret = []\nreturn ret\n- def makeFunctionThunk(self, fva, thname, addVa=True):\n+ def makeFunctionThunk(self, fva, thname, addVa=True, filelocal=False):\n\"\"\"\nInform the workspace that a given function is considered a \"thunk\" to another.\nThis allows the workspace to process argument inheritance and several other things.\n@@ -1496,7 +1496,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nname = \"%s_%.8x\" % (base,fva)\nelse:\nname = base\n- newname = self.makeName(fva, name, makeuniq=True)\n+ newname = self.makeName(fva, name, filelocal=filelocal, makeuniq=True)\nlogger.debug('makeFunctionThunk: makeName(0x%x, %r, makeuniq=True): returned %r', fva, name, newname)\napi = self.getImpApi(thname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
allow makeFunctionThunk() to set filelocal.
|
718,770 |
30.03.2020 23:04:52
| 14,400 |
b0be9fae4c70df88d618c41942b5a75b3e4ed5f1
|
allow architecture to fixup Xrefs in vw._handleADDRELOC() (was causing all the THUMB relocations to completely screw up the locations database).
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -260,8 +260,9 @@ class VivWorkspaceCore(object, viv_impapi.ImportApi):\n# self.addXref(va, tova, REF_PTR)\n# ploc = self.addLocation(va, psize, LOC_POINTER)\n# don't follow. handle it later, once \"known code\" is analyzed\n+ ptr, reftype, rflags = self.arch.archModifyXrefAddr(ptr, None, None)\nself._handleADDXREF((rva, ptr, REF_PTR, 0))\n- self._handleADDLOCATION((rva, self.psize, LOC_POINTER, None))\n+ self._handleADDLOCATION((rva, self.psize, LOC_POINTER, ptr))\ndef _handleADDMODULE(self, einfo):\nprint('DEPRICATED (ADDMODULE) ignored: %s' % einfo)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
allow architecture to fixup Xrefs in vw._handleADDRELOC() (was causing all the THUMB relocations to completely screw up the locations database).
|
718,770 |
31.03.2020 13:06:59
| 14,400 |
7bb1f17043337833b817962129d92a0334c94c3e
|
arch-flip bugfix.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -91,17 +91,6 @@ def analyzePLT(vw, ssva, ssize):\nlogger.info('making PLT function: 0x%x', sva)\nvw.makeFunction(sva)\nanalyzeFunction(vw, sva)\n- '''\n- vw.makeFunction(ssva)\n- for jmpva in branchvas:\n- # need to determine isNop()???\n- op = vw.parseOpcode(jmpva)\n- sva = jmpva + len(op)\n-\n- logger.info('making PLT function: 0x%x', sva)\n- vw.makeFunction(sva)\n- analyzeFunction(vw, sva)\n- '''\nMAX_OPS = 10\n@@ -190,17 +179,16 @@ def analyzeFunction(vw, funcva):\nlogger.debug('0x%x: LOC_IMPORT: 0x%x: %r', opva, lva, funcname)\nelse:\n- #dbg_interact(locals(), globals())\n-\n+ # instead of a taint (which *should* indicate an IMPORT), we have real pointer.\nloctup = vw.getLocation(opval)\n# check the location type\nif loctup is None:\nif opval is None:\nlogger.warn(\"PLT: 0x%x - branch deref not defined: (opval is None!)\", opva)\n+ return\nelse:\nlogger.warn(\"PLT: 0x%x - making function at location 0x%x\", opva, opval)\nvw.makeFunction(opval)\n- return\n# in case the architecture cares about the function address...\naopval, aflags = vw.arch.archModifyFuncAddr(opval, {})\n@@ -208,11 +196,14 @@ def analyzeFunction(vw, funcva):\nif funcname is None:\nfuncname = vw.getName(opval)\n- if vw.getFunction(aopval) == aopval:\n+ if vw.getFunction(aopval) is None:\n+ logger.debug(\"0x%x: code does not exist at 0x%x. calling makeFunction()\", funcva, aopval)\n+ vw.makeFunction(aopval, arch=aflags['arch'])\n+\n# this \"thunk\" actually calls something in the workspace, that exists as a function...\nlogger.info('0x%x points to real code (0x%x: %r)', funcva, opval, funcname)\nvw.addXref(op.va, aopval, vivisect.REF_CODE)\n- vw.setVaSetRow('FuncWrappers', (op.va, opval))\n+ vw.setVaSetRow('FuncWrappers', (funcva, opval))\n#if loctup[vivisect.L_LTYPE] == vivisect.LOC_POINTER: # Some AMD64 PLT entries point at nameless relocations that point internally\n@@ -249,7 +240,7 @@ def analyzeFunction(vw, funcva):\nfuncname = funcname[:-9]\nlogger.info('makeFunctionThunk(0x%x, \"plt_%s\")', funcva, funcname)\n- vw.makeFunctionThunk(funcva, \"plt_\" + funcname, addVa=False)\n+ vw.makeFunctionThunk(funcva, \"plt_\" + funcname, addVa=False, filelocal=True)\ndef dbg_interact(lcls, gbls):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
arch-flip bugfix.
|
718,770 |
04.04.2020 17:07:32
| 14,400 |
a7661dfe54dbf1f84361d7adae9c17a36f9e5664
|
lots of bugfixes and logging.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -251,7 +251,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef executeOpcode(self, op):\n# NOTE: If an opcode method returns\n- # other than None, that is the new eip\n+ # other than None, that is the new pc\ntry:\nself.setMeta('forrealz', True)\nnewpc = None\n@@ -276,7 +276,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# the actual execution... if we're supposed to.\nif condval and not skip:\nmeth = self.op_methods.get(op.mnem, None)\n- if meth == None:\n+ if meth is None:\nraise envi.UnsupportedInstruction(self, op)\n# executing opcode now...\n@@ -284,7 +284,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\npc = self.getProgramCounter()\n# returned None, so the instruction hasn't directly changed PC\n- if newpc == None:\n+ if newpc is None:\nnewpc = pc+op.size\n# we don't want to trust the opcode emulator to know that it's updating PC\n@@ -1196,11 +1196,12 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# hint: covers ldr, ldrb, ldrbt, ldrd, ldrh, ldrsh, ldrsb, ldrt (any instr where the syntax is ldr{condition}stuff)\n# need to check that t variants only allow non-priveleged access (ldrt, ldrht etc)\nval = self.getOperValue(op, 1)\n- self.setOperValue(op, 0, val)\nif op.opers[0].reg == REG_PC:\nself.setThumbMode(val & 1)\nreturn val & -2\n+ self.setOperValue(op, 0, val)\n+\ni_ldrb = i_ldr\ni_ldrbt = i_ldr\ni_ldrd = i_ldr\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -283,6 +283,7 @@ class CodeFlowContext(object):\n# Finally, notify the callback of a new function\nself._cb_function(va, {'CallsFrom':calls_from})\n+ return va\ndef flushFunction(self, fva):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "import sys\n+import logging\nimport vivisect\nimport vivisect.impemu.monitor as viv_monitor\n@@ -13,6 +14,9 @@ from envi.archs.arm.const import *\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n+\nclass AnalysisMonitor(viv_monitor.AnalysisMonitor):\ndef __init__(self, vw, fva, verbose=True):\n@@ -32,16 +36,17 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\ntmode = emu.getFlag(PSR_T_bit)\nself.last_tmode = tmode\n#if self.verbose: print( \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op))\n- #if op == self.badop:\nif op in self.badops:\nraise Exception(\"Hit known BADOP at 0x%.8x %s (fva: 0x%x)\" % (starteip, repr(op), self.fva))\nviv_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\nloctup = emu.vw.getLocation(starteip)\n- if loctup == None:\n+ if loctup is None:\n# do we want to hand this off to makeCode?\n- emu.vw.addLocation(starteip, len(op), vivisect.LOC_OP, op.iflags)\n+ #print \"emulation: prehook: new LOC_OP fva: 0x%x starteip: 0x%x flags: 0x%x\" % (self.fva, starteip, op.iflags)\n+ arch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[(starteip & 1) | tmode]\n+ emu.vw.makeCode(starteip & -2, arch=arch)\nelif loctup[2] != LOC_OP:\nif self.verbose: print(\"ARG! emulation found opcode in an existing NON-OPCODE location (0x%x): 0x%x: %s\" % (loctup[0], op.va, op))\n@@ -111,10 +116,13 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nif self.verbose: print(\"+++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\")\nif op.va not in self.infloops:\nself.infloops.append(op.va)\n+ if 'InfiniteLoops' not in vw.getVaSetNames():\n+ vw.addVaSet('InfiniteLoops', (('va', vivisect.VASET_ADDRESS, 'function', vivisect.VASET_STRING)))\n+ self.vw.setVaSetRow('InfiniteLoops', (op.va, self.fva))\nexcept Exception, e:\n# FIXME: make raise Exception?\n- print(\"0x%x: ERROR: %s\" % (op.va, e))\n+ logger.info(\"0x%x: (%r) ERROR: %s\",op.va, op, e)\nexcept Exception, e:\n# FIXME: make raise Exception?\n@@ -174,27 +182,27 @@ def analyzeFunction(vw, fva):\nemu.setEmulationMonitor(emumon)\nloc = vw.getLocation(fva)\n- if loc != None:\n+ if loc is not None:\nlva, lsz, lt, lti = loc\nif lt == LOC_OP:\nif (lti & envi.ARCH_MASK) != envi.ARCH_ARMV7:\nemu.setFlag(PSR_T_bit, 1)\nelse:\n- print(\"NO LOCATION at FVA: 0x%x\" % fva)\n+ logger.warn(\"NO LOCATION at FVA: 0x%x\", fva)\nemu.runFunction(fva, maxhit=1)\n# Do we already have API info in meta?\n# NOTE: do *not* use getFunctionApi here, it will make one!\napi = vw.getFunctionMeta(fva, 'api')\n- if api == None:\n+ if api is None:\napi = buildFunctionApi(vw, fva, emu, emumon)\nrettype,retname,callconv,callname,callargs = api\nargc = len(callargs)\ncc = emu.getCallingConvention(callconv)\n- if cc == None:\n+ if cc is None:\nreturn\nstcount = cc.getNumStackArgs(emu, argc)\n@@ -286,7 +294,13 @@ def analyzeTB(emu, op, starteip, amon):\nnexttgt = base + nextoff\nemu.vw.makeNumber(ova, 2)\n# check for loc first?\n- emu.vw.makeCode(nexttgt)\n+ if nexttgt & 1:\n+ nexttgt &= -2\n+ arch = envi.ARCH_THUMB\n+ else:\n+ arch = envi.ARCH_ARMV7\n+\n+ emu.vw.makeCode(nexttgt, arch=arch)\n# check xrefs fist?\nemu.vw.addXref(op.va, nexttgt, REF_CODE)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -743,6 +743,7 @@ class VivCodeFlowContext(e_codeflow.CodeFlowContext):\nfor fmname in vw.fmodlist:\nfmod = vw.fmods.get(fmname)\ntry:\n+ logger.debug('fmod: 0x%x (%r)', fva, fmod)\nfmod.analyzeFunction(vw, fva)\nexcept Exception as e:\nif vw.verbose:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -163,6 +163,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.setEmuSnap(esnap)\nself.setProgramCounter(va)\n+ tmode = self.getFlag(PSR_T_bit)\n# Check if we are beyond our loop max...\nif maxloop is not None:\n@@ -195,7 +196,6 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\ntry:\n- tmode = self.getFlag(PSR_T_bit)\n# FIXME unify with stepi code...\nop = self.parseOpcode(starteip | tmode)\n@@ -239,6 +239,8 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nfor bva, bpath in blist:\ntodo.append((bva, esnap, bpath))\nbreak\n+\n+ else:\n# check if we've blx'd to a different thumb state. if so,\n# be sure to return to the original tmode before continuing emulation pass\nnewtmode = self.getFlag(PSR_T_bit)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -673,8 +673,11 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nif vw.vaByName(pname) is None:\nvw.makeName(rlva, pname)\n+ # name the target as well\nif addbase:\nptr += baseaddr\n+ # normalize thumb addresses\n+ ptr &= -2\nvw.makeName(ptr, name)\nvw.setComment(ptr, dmglname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
lots of bugfixes and logging.
|
718,770 |
06.04.2020 16:23:45
| 14,400 |
c8e6d4038bf8faabeca15acfea642cf7abc58fd3
|
just adding a few defines i got from apple's opensource repos.
|
[
{
"change_type": "MODIFY",
"old_path": "vstruct/defs/macho/const.py",
"new_path": "vstruct/defs/macho/const.py",
"diff": "@@ -63,14 +63,23 @@ LC_SUB_CLIENT = 0x14 # sub client\nLC_SUB_LIBRARY = 0x15 # sub library\nLC_TWOLEVEL_HINTS = 0x16 # two-level namespace lookup hints\nLC_PREBIND_CKSUM = 0x17 # prebind checksum\n+LC_LOAD_WEAK_DYLIB = (0x18 | LC_REQ_DYLD)\nLC_SEGMENT_64 = 0x19 # 64-bit segment of this file to bemapped\nLC_ROUTINES_64 = 0x1a # 64-bit image routines\nLC_UUID = 0x1b # the uuid\n+LC_RPATH = (0x1c | LC_REQ_DYLD)\nLC_CODE_SIGNATURE = 0x1d # local of code signature\nLC_SEGMENT_SPLIT_INFO = 0x1e # local of info to split segments\n+LC_REEXPORT_DYLIB = (0x1f | LC_REQ_DYLD)\nLC_LAZY_LOAD_DYLIB = 0x20 # delay load of dylib until first use\nLC_ENCRYPTION_INFO = 0x21 # encrypted segment information\nLC_DYLD_INFO = 0x22 # compressed dyld information\n+LC_DYLD_INFO_ONLY = (0x22|LC_REQ_DYLD)\n+LC_LOAD_UPWARD_DYLIB = (0x23|LC_REQ_DYLD)\n+LC_VERSION_MIN_MACOSX = 0x24\n+LC_VERSION_MIN_IPHONEOS = 0x25\n+LC_FUNCTION_STARTS = 0x26\n+LC_DYLD_ENVIRONMENT = 0x27\nSG_HIGHVM = 0x1 # the file contents for this segment is forthe high part of the VM space, the low partis zero filled (for stacks in core files)\nSG_FVMLIB = 0x2 # this segment is the VM that is allocated bya fixed VM library, for overlap checking inthe link editor\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
just adding a few defines i got from apple's opensource repos.
|
718,770 |
08.04.2020 23:51:55
| 14,400 |
50a1dde3eb2077bc68f0d6df91646b0636767d87
|
bugfixes and savegame. this seems to make amd64/ls happy.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -22,11 +22,15 @@ def analyze(vw):\ncontinue\nanalyzePLT(vw, sva, ssize)\n+\ndef analyzePLT(vw, ssva, ssize):\n# make code for every opcode in PLT\nsva = ssva\nnextseg = sva + ssize\n+ trampbr = None\n+ hastramp = False\n+\nbranchvas = []\nwhile sva < nextseg:\nif vw.getLocation(sva) is None:\n@@ -41,9 +45,14 @@ def analyzePLT(vw, ssva, ssize):\nif ltup is not None:\nop = vw.parseOpcode(ltup[vivisect.L_VA])\nif op.iflags & envi.IF_BRANCH and \\\n- not op.iflags & envi.IF_COND and \\\n- not op.opers[-1].getOperValue(op) == ssva:\n- branchvas.append(op.va)\n+ not op.iflags & envi.IF_COND:\n+\n+ # we grab all unconditional branches, and tag them\n+ realplt = not bool(op.opers[-1].getOperValue(op) == ssva)\n+ if not realplt:\n+ hastramp = True\n+\n+ branchvas.append((op.va, realplt))\nsva += ltup[vivisect.L_SIZE]\nlogger.debug('incrementing to next va: 0x%x', sva)\n@@ -51,15 +60,39 @@ def analyzePLT(vw, ssva, ssize):\nlogger.warn('makeCode(0x%x) failed to make a location (probably failed instruction decode)! incrementing instruction pointer by 1 to continue PLT analysis <fingers crossed>', sva)\nsva += 1\n-\nif not len(branchvas):\nreturn\n- # heuristically determine PLT entry size\n+ ###### FIXME BETWEEN THESE ######\n+ # plt entries have:\n+ # a distance between starts/finish\n+ # a size\n+ # they are not the same.\n+\n+ if hastramp:\n+ # find the tramp's branch\n+ trampbr = ssva\n+ loc = vw.getLocation(trampbr)\n+ while loc is not None and (loc[vivisect.L_TINFO] & envi.IF_BRANCH == 0):\n+ lva, lsz, ltype, ltinfo = loc\n+ trampbr += lsz\n+ loc = vw.getLocation(trampbr)\n+\n+ # set our branchva list straight. trampoline is *not* a realplt.\n+ if branchvas[0][0] == trampbr:\n+ branchvas[0] = (trampbr, False)\n+ else:\n+ logger.debug(\"hastramp: trampbr: 0x%x branchvas[0][0]: 0x%x\", trampbr, branchvas[0][0])\n+\n+ # heuristically determine PLT entry size and distance\nheur = {}\nlastva = ssva\n+ # first determine distance between GOT branches:\nfor vidx in range(1, len(branchvas)):\n- bva = branchvas[vidx]\n+ bva, realplt = branchvas[vidx]\n+ if not realplt:\n+ continue\n+\ndelta = bva - lastva\nlastva = bva\nheur[delta] = heur.get(delta, 0) + 1\n@@ -67,27 +100,75 @@ def analyzePLT(vw, ssva, ssize):\nheurlist = [(y, x) for x, y in heur.items()]\nheurlist.sort()\n- plt_size = heurlist[-1][1]\n- logger.debug('plt_size: 0x%x\\n%r', plt_size, heurlist)\n+ # distance should be the greatest value.\n+ plt_distance = heurlist[-1][1]\n+ logger.debug('plt_distance : 0x%x\\n%r', plt_distance, heurlist)\n+\n+ # there should be only one heuristic\n+ if len(heurlist) > 1:\n+ logger.warn(\"heuristics have more than one tracked branch: investigate! PLT analysis is likely to be wrong (%r)\", heurlist)\n+\n+ # now determine plt_size (basically, how far to backup from the branch to find the start of function\n+ # *don't* use the first entry, because the trampoline is often odd...\n+ plt_size = 0 # not including the branch instruction size?\n+ bridx = 1\n+\n+ # if hastramp, we need to skip two to make sure we're not analyzing the first real plt\n+ if hastramp:\n+ bridx += 1\n+\n+ brva, realplt = branchvas[bridx]\n+ while brva != trampbr and not realplt:\n+ bridx += 1\n+ brva, realplt = branchvas[bridx]\n+\n+ # start off pointing at the branch location which bounces through GOT.\n+ loc = vw.getLocation(brva)\n+ # grab the size of the plt branch instruction for our benefit\n+ pltbrsz = loc[vivisect.L_SIZE]\n+\n+ # we're searching for a point where either we hit:\n+ # * another branch (ie. lazy-loader) or\n+ # * non-Opcode (eg. literal pool)\n+ # bounded to what we know is the distance between PLT branches\n+ while loc is not None and \\\n+ plt_size <= plt_distance:\n+ # first we back up one location\n+ loc = vw.getLocation(loc[vivisect.L_VA] - 1)\n+ lva, lsz, ltype, ltinfo = loc\n+\n+ if ltype != vivisect.LOC_OP:\n+ # we've run into a non-opcode location: bail!\n+ break\n+\n+ if ltinfo & envi.IF_BRANCH:\n+ # we've hit another branch instruction. stop!\n+ break\n+\n+ plt_size += lsz\n# now get start of first real PLT entry\nbridx = 0\nbrlen = len(branchvas)\n- while bridx < brlen - 1:\n- firstbr = branchvas[bridx]\n- if branchvas[bridx+1] - firstbr == plt_size:\n- break\n+\n+ firstbr, realplt = branchvas[bridx]\n+ while not realplt:\n+ firstbr, realplt = branchvas[bridx]\nbridx += 1\n- firstva = firstbr - plt_size + 4 # size of ARM opcode\n- logger.debug('plt first entry: 0x%x\\n%r', firstva, [hex(x) for x in branchvas])\n+\n+ firstva = firstbr - plt_size\n+ logger.debug('plt first entry: 0x%x\\n%r', firstva, [(hex(x), y) for x, y in branchvas])\n+ ###### FIXME BETWEEN THESE ######\n+\n+ dbg_interact(locals(), globals())\nif bridx != 0:\nlogger.debug('First function in PLT is not a PLT entry. Found Lazy Loader Trampoline.')\nvw.makeName(ssva, 'LazyLoaderTrampoline', filelocal=True)\n# scroll through arbitrary length functions and make functions\n- for sva in range(firstva, nextseg, plt_size):\n+ for sva in range(firstva, nextseg, plt_distance):\nlogger.info('making PLT function: 0x%x', sva)\nvw.makeFunction(sva)\nanalyzeFunction(vw, sva)\n@@ -198,15 +279,6 @@ def analyzeFunction(vw, funcva):\nif funcname is None:\nfuncname = vw.getName(opval)\n- if vw.getFunction(aopval) is None:\n- logger.debug(\"0x%x: code does not exist at 0x%x. calling makeFunction()\", funcva, aopval)\n- vw.makeFunction(aopval, arch=aflags['arch'])\n-\n- # this \"thunk\" actually calls something in the workspace, that exists as a function...\n- logger.info('0x%x points to real code (0x%x: %r)', funcva, opval, funcname)\n- vw.addXref(op.va, aopval, vivisect.REF_CODE)\n- vw.setVaSetRow('FuncWrappers', (funcva, opval))\n-\n#if loctup[vivisect.L_LTYPE] == vivisect.LOC_POINTER: # Some AMD64 PLT entries point at nameless relocations that point internally\n# tgtva = loctup[vivisect.L_VA]\n@@ -219,11 +291,21 @@ def analyzeFunction(vw, funcva):\n#elif loctup[vivisect.L_LTYPE] == vivisect.LOC_IMPORT:\nif loctup[vivisect.L_LTYPE] == vivisect.LOC_IMPORT:\n- logger.warn(\"0x%x: (0x%x) FAIL: dest is LOC_IMPORT but missed taint for %r\", funcva, opval, funcname)\n- return\n+ logger.warn(\"0x%x: (0x%x) dest is LOC_IMPORT but missed taint for %r\", funcva, opval, funcname)\n+ lva, lsz, ltype, ltinfo = loctup\n+ funcname = ltinfo\nelif loctup[vivisect.L_LTYPE] == vivisect.LOC_OP:\nlogger.debug(\"0x%x: succeeded finding LOC_OP at the end of the rainbow! (%r)\", funcva, funcname)\n+ if vw.getFunction(aopval) is None:\n+ logger.debug(\"0x%x: code does not exist at 0x%x. calling makeFunction()\", funcva, aopval)\n+ vw.makeFunction(aopval, arch=aflags['arch'])\n+\n+ # this \"thunk\" actually calls something in the workspace, that exists as a function...\n+ logger.info('0x%x points to real code (0x%x: %r)', funcva, opval, funcname)\n+ vw.addXref(op.va, aopval, vivisect.REF_CODE)\n+ vw.setVaSetRow('FuncWrappers', (funcva, opval))\n+\nif vw.getFunction(opval) == segva:\n# this is a lazy-link/load function, calling the first entry in the PLT\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfixes and savegame. this seems to make amd64/ls happy.
|
718,770 |
09.04.2020 09:46:23
| 14,400 |
c6f77250102f006b56e061a636cefb320bdbd58e
|
minor improvements, but still with some bugs. wasn't taking into account the way getBranches can hand out both direct addresses (code) and BR_DEREF (pointers). about to revamp a bit. SAVEGAME!
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -129,6 +129,7 @@ def analyzePLT(vw, ssva, ssize):\n# we're searching for a point where either we hit:\n# * another branch (ie. lazy-loader) or\n# * non-Opcode (eg. literal pool)\n+ # * or a NOP\n# bounded to what we know is the distance between PLT branches\nwhile loc is not None and \\\nplt_size <= plt_distance:\n@@ -144,6 +145,11 @@ def analyzePLT(vw, ssva, ssize):\n# we've hit another branch instruction. stop!\nbreak\n+ op = vw.parseOpcode(lva)\n+ if op.mnem == 'nop': # should we let architectures set a \"nop\" iflag\n+ # we've run into inter-plt padding - curse you, i386 gcc!\n+ break\n+\nplt_size += lsz\n# now get start of first real PLT entry\n@@ -268,6 +274,7 @@ def analyzeFunction(vw, funcva):\nvw.makeFunction(opval)\nloctup = vw.getLocation(opval)\n+ lva, lsz, ltype, ltinfo = loctup\n# in case the architecture cares about the function address...\naopval, aflags = vw.arch.archModifyFuncAddr(opval, {'arch': envi.ARCH_DEFAULT})\n@@ -276,12 +283,12 @@ def analyzeFunction(vw, funcva):\nfuncname = vw.getName(opval)\n# sort through the location types and adjust accordingly\n- if loctup[vivisect.L_LTYPE] == vivisect.LOC_IMPORT:\n+ if ltype == vivisect.LOC_IMPORT:\nlogger.warn(\"0x%x: (0x%x) dest is LOC_IMPORT but missed taint for %r\", funcva, opval, funcname)\n- lva, lsz, ltype, ltinfo = loctup\n+ # import locations store the name as ltinfo\nfuncname = ltinfo\n- elif loctup[vivisect.L_LTYPE] == vivisect.LOC_OP:\n+ elif ltype == vivisect.LOC_OP:\nlogger.debug(\"0x%x: succeeded finding LOC_OP at the end of the rainbow! (%r)\", funcva, funcname)\nif vw.getFunction(aopval) is None:\nlogger.debug(\"0x%x: code does not exist at 0x%x. calling makeFunction()\", funcva, aopval)\n@@ -292,6 +299,10 @@ def analyzeFunction(vw, funcva):\nvw.addXref(op.va, aopval, vivisect.REF_CODE)\nvw.setVaSetRow('FuncWrappers', (funcva, opval))\n+ elif ltype == vivisect.LOC_POINTER:\n+ logger.warn(\"0x%x: (0x%x) dest is LOC_POINTER -> 0x%x\", funcva, opval, ltinfo)\n+ funcname = ltinfo\n+\nif vw.getFunction(opval) == segva:\n# this is a lazy-link/load function, calling the first entry in the PLT\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
minor improvements, but still with some bugs. wasn't taking into account the way getBranches can hand out both direct addresses (code) and BR_DEREF (pointers). about to revamp a bit. SAVEGAME!
|
718,770 |
09.04.2020 11:27:42
| 14,400 |
be15144c6a78a5521362416147114a95366ac36b
|
works on amd64/libc now... cycling back to check all unittest files.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3919,7 +3919,6 @@ class ArmOpcode(envi.Opcode):\nret.append((self.va + self.size, envi.BR_FALL | self._def_arch))\n#print \"getBranches: next...\", hex(self.va), self.size\n- # FIXME if this is a move to PC god help us...\nflags = 0\nif self.prefixes != COND_AL:\n@@ -3932,7 +3931,7 @@ class ArmOpcode(envi.Opcode):\noperval = oper.getOperValue(self, emu)\nif self.opcode in (INS_BLX, INS_BX):\n- if operval != None and operval & 3:\n+ if operval is not None and operval & 3:\nflags |= envi.ARCH_THUMB\noperval &= -2\nelse:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -229,25 +229,44 @@ def analyzeFunction(vw, funcva):\nlogger.warn(\"PLT: 0x%x - Could not find a branch!\", funcva)\nreturn\n+ # cycle through the opcode's \"branches\" to make connections and look for funcname.\n+ # BR_DEREF - the address in opval is a pointer, not code\n+ # BR_FALL - the address is the next instruction (should never happen here)\n+ funcname = None\nbranches = op.getBranches(emu)\n- if len(branches) != 1:\n- logger.warn('getBranches() returns anomolous results: 0x%x: %r (result: %r)',\n- op.va, op, branches)\n- return\n+ logger.debug(\"getBranches returned: %r\", branches)\n- # get opval (the target of the jump, or the taint) and opref (the reference used to find it)\n- opref = op.opers[-1].getOperAddr(op, emu) # HACK: this assumes the target is the last operand!\n- opval, brflags = branches[0]\n+ for opval, brflags in branches:\nif opval is None:\nlogger.warn(\"getBranches(): opval is None!: op = %r branches = %r\", op, branches)\nelse:\nlogger.debug('getBranches(): ref: 0x%x brflags: 0x%x', opval, brflags)\n+ loctup = vw.getLocation(opval)\n+\n+ # if BR_DEREF, this is a pointer\n+ if brflags & envi.BR_DEREF:\n+ if loctup is not None:\n+ lva, lsz, ltype, ltinfo = loctup\n+ opref = opval\n# add the xref to whatever location referenced (assuming the opref hack worked)\nif vw.isValidPointer(opref):\nlogger.debug('reference 0x%x is valid, adding Xref', opref)\nvw.addXref(op.va, opref, vivisect.REF_DATA)\n+ if ltype == vivisect.LOC_IMPORT:\n+ # import locations store the name as ltinfo\n+ funcname = ltinfo\n+ logger.warn(\"0x%x: (0x%x) LOC_IMPORT by BR_DEREF %r\", funcva, opval, funcname)\n+\n+ elif ltype == vivisect.LOC_POINTER:\n+ # we have a deref to a pointer.\n+ funcname = vw.getName(ltinfo)\n+ logger.warn(\"0x%x: (0x%x->0x%x) LOC_POINTER by BR_DEREF %r\", funcva, opval, ltinfo, funcname)\n+ else:\n+ logger.warn(\"0x%x: (0x%x) not LOC_IMPORT or LOC_POINTER?? by BR_DEREF %r\", funcva, opval, loctup)\n+\n+ else:\n# check the taint tracker to determine if it's an import (the opval value is pointless if it is)\ntaint = emu.getVivTaint(opval)\nif taint is not None:\n@@ -259,11 +278,10 @@ def analyzeFunction(vw, funcva):\nlva, lsz, ltype, ltinfo = loctup\nfuncname = ltinfo\n- logger.debug('0x%x: LOC_IMPORT: 0x%x: %r', opva, lva, funcname)\n+ logger.debug('0x%x: LOC_IMPORT (emu-taint): 0x%x: %r', opva, lva, funcname)\nelse:\n# instead of a taint (which *should* indicate an IMPORT), we have real pointer.\n- loctup = vw.getLocation(opval)\n# check the location type\nif loctup is None:\nif opval is None:\n@@ -287,6 +305,7 @@ def analyzeFunction(vw, funcva):\nlogger.warn(\"0x%x: (0x%x) dest is LOC_IMPORT but missed taint for %r\", funcva, opval, funcname)\n# import locations store the name as ltinfo\nfuncname = ltinfo\n+ dbg_interact(locals(), globals())\nelif ltype == vivisect.LOC_OP:\nlogger.debug(\"0x%x: succeeded finding LOC_OP at the end of the rainbow! (%r)\", funcva, funcname)\n@@ -309,6 +328,7 @@ def analyzeFunction(vw, funcva):\nlogger.debug('skipping lazy-loader function: 0x%x (calls 0x%x)', funcva, opval)\nreturn\n+ # now make the thunk with appropriate naming\n# if we can't resolve a name, don't make it a thunk\nif funcname is None:\nlogger.warn('0x%x: FAIL: could not resolve name for 0x%x. Skipping.', funcva, opval)\n@@ -317,6 +337,12 @@ def analyzeFunction(vw, funcva):\n# trim up the name\nif funcname.startswith('*.'):\nfuncname = funcname[2:]\n+\n+ # if filelocal for the target symbol, strip off the filename\n+ if funcname.startswith(fname + \".\"):\n+ funcname = funcname[len(fname)+1:]\n+\n+ # trim off any address at the end\nif funcname.endswith('_%.8x' % opval):\nfuncname = funcname[:-9]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
works on amd64/libc now... cycling back to check all unittest files.
|
718,770 |
10.04.2020 18:36:35
| 14,400 |
3752088617f60e2b44ece9a94e8dacba72e7b31b
|
bugfixes and normalizing emulation, elfplt and ARM ELF relocations...
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3954,6 +3954,13 @@ class ArmOpcode(envi.Opcode):\nprint \"0x%x: %r getBranches() with no emulator\" % (self.va, self)\n'''\nelse:\n+ # actually add the branch here...\n+ # if we are a deref, add the DEREF\n+ if oper.isDeref():\n+ ref = oper.getOperAddr(self, emu)\n+ ret.append((ref, flags | envi.BR_DEREF))\n+\n+ # if we point to a valid address, add that branch as well:\nret.append((operval, flags))\n#print \"getBranches: (0x%x) add 0x%x %x\"% (self.va, operval, flags)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -79,10 +79,12 @@ def addAnalysisModules(vw):\n# elfplt wants to be run before generic.entrypoints.\nvw.addAnalysisModule(\"vivisect.analysis.elf.elfplt\")\n+ # due to inconsistencies in plt layouts, we'll keep this as a func module as well\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.elf.elfplt\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.entrypoints\")\nvw.addAnalysisModule(\"vivisect.analysis.elf\")\n- if arch in ('i386', 'amd64'):\n+ if arch in ('i386', 'amd64', 'arm'):\nvw.addImpApi('posix', arch)\nif arch == 'i386':\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -37,6 +37,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nself.last_tmode = tmode\n#if self.verbose: print( \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op))\nif op in self.badops:\n+ emu.stopEmu()\nraise Exception(\"Hit known BADOP at 0x%.8x %s (fva: 0x%x)\" % (starteip, repr(op), self.fva))\nviv_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n@@ -49,11 +50,11 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nemu.vw.makeCode(starteip & -2, arch=arch)\nelif loctup[2] != LOC_OP:\n- if self.verbose: print(\"ARG! emulation found opcode in an existing NON-OPCODE location (0x%x): 0x%x: %s\" % (loctup[0], op.va, op))\n+ logger.info(\"ARG! emulation found opcode in an existing NON-OPCODE location (0x%x): 0x%x: %s\", loctup[0], op.va, op)\nemu.stopEmu()\nelif loctup[0] != starteip:\n- if self.verbose: print(\"ARG! emulation found opcode in a location at the wrong address (0x%x): 0x%x: %s\" % (loctup[0], op.va, op))\n+ logger.info(\"ARG! emulation found opcode in a location at the wrong address (0x%x): 0x%x: %s\", loctup[0], op.va, op)\nemu.stopEmu()\nif op.iflags & envi.IF_RET:\n@@ -84,7 +85,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nelif op.opcode == INS_BX:\nif starteip - self.last_lr_pc <= 4:\n# this is a call. the compiler updated lr\n- if self.verbose: print(\"CALL by mov lr, pc; bx <foo> at 0x%x\" % starteip)\n+ logger.info(\"CALL by mov lr, pc; bx <foo> at 0x%x\", starteip)\n### DO SOMETHING?? identify new function like emucode.\nelif op.opcode == INS_ADD and op.opers[0].reg == REG_PC:\n@@ -113,7 +114,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\n#if self.verbose: print(\"BRANCH: \", hex(tgt), hex(op.va), hex(op.va))\nif tgt == op.va:\n- if self.verbose: print(\"+++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\")\n+ logger.info(\"0x%x: +++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\", op.va)\nif op.va not in self.infloops:\nself.infloops.append(op.va)\nif 'InfiniteLoops' not in vw.getVaSetNames():\n@@ -231,7 +232,7 @@ def analyzeTB(emu, op, starteip, amon):\n######################### FIXME: ADD THIS TO getBranches(emu)\n### DEBUGGING\n#raw_input(\"\\n\\n\\nPRESS ENTER TO START TB: 0x%x\" % op.va)\n- if emu.vw.verbose: print(\"\\n\\nTB at 0x%x\" % starteip)\n+ logger.debug(\"\\n\\nTB at 0x%x\", starteip)\ntsize = op.opers[0].tsize\ntbl = []\nbasereg = op.opers[0].base_reg\n@@ -240,28 +241,28 @@ def analyzeTB(emu, op, starteip, amon):\nelse:\nbase = op.opers[0].va\n- if emu.vw.verbose: print(\"\\nbase: 0x%x\" % base)\n+ logger.debug(\"\\nbase: 0x%x\", base)\nval0 = emu.readMemValue(base, tsize)\nif val0 > 0x100 + base:\n- print(\"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\")\n+ logger.debug(\"ummmm.. Houston we got a problem. first option is a long ways beyond BASE\")\nva = base\nwhile va < base + val0:\nnextoff = emu.readMemValue(va, tsize) * 2\n- if emu.vw.verbose: print(\"0x%x: -> 0x%x\" % (va, nextoff + base))\n+ logger.debug(\"0x%x: -> 0x%x\", va, nextoff + base)\nif nextoff == 0:\n- if emu.vw.verbose: print(\"Terminating TB at 0-offset\")\n+ logging.debug(\"Terminating TB at 0-offset\")\nbreak\nif nextoff > 0x500:\n- if emu.vw.verbose: print(\"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\" % nextoff)\n+ logging.debug(\"Terminating TB at LARGE - offset (may be too restrictive): 0x%x\", nextoff)\nbreak\nloc = emu.vw.getLocation(va)\nif loc != None:\n- if emu.vw.verbose: print(\"Terminating TB at Location/Reference\")\n- if emu.vw.verbose: print(\"%x, %d, %x, %r\" % loc)\n+ logger.debug(\"Terminating TB at Location/Reference\")\n+ logger.debug(\"%x, %d, %x, %r\", loc)\nbreak\ntbl.append((va, nextoff))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -38,7 +38,8 @@ def analyzePLT(vw, ssva, ssize):\ntry:\nvw.makeCode(sva)\nexcept Exception as e:\n- logger.warn('0x%x: exception: %r', sva, e)\n+ #logger.warn('0x%x: exception: %r', sva, e)\n+ logger.exception('0x%x: exception: %r', sva, e)\nltup = vw.getLocation(sva)\n@@ -157,12 +158,32 @@ def analyzePLT(vw, ssva, ssize):\nbrlen = len(branchvas)\nfirstbr, realplt = branchvas[bridx]\n- while not realplt:\n+ # roll through branches until we find one we like as the start of the real plts\n+ while bridx < brlen:\nfirstbr, realplt = branchvas[bridx]\n+ if realplt:\n+ firstva = firstbr - plt_size\n+ prevloc = vw.getLocation(firstva - 1)\n+ if prevloc is None:\n+ continue\n+ plva, plsz, pltp, pltinfo = prevloc\n+ if pltp == vivisect.LOC_OP:\n+ if pltinfo & envi.IF_NOFALL:\n+ # the previous instruction is IF_NOFALL! good.\n+ logger.debug(\"firstva found: preceeded by IF_NOFALL\")\n+ break\n+ op = vw.parseOpcode(plva)\n+ if op.mnem == 'nop':\n+ # ugly, but effective:\n+ logger.debug(\"firstva found: preceeded by 'nop'\")\n+ break\n+ else:\n+ # we've hit a non-LOC_OP... that seems like this is the start of func\n+ logger.debug(\"firstva found: preceeded by non-LOC_OP\")\n+ break\nbridx += 1\n- firstva = firstbr - plt_size\nlogger.debug('plt first entry: 0x%x\\n%r', firstva, [(hex(x), y) for x, y in branchvas])\nif bridx != 0:\n@@ -189,7 +210,7 @@ def analyzeFunction(vw, funcva):\nsegva, segsize, segname, segfname = seg\nif segname not in (\".plt\", \".plt.got\"):\n- logger.warn('0x%x: not part of \".plt\" or \".plt.got\"', funcva)\n+ logger.debug('0x%x: not part of \".plt\" or \".plt.got\"', funcva)\nreturn\nlogger.info('analyzing PLT function: 0x%x', funcva)\n@@ -287,7 +308,7 @@ def analyzeFunction(vw, funcva):\n# instead of a taint (which *should* indicate an IMPORT), we have real pointer.\n# check the location type\nif not vw.isValidPointer(opval):\n- logger.info(\"PLT: opval=0x%x - not a valid pointer... skipping\")\n+ logger.info(\"PLT: opval=0x%x - not a valid pointer... skipping\", opval)\ncontinue\nif loctup is None:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -663,7 +663,9 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nptr = sym.st_value\n# quick check to make sure we don't provide this symbol\n- if ptr:\n+ # some toolchains like to point the GOT back at it's PLT entry\n+ # that does *not* mean it's not an IMPORT\n+ if ptr and not isPLT(vw, ptr):\nlogger.info('R_ARM_JUMP_SLOT: adding Relocation 0x%x -> 0x%x (%s) ', rlva, ptr, dmglname)\nif addbase:\nvw.addRelocation(rlva, vivisect.RTYPE_BASEPTR, ptr)\n@@ -746,6 +748,16 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nexcept vivisect.InvalidLocation as e:\nlogger.warn(\"NOTE\\t%r\", e)\n+def isPLT(vw, va):\n+ '''\n+ Do a decent check to see if this va is in a PLT section\n+ '''\n+ seg = vw.getSegment(va)\n+ if seg is None:\n+ return False\n+ if seg[2].startswith('.plt'):\n+ return True\n+ return False\ndef normName(name):\n'''\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfixes and normalizing emulation, elfplt and ARM ELF relocations...
|
718,770 |
10.04.2020 20:05:20
| 14,400 |
2ab48ce076ecac72539aec9869ec45c402cfe72b
|
lots of improvements, impapi, emulation, stuff
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impapi/posix/amd64.py",
"new_path": "vivisect/impapi/posix/amd64.py",
"diff": "@@ -5,4 +5,5 @@ apitypes = {\n'HANDLE': 'unsigned long',\n}\n-api = p386.api\n+# FIXME: complete the libc import api call work and update this cleanly\n+api = {symbol: (a[0], a[1], 'sysvamd64call', a[3], a[4]) for symbol, a in p386.api.items()}\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "vivisect/impapi/posix/arm.py",
"diff": "+import vivisect.impapi.posix.i386 as p386\n+\n+apitypes = {\n+ 'DWORD': 'unsigned int',\n+ 'HANDLE': 'unsigned long',\n+ }\n+\n+# FIXME: complete the libc import api call work and update this cleanly\n+api = {symbol: (a[0], a[1], 'armcall', a[3], a[4]) for symbol, a in p386.api.items()}\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -171,6 +171,9 @@ class WorkspaceEmulator:\napi = self.getCallApi(endeip)\nrtype, rname, convname, callname, funcargs = api\ncallconv = self.getCallingConvention(convname)\n+ if callconv is None:\n+ logger.exception(\"checkCall(0x%x, 0x%x, %r): cannot get calling convention!\", starteip, endeip, op)\n+\nargv = callconv.getCallArgs(self, len(funcargs))\nret = None\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -139,6 +139,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.funcva = funcva\n+ return funcva\ndef runFunction(self, funcva, stopva=None, maxhit=None, maxloop=None, tmode=None):\n@@ -148,7 +149,8 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nto return once that location is hit.\n\"\"\"\nlogger.debug('=== emu.runFunction(0x%x, stopva=%r, maxhit=%r, maxloop=%r, tmode=%r)', funcva, stopva, maxhit, maxloop, tmode)\n- self._prep(funcva, tmode)\n+ funcva = self._prep(funcva, tmode)\n+\n# Let the current (should be base also) path know where we are starting\nvg_path.setNodeProp(self.curpath, 'bva', funcva)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
lots of improvements, impapi, emulation, stuff
|
718,770 |
10.04.2020 21:10:45
| 14,400 |
a9ca980684b47889c8f87dfb811505dce41264c7
|
impapi strips filelocal prefix if one exists.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/impapi.py",
"new_path": "vivisect/analysis/generic/impapi.py",
"diff": "@@ -9,6 +9,10 @@ logger = logging.getLogger(__name__)\ndef analyzeFunction(vw, fva):\nfname = vw.getName(fva)\n+ filename = vw.getFileByVa(fva)\n+ if fname.startswith(filename + \".\"):\n+ fname = fname[len(filename)+1:]\n+\nlogger.info(\"impapi.analyzeFunction(0x%x): name: %r\", fva, fname)\napi = vw.getImpApi(fname)\nif api == None:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
impapi strips filelocal prefix if one exists.
|
718,770 |
11.04.2020 00:00:20
| 14,400 |
6fbf80be170449b87ed8b986efd0387210275df1
|
bugfix: infinite loop on firstva being preceeded by no location
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -165,6 +165,9 @@ def analyzePLT(vw, ssva, ssize):\nfirstva = firstbr - plt_size\nprevloc = vw.getLocation(firstva - 1)\nif prevloc is None:\n+ # perhaps this is ok?\n+ logger.debug(\"NOT firstva: 0x%x - preceeded by loctup==None\", firstva)\n+ bridx += 1\ncontinue\nplva, plsz, pltp, pltinfo = prevloc\nif pltp == vivisect.LOC_OP:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: infinite loop on firstva being preceeded by no location
|
718,770 |
11.04.2020 00:07:13
| 14,400 |
9c6e6a0bd8262cb29130237f8e9709ccaf0c0edf
|
a few oddball non-ARM-specific fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/disasm.py",
"new_path": "envi/archs/i386/disasm.py",
"diff": "@@ -247,6 +247,9 @@ class i386PcRelOper(envi.Operand):\ndef getOperValue(self, op, emu=None):\nreturn op.va + op.size + self.imm\n+ def getOperAddr(self, op, emu=None):\n+ return None\n+\ndef render(self, mcanv, op, idx):\nhint = mcanv.syms.getSymHint(op.va, idx)\nif hint != None:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -1250,6 +1250,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif self.isLocation(va):\nreturn\n+ logger.debug(\"makeCode(0x%x, 0x%x)\", va, arch)\ncalls_from = self.cfctx.addCodeFlow(va, arch=arch)\ndef previewCode(self, va, arch=envi.ARCH_DEFAULT):\n@@ -1305,9 +1306,6 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif self.isFunction(va):\nreturn\n- if meta == None:\n- meta = {}\n-\nif not self.isValidPointer(va):\nraise InvalidLocation(va)\n@@ -1315,7 +1313,11 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif loc != None and loc[L_TINFO] != None and loc[L_LTYPE] == LOC_OP:\narch = loc[L_TINFO]\n- self.cfctx.addEntryPoint(va, arch=arch)\n+ realfva = self.cfctx.addEntryPoint(va, arch=arch)\n+\n+ if meta is not None:\n+ for key, val in meta.items():\n+ self.setFunctionMeta(realfva, key, val)\ndef delFunction(self, funcva):\n\"\"\"\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
a few oddball non-ARM-specific fixes
|
718,770 |
12.04.2020 01:07:11
| 14,400 |
b6a32d1fe16ce662011107bb73d49136f6602d03
|
logging of function creation
|
[
{
"change_type": "MODIFY",
"old_path": "envi/codeflow.py",
"new_path": "envi/codeflow.py",
"diff": "@@ -280,6 +280,7 @@ class CodeFlowContext(object):\nself._funcs[va] = True\ncalls_from = self.addCodeFlow(va, arch=arch)\nself._fcalls[va] = calls_from\n+ logger.debug('addEntryPoint(0x%x): calls_from: %r', va, calls_from)\n# Finally, notify the callback of a new function\nself._cb_function(va, {'CallsFrom': calls_from})\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -653,6 +653,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif ltype == LOC_OP:\n# NOTE: currently analyzePointer returns LOC_OP\n# based on function entries, lets make a func too...\n+ logger.debug('discovered new function (followPointer(0x%x))', va)\nself.makeFunction(va)\nreturn True\n@@ -837,7 +838,6 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nmaxsize = len(bytes) - size\nwhile offset + size < maxsize:\n- dbg = 0\nva = mva + offset\nloctup = self.getLocation(va)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/amd64/golang.py",
"new_path": "vivisect/analysis/amd64/golang.py",
"diff": "@@ -16,6 +16,10 @@ import envi\nimport envi.archs.amd64.disasm\nimport envi.archs.i386.disasm\n+import logging\n+\n+logger = logging.getLogger(__name__)\n+\ndef analyze(vw):\n'''\n@@ -44,6 +48,7 @@ def analyze(vw):\n# Invoke codeflow on runtime_main().\nvw.addEntryPoint(runtime_va)\n+ logger.debug('discovered runtime function: 0x%x', runtime_va)\nvw.makeFunction(runtime_va)\n# Also mark the ptr_va as a pointer to runtime_va.\n@@ -253,6 +258,7 @@ def find_golang_bblock_via_ind_jmp(vw, filename):\n# Analyze the function at the pointer if necessary.\nif not vw.isFunction(ptr_va):\n+ logger.debug('discovered new function (ptr): 0x%x', ptr_va)\nvw.makeFunction(ptr_va)\n# Expect a function with one BB, ending with an indirect jump\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/__init__.py",
"new_path": "vivisect/analysis/elf/__init__.py",
"diff": "-\n+import logging\nimport vivisect\nimport envi.bits as e_bits\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n+\ndef ffTermFptrArray(vw, va, max=100):\nret = []\nffterm = e_bits.u_maxes[vw.psize]\n@@ -17,6 +20,7 @@ def ffTermFptrArray(vw, va, max=100):\nreturn ret\ntry:\n+ logger.debug('ffTermFptrArray(): discovered new function: 0x%x', val)\nvw.makeFunction(val)\nret.append(val)\nexcept Exception, e:\n@@ -24,6 +28,7 @@ def ffTermFptrArray(vw, va, max=100):\nva += vw.psize\nreturn ret\n+\ndef analyze(vw):\n# Go through the elf sections and handle known types.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/libc_start_main.py",
"new_path": "vivisect/analysis/elf/libc_start_main.py",
"diff": "@@ -34,6 +34,7 @@ def analyzeFunction(vw, funcva):\nmainva = args[0]\nvw.addEntryPoint(mainva)\n+ logger.debug('discovered new function: 0x%x', mainva)\nvw.makeFunction(mainva)\ncurname = vw.getName(mainva)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/emucode.py",
"new_path": "vivisect/analysis/generic/emucode.py",
"diff": "@@ -10,9 +10,12 @@ import vivisect.reports as viv_rep\nfrom envi.archs.i386.opconst import *\nimport vivisect.impemu.monitor as viv_imp_monitor\n+import logging\n+\nfrom vivisect.const import *\n-verbose = False\n+logger = logging.getLogger(__name__)\n+\nclass watcher(viv_imp_monitor.EmulationMonitor):\n@@ -158,6 +161,7 @@ def analyze(vw):\ncontinue\n# XXX - RP\ntry:\n+ logger.debug('discovered new function: 0x%x', va)\nvw.makeFunction(va)\nexcept:\ncontinue\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/funcentries.py",
"new_path": "vivisect/analysis/generic/funcentries.py",
"diff": "@@ -6,12 +6,16 @@ already defined... Additionally, if the \"pointers\" generic\nmodule is run first, there is a reasonabily high likelyhood\nthat the code this finds is dead...\n\"\"\"\n+import logging\nimport traceback\nimport envi\nimport envi.memory as e_mem\nimport vivisect\n+logger = logging.getLogger(__name__)\n+\n+\ndef analyze(vw):\n\"\"\"\nAssuming that a bunch of functions have already been defined and\n@@ -42,6 +46,7 @@ def analyze(vw):\nif vw.isFunctionSignature(va):\n#print \"MATCH MATCH MATCH: 0x%.8x\" % va\n+ logger.debug('discovered new function (by signature): 0x%x', va)\nvw.makeFunction(va)\nexcept vivisect.InvalidLocation, msg:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/golang.py",
"new_path": "vivisect/analysis/i386/golang.py",
"diff": "@@ -12,9 +12,13 @@ Samples have been found with different instruction sequences for reaching the\naddress of runtime_main(); this module attempts all observed sequences.\n'''\n+import logging\n+\nimport envi\nimport envi.archs.i386.disasm\n+logger = logging.getLogger(__name__)\n+\ndef analyze(vw):\n'''\n@@ -50,6 +54,7 @@ def analyze(vw):\n# Invoke codeflow on runtime_main().\nvw.addEntryPoint(runtime_va)\n+ logger.debug('discovered runtime function: 0x%x', runtime_va)\nvw.makeFunction(runtime_va)\n# Also mark the ptr_va as a pointer to runtime_va.\n@@ -147,6 +152,7 @@ def find_golang_bblock_via_stack(vw, filename):\n# Analyze the function at the pointer if necessary.\nif not vw.isFunction(ptr_va):\n+ logger.debug('discovered new function(ptr): 0x%x', ptr_va)\nvw.makeFunction(ptr_va)\n# This function should contain the special basic block.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/cli.py",
"new_path": "vivisect/cli.py",
"diff": "@@ -6,6 +6,7 @@ import sys\nimport shlex\nimport pprint\nimport socket\n+import logging\nimport traceback\nfrom getopt import getopt\n@@ -37,6 +38,9 @@ import envi.memcanvas.renderers as e_render\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n+\nclass VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\ndef __init__(self):\n@@ -601,6 +605,7 @@ class VivCli(e_cli.EnviCli, vivisect.VivWorkspace):\nopt, optarg = opts[0]\nif opt == \"-f\":\n+ logger.debug('new function (manual-cli): 0x%x', addr)\nself.makeFunction(addr)\nelif opt == \"-c\":\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/monitor.py",
"new_path": "vivisect/impemu/monitor.py",
"diff": "import envi\nimport envi.bits as e_bits\n+import logging\n+\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n+\nBRANCH_FLAGS = envi.IF_BRANCH | envi.IF_CALL\nclass EmulationMonitor:\n\"\"\"\n@@ -174,6 +179,7 @@ class AnalysisMonitor(EmulationMonitor):\nself.vw.setComment(arg, argtype, check=True)\nif not self.vw.isLocation(arg):\nif argname == 'funcptr':\n+ logger.debug('discovered new function: 0x%x', arg)\nself.vw.makeFunction(arg)\n# FIXME make an API for this? ( the name parsing )\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "+import logging\n+\nimport envi\ntry:\nfrom PyQt5.QtWidgets import *\n@@ -27,6 +29,9 @@ from envi.threads import firethread\nfrom vqt.main import *\nfrom vivisect.const import *\n+logger = logging.getLogger(__name__)\n+\n+\n# FIXME HACK where do these really live?\nqt_horizontal = 1\nqt_vertical = 2\n@@ -177,6 +182,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\n@vq_hotkey.hotkey('viv:make:function')\ndef _hotkey_make_function(self):\nif self._canv_curva is not None:\n+ logger.debug('new function (manual): 0x%x', self._canv_curva)\nself.vw.makeFunction(self._canv_curva)\n@vq_hotkey.hotkey('viv:make:string')\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
logging of function creation
|
718,770 |
12.04.2020 01:09:09
| 14,400 |
205083e82accaf65c497640556f35b06e9769de0
|
bugfix: bxcc lr is now IF_COND and not IF_NOFALL
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -404,9 +404,19 @@ def p_misc1(opval, va): #\nopcode = INS_BX\nmnem = 'bx'\nRm = opval & 0xf\n+ cond = (opval >> 28) & 0xf\n+\nolist = ( ArmRegOper(Rm, va=va), )\n+\nif Rm == REG_LR:\n+ if cond < 0xe:\n+ iflags |= envi.IF_RET | envi.IF_COND\n+ else:\niflags |= envi.IF_RET | envi.IF_NOFALL\n+\n+ else:\n+ if cond < 0xe:\n+ iflags |= envi.IF_BRANCH | envi.IF_COND\nelse:\niflags |= envi.IF_BRANCH\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix: bxcc lr is now IF_COND and not IF_NOFALL
|
718,770 |
12.04.2020 10:18:54
| 14,400 |
0e6784b33660130df7ffce41d33814f771643b3a
|
make pointers.py obey architecture-dependent pointer-alignment rules. (really nailed some horrible bugs in ARM analysis)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -219,6 +219,9 @@ class ArchitectureModule:\ndefcall = self._plat_def_calls.get(platform)\nreturn defcall\n+ def archGetPointerAlignment(self):\n+ return 1\n+\ndef stealArchMethods(obj, archname):\n'''\nUsed by objects which are expected to inherit from an\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -84,6 +84,9 @@ class ArmModule(envi.ArchitectureModule):\ngroups.append(switch_mapbase)\nreturn groups\n+ def archGetPointerAlignment(self):\n+ return 4\n+\nclass ThumbModule(envi.ArchitectureModule):\n'''\n@@ -148,5 +151,8 @@ class ThumbModule(envi.ArchitectureModule):\nreturn tova & -2, reftype, rflags\nreturn tova, reftype, rflags\n+ def archGetPointerAlignment(self):\n+ return 4\n+\nfrom envi.archs.arm.emu import *\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -821,11 +821,12 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nif you can find pointers there... Returns a list of tuples\nwhere the tuple is (<ptr at>,<pts to>).\n\"\"\"\n+ align = self.arch.archGetPointerAlignment()\nif cache:\nret = self.getTransMeta('findPointers')\n- if ret != None:\n+ if ret is not None:\n# Filter locations added since last run...\n- ret = [ (va,x) for (va,x) in ret if self.getLocation(va) == None ]\n+ ret = [(va, x) for (va, x) in ret if self.getLocation(va) is None and not (va % align)]\nself.setTransMeta('findPointers', ret)\nreturn ret\n@@ -837,11 +838,16 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\noffset, bytes = self.getByteDef(mva)\nmaxsize = len(bytes) - size\n+ # if our memory map is not starting off aligned appropriately\n+ if offset % align:\n+ offset &= -align\n+ offset += align\n+\nwhile offset + size < maxsize:\nva = mva + offset\nloctup = self.getLocation(va)\n- if loctup != None:\n+ if loctup is not None:\noffset += loctup[L_SIZE]\ncontinue\n@@ -851,8 +857,8 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\noffset += size\ncontinue\n-\n- offset += 1\n+ offset += align\n+ offset &= -align\nif cache:\nself.setTransMeta('findPointers', ret)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
make pointers.py obey architecture-dependent pointer-alignment rules. (really nailed some horrible bugs in ARM analysis)
|
718,770 |
13.04.2020 08:27:46
| 14,400 |
6402ad51090fab81a94f2625a5e65c06a621d177
|
alignment bugfix on findPointers(), other cleanup/prettification
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -849,6 +849,9 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nloctup = self.getLocation(va)\nif loctup is not None:\noffset += loctup[L_SIZE]\n+ if offset % align:\n+ offset += align\n+ offset &= -align\ncontinue\nx = e_bits.parsebytes(bytes, offset, size, bigend=self.bigend)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/pointers.py",
"new_path": "vivisect/analysis/generic/pointers.py",
"diff": "@@ -11,8 +11,7 @@ logger = logging.getLogger(__name__)\ndef analyze(vw):\n- if vw.verbose:\n- vw.vprint('...analyzing pointers.')\n+ logger.info('...analyzing pointers.')\ndone = []\n@@ -51,8 +50,7 @@ def analyze(vw):\ndone.append((lva, tva))\nlogger.info('pointer(3): 0x%x -> 0x%x', lva, tva)\nexcept Exception:\n- if vw.verbose:\n- vw.vprint(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (lva, tva))\n+ logger.info(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (lva, tva))\n# Now, lets find likely free-hanging pointers\n@@ -64,8 +62,7 @@ def analyze(vw):\ndone.append((addr, pval))\nlogger.info('pointer(4): 0x%x -> 0x%x', addr, pval)\nexcept Exception:\n- if vw.verbose:\n- vw.vprint(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (addr, pval))\n+ logger.info(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (addr, pval))\n# Now let's see what these guys should be named (if anything)\nfor ptr, tgt in done:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impapi/posix/i386.py",
"new_path": "vivisect/impapi/posix/i386.py",
"diff": "@@ -5,6 +5,7 @@ apitypes = {\napi = {\n# libc\n+ 'plt___libc_start_main':( 'int', None, 'cdecl', '*.__libc_start_main', (('int', 'main'), ('int', 'argc'), ('int', 'argv')) ),\n'plt_main_entry':( 'int', None, 'stdcall', '*.main_entry', (('int', None), ('int', None), ('int', None)) ),\n'plt__cicos':( 'int', None, 'cdecl', '*._CIcos', () ),\n'plt__cilog':( 'int', None, 'cdecl', '*._CIlog', () ),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
alignment bugfix on findPointers(), other cleanup/prettification
|
718,770 |
14.04.2020 00:58:18
| 14,400 |
45f0a7fc606cb11d53a63cfc5694008e18aea25f
|
nearly finishing touches.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -2267,12 +2267,19 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nraise DuplicateName(oldva, va, name)\nelse:\n+ logger.debug('makeName: %r already lives at 0x%x', name, oldva)\n# tack a number on the end\nindex = 0\nnewname = \"%s_%d\" % (name, index)\n+ newoldva = self.vaByName(newname)\nwhile self.vaByName(newname) not in (None, newname):\n+ # if we run into the va we're naming, that's the name still\n+ if newoldva == va:\n+ return newname\n+ logger.debug('makeName: %r already lives at 0x%x', newname, newoldva)\nindex += 1\nnewname = \"%s_%d\" % (name, index)\n+ newoldva = self.vaByName(newname)\nname = newname\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -80,7 +80,6 @@ def addAnalysisModules(vw):\n# elfplt wants to be run before generic.entrypoints.\nvw.addAnalysisModule(\"vivisect.analysis.elf.elfplt\")\n# due to inconsistencies in plt layouts, we'll keep this as a func module as well\n- vw.addFuncAnalysisModule(\"vivisect.analysis.elf.elfplt\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.entrypoints\")\nvw.addAnalysisModule(\"vivisect.analysis.elf\")\n@@ -119,6 +118,7 @@ def addAnalysisModules(vw):\n# Find import thunks\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.elf.elfplt\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.pointers\")\nelif fmt == 'macho': # MACH-O ###################################################\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -197,7 +197,6 @@ def analyzePLT(vw, ssva, ssize):\nfor sva in range(firstva, nextseg, plt_distance):\nlogger.info('making PLT function: 0x%x', sva)\nvw.makeFunction(sva)\n- analyzeFunction(vw, sva)\nMAX_OPS = 10\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/pointers.py",
"new_path": "vivisect/analysis/generic/pointers.py",
"diff": "@@ -52,13 +52,12 @@ def analyze(vw):\nexcept Exception:\nlogger.info(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (lva, tva))\n-\n# Now, lets find likely free-hanging pointers\nfor addr, pval in vw.findPointers():\nif vw.isDeadData(pval):\ncontinue\ntry:\n- vw.followPointer(pval)\n+ vw.makePointer(addr, follow=True)\ndone.append((addr, pval))\nlogger.info('pointer(4): 0x%x -> 0x%x', addr, pval)\nexcept Exception:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
nearly finishing touches.
|
718,770 |
16.04.2020 14:02:47
| 14,400 |
441b6c16a537cc30044ba9e75dc9b212dacea183
|
finally figured out what the ELFARM spec meant about addend calculation!
cleanup (thought i committed them already)
|
[
{
"change_type": "MODIFY",
"old_path": "Elf/elf_lookup.py",
"new_path": "Elf/elf_lookup.py",
"diff": "@@ -270,6 +270,7 @@ R_ARM_PC24 = 1 # PC relative 26 bit branch */\nR_ARM_ABS32 = 2 # Direct 32 bit */\nR_ARM_REL32 = 3 # PC relative 32 bit */\nR_ARM_PC13 = 4\n+R_ARM_LDR_PC_G0 = 4 # also 4\nR_ARM_ABS16 = 5 # Direct 16 bit */\nR_ARM_ABS12 = 6 # Direct 12 bit */\nR_ARM_THM_ABS5 = 7\n@@ -278,7 +279,9 @@ R_ARM_SBREL32 = 9\nR_ARM_THM_PC22 = 10\nR_ARM_THM_PC8 = 11\nR_ARM_AMP_VCALL9 = 12\n+R_ARM_BREL_ADJ = 12 # also 12\nR_ARM_SWI24 = 13\n+R_ARM_TLS_DESC = 13 # also 13\nR_ARM_THM_SWI8 = 14\nR_ARM_XPC25 = 15\nR_ARM_THM_XPC22 = 16\n@@ -293,6 +296,10 @@ R_ARM_GOTOFF = 24 # 32 bit offset to GOT */\nR_ARM_GOTPC = 25 # 32 bit PC relative offset to GOT */\nR_ARM_GOT32 = 26 # 32 bit GOT entry */\nR_ARM_PLT32 = 27 # 32 bit PLT address */\n+R_ARM_CALL = 28\n+R_ARM_JUMP24 = 29\n+R_ARM_THM_JUMP24 = 30\n+R_ARM_BASE_ABS = 31\nR_ARM_ALU_PCREL_7_0 = 32\nR_ARM_ALU_PCREL_15_8 = 33\nR_ARM_ALU_PCREL_23_15 = 34\n@@ -308,6 +315,7 @@ R_ARM_TLS_LDM32 = 105 # PC-rel 32 bit for local dynamic thread local data */\nR_ARM_TLS_LDO32 = 106 # 32 bit offset relative to TLS block */\nR_ARM_TLS_IE32 = 107 # PC-rel 32 bit for GOT entry of static TLS block offset */\nR_ARM_TLS_LE32 = 108 # 32 bit offset relative to static TLS block */\n+R_ARM_IRELATIVE = 160\nR_ARM_RXPC25 = 249\nR_ARM_RSBREL32 = 250\nR_ARM_THM_RPC22 = 251\n@@ -316,6 +324,63 @@ R_ARM_RABS22 = 253\nR_ARM_RPC24 = 254\nR_ARM_RBASE = 255\n+R_ARMCLASS_DATA = 0\n+R_ARMCLASS_ARM = 1\n+R_ARMCLASS_THUMB16 = 2\n+R_ARMCLASS_THUMB32 = 3\n+R_ARMCLASS_MISC = 4\n+\n+r_armclasses = [\n+ (R_ARM_ABS32,\n+ R_ARM_REL32,\n+ R_ARM_ABS16,\n+ R_ARM_ABS8,\n+ R_ARM_SBREL32,\n+ R_ARM_BREL_ADJ,\n+ R_ARM_TLS_DESC,\n+ R_ARM_TLS_DTPMOD32,\n+ R_ARM_TLS_DTPOFF32,\n+ R_ARM_TLS_TPOFF32,\n+ R_ARM_GLOB_DAT,\n+ R_ARM_JUMP_SLOT,\n+ R_ARM_RELATIVE,\n+ R_ARM_GOTOFF,\n+ R_ARM_GOTPC,\n+ R_ARM_GOT32,\n+ R_ARM_IRELATIVE,\n+ ),\n+ (\n+ R_ARM_PC24,\n+ R_ARM_LDR_PC_G0,\n+ R_ARM_ABS12,\n+ R_ARM_PLT32,\n+ R_ARM_CALL,\n+ R_ARM_JUMP24,\n+ R_ARM_LDR_SBREL_11_0,\n+ R_ARM_ALU_SBREL_19_12,\n+ R_ARM_ALU_SBREL_27_20,\n+ ),\n+ (\n+ R_ARM_THM_ABS5,\n+ R_ARM_THM_PC8,\n+ ),\n+ (\n+ R_ARM_THM_PC22,\n+ R_ARM_THM_JUMP24,\n+ ),\n+ (\n+ R_ARM_NONE,\n+ R_ARM_COPY,\n+ ),\n+ ]\n+\n+\n+\n+\n+\n+\n+\n+\nR_386_NONE = 0\nR_386_32 = 1\nR_386_PC32 = 2\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -269,8 +269,7 @@ def analyzeTB(emu, op, starteip, amon):\nva += tsize\n#sys.stderr.write('.')\n- if emu.vw.verbose:\n- print(\"%s: \\n\\t\"%op.mnem + '\\n\\t'.join(['0x%x (0x%x)' % (x, base + x) for v,x in tbl]))\n+ logger.debug(\"%s: \\n\\t\"%op.mnem + '\\n\\t'.join(['0x%x (0x%x)' % (x, base + x) for v,x in tbl]))\n###\n# for workspace emulation analysis, let's check the index register for sanity.\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -550,14 +550,11 @@ def loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\nreturn fname\n-armemu = None\ndef applyRelocs(elf, vw, addbase=False, baseaddr=0):\n'''\nprocess relocations / strings (relocs use Dynamic Symbols)\n'''\n- global armemu # certain ARM relocations allow instructions to determine the relocation\n-\narch = arch_names.get(elf.e_machine)\nrelocs = elf.getRelocs()\nlogger.debug(\"reloc len: %d\", len(relocs))\n@@ -631,7 +628,11 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\n# figure out if it's negative based on the instruction!\ntry:\ntemp = vw.readMemoryPtr(rlva)\n- if temp & 0xffffff00: # it's not just a little number\n+ if rtype in Elf.r_armclasses[Elf.R_ARMCLASS_DATA] or rtype in Elf.r_armclasses[Elf.R_ARMCLASS_MISC]:\n+ # relocation points to a DATA or MISCELLANEOUS location\n+ addend = temp\n+ else:\n+ # relocation points to a CODE location (ARM, THUMB16, THUMB32)\nop = vw.parseOpcode(rlva)\nfor oper in op.opers:\nif hasattr(oper, 'val'):\n@@ -648,9 +649,6 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nhasattr(lastoper, 'pubwl') and \\\nnot (lastoper.pubwl & eaac.PUxWL_ADD):\naddend = -addend\n- else:\n- # just a small number\n- addend = temp\nexcept Exception:\nlogger.exception(\"ELF: Reloc Addend determination:\")\naddend = temp\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
finally figured out what the ELFARM spec meant about addend calculation!
cleanup (thought i committed them already)
|
718,773 |
07.05.2020 14:41:51
| 18,000 |
173850ec3d27c7c20b230b687d8fe1f14067326f
|
instrhook function analysis module for i386
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -55,6 +55,7 @@ def addAnalysisModules(vw):\n# Snap in an architecture specific emulation pass\nif arch == 'i386':\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.i386.instrhook\")\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "vivisect/analysis/i386/instrhook.py",
"diff": "+\"\"\"\n+Finds functions containing specific instructions to determine if\n+their operands should be a pointer locations.\n+This module works should be run after codeblocks analyis pass.\n+\"\"\"\n+\n+import envi\n+import vivisect.impemu.monitor as viv_imp_monitor\n+\n+verbose = False\n+\n+\n+class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\n+\n+ def __init__(self, vw, tryva):\n+ viv_imp_monitor.EmulationMonitor.__init__(self)\n+ self.vw = vw\n+ self.tryva = tryva\n+ self.hasret = False\n+ self.mndist = {}\n+ self.insn_count = 0\n+ self.lastop = None\n+ self.badcode = False\n+ self.badops = vw.arch.archGetBadOps()\n+\n+ def prehook(self, emu, op, eip):\n+ # Not sure if we need to stop emulation altogether, since we're only looking for specific instructions anyway?\n+ if op in self.badops:\n+ emu.stopEmu()\n+ raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (eip, repr(op)))\n+\n+ if op.mnem == 'stosb' or op.mnem == 'stosd':\n+ edi = emu.getRegister(envi.archs.i386.REG_EDI)\n+ if self.vw.isValidPointer(edi):\n+ self.vw.makePointer(edi, follow=True)\n+\n+\n+def analyzeFunction(vw, fva):\n+\n+ dist = vw.getFunctionMeta(fva, 'MnemDist')\n+\n+ if 'stosb' in dist or 'stosd' in dist:\n+ emu = vw.getEmulator()\n+ instrwat = instrhook_watcher(vw, fva)\n+ emu.setEmulationMonitor(instrwat)\n+ try:\n+ emu.runFunction(fva, maxhit=1)\n+ except Exception:\n+ pass\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
instrhook function analysis module for i386
|
718,773 |
11.05.2020 15:25:56
| 18,000 |
9120271fb217ac9268ce0471c761212ebd04e2b3
|
instrhook analysis module amd64
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -59,6 +59,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.amd64.instrhook\")\n# See if we got lucky and got arg/local hints from symbols\nvw.addAnalysisModule('vivisect.analysis.ms.localhints')\n@@ -99,8 +100,10 @@ def addAnalysisModules(vw):\n# Add our emulation modules\nif arch == 'i386':\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.i386.instrhook\")\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.amd64.instrhook\")\n# Find import thunks\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "vivisect/analysis/amd64/instrhook.py",
"diff": "+\"\"\"\n+Finds functions containing specific instructions to determine if\n+their operands should be a pointer locations.\n+This module should be run after codeblocks analyis pass.\n+\"\"\"\n+\n+import envi\n+import vivisect.impemu.monitor as viv_imp_monitor\n+\n+verbose = False\n+\n+\n+class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\n+\n+ def __init__(self, vw, tryva):\n+ viv_imp_monitor.EmulationMonitor.__init__(self)\n+ self.vw = vw\n+ self.tryva = tryva\n+ self.hasret = False\n+ self.mndist = {}\n+ self.insn_count = 0\n+ self.lastop = None\n+ self.badcode = False\n+ self.badops = vw.arch.archGetBadOps()\n+\n+ def prehook(self, emu, op, rip):\n+ # Not sure if we need to stop emulation altogether,\n+ # since we're only looking for specific instructions anyway?\n+ if op in self.badops:\n+ emu.stopEmu()\n+ raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (rip, repr(op)))\n+\n+ if op.mnem == 'stosb' or op.mnem == 'stosd' or op.mnem == 'stosq':\n+ rdi = emu.getRegister(envi.archs.amd64.REG_RDI)\n+ if self.vw.isValidPointer(rdi):\n+ self.vw.makePointer(rdi, follow=True)\n+\n+\n+def analyzeFunction(vw, fva):\n+\n+ dist = vw.getFunctionMeta(fva, 'MnemDist')\n+\n+ if 'stosb' in dist or 'stosd' in dist or 'stosq' in dist:\n+ emu = vw.getEmulator()\n+ instrwat = instrhook_watcher(vw, fva)\n+ emu.setEmulationMonitor(instrwat)\n+ try:\n+ emu.runFunction(fva, maxhit=1)\n+ except Exception:\n+ pass\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/instrhook.py",
"new_path": "vivisect/analysis/i386/instrhook.py",
"diff": "\"\"\"\nFinds functions containing specific instructions to determine if\ntheir operands should be a pointer locations.\n-This module works should be run after codeblocks analyis pass.\n+This module should be run after codeblocks analyis pass.\n\"\"\"\nimport envi\n@@ -24,7 +24,8 @@ class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\nself.badops = vw.arch.archGetBadOps()\ndef prehook(self, emu, op, eip):\n- # Not sure if we need to stop emulation altogether, since we're only looking for specific instructions anyway?\n+ # Not sure if we need to stop emulation altogether,\n+ # since we're only looking for specific instructions anyway?\nif op in self.badops:\nemu.stopEmu()\nraise Exception(\"Hit known BADOP at 0x%.8x %s\" % (eip, repr(op)))\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
instrhook analysis module amd64
|
718,773 |
12.05.2020 13:20:14
| 18,000 |
d8e1de76cdd9a59396f8d9e3ede2ba0920e5e400
|
Changes to instrhook func ananlysis module per code review feedback
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -7,6 +7,7 @@ for different phases of analysis on different platforms.\nimport logging\nlogger = logging.getLogger(__name__)\n+\ndef addAnalysisModules(vw):\nimport vivisect\n@@ -52,14 +53,16 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.ms.hotpatch\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.ms.msvc\")\n+ if arch in ('i386', 'amd64'):\n+ # Applies to i386 and amd64, will split it up when neccessary\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.i386.instrhook\")\n+\n# Snap in an architecture specific emulation pass\nif arch == 'i386':\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\n- vw.addFuncAnalysisModule(\"vivisect.analysis.i386.instrhook\")\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- vw.addFuncAnalysisModule(\"vivisect.analysis.amd64.instrhook\")\n# See if we got lucky and got arg/local hints from symbols\nvw.addAnalysisModule('vivisect.analysis.ms.localhints')\n@@ -97,13 +100,16 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.impapi\")\n+ if arch in ('i386', 'amd64'):\n+ # Applies to i386 and amd64, will split it up when neccessary\n+ vw.addFuncAnalysisModule(\"vivisect.analysis.i386.instrhook\")\n+\n# Add our emulation modules\nif arch == 'i386':\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\n- vw.addFuncAnalysisModule(\"vivisect.analysis.i386.instrhook\")\n+\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- vw.addFuncAnalysisModule(\"vivisect.analysis.amd64.instrhook\")\n# Find import thunks\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n"
},
{
"change_type": "DELETE",
"old_path": "vivisect/analysis/amd64/instrhook.py",
"new_path": null,
"diff": "-\"\"\"\n-Finds functions containing specific instructions to determine if\n-their operands should be a pointer locations.\n-This module should be run after codeblocks analyis pass.\n-\"\"\"\n-\n-import envi\n-import vivisect.impemu.monitor as viv_imp_monitor\n-\n-verbose = False\n-\n-\n-class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\n-\n- def __init__(self, vw, tryva):\n- viv_imp_monitor.EmulationMonitor.__init__(self)\n- self.vw = vw\n- self.tryva = tryva\n- self.hasret = False\n- self.mndist = {}\n- self.insn_count = 0\n- self.lastop = None\n- self.badcode = False\n- self.badops = vw.arch.archGetBadOps()\n-\n- def prehook(self, emu, op, rip):\n- # Not sure if we need to stop emulation altogether,\n- # since we're only looking for specific instructions anyway?\n- if op in self.badops:\n- emu.stopEmu()\n- raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (rip, repr(op)))\n-\n- if op.mnem == 'stosb' or op.mnem == 'stosd' or op.mnem == 'stosq':\n- rdi = emu.getRegister(envi.archs.amd64.REG_RDI)\n- if self.vw.isValidPointer(rdi):\n- self.vw.makePointer(rdi, follow=True)\n-\n-\n-def analyzeFunction(vw, fva):\n-\n- dist = vw.getFunctionMeta(fva, 'MnemDist')\n-\n- if 'stosb' in dist or 'stosd' in dist or 'stosq' in dist:\n- emu = vw.getEmulator()\n- instrwat = instrhook_watcher(vw, fva)\n- emu.setEmulationMonitor(instrwat)\n- try:\n- emu.runFunction(fva, maxhit=1)\n- except Exception:\n- pass\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/instrhook.py",
"new_path": "vivisect/analysis/i386/instrhook.py",
"diff": "@@ -8,6 +8,7 @@ import envi\nimport vivisect.impemu.monitor as viv_imp_monitor\nverbose = False\n+STOS = ('stosb', 'stosw', 'stosd', 'stosq')\nclass instrhook_watcher (viv_imp_monitor.EmulationMonitor):\n@@ -22,25 +23,33 @@ class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\nself.lastop = None\nself.badcode = False\nself.badops = vw.arch.archGetBadOps()\n+ self.arch = vw.getMeta('Architecture')\ndef prehook(self, emu, op, eip):\n- # Not sure if we need to stop emulation altogether,\n- # since we're only looking for specific instructions anyway?\nif op in self.badops:\nemu.stopEmu()\nraise Exception(\"Hit known BADOP at 0x%.8x %s\" % (eip, repr(op)))\n- if op.mnem == 'stosb' or op.mnem == 'stosd':\n- edi = emu.getRegister(envi.archs.i386.REG_EDI)\n- if self.vw.isValidPointer(edi):\n- self.vw.makePointer(edi, follow=True)\n+ if op.mnem in STOS:\n+ if self.arch == 'i386':\n+ reg = emu.getRegister(envi.archs.i386.REG_EDI)\n+ elif self.arch == 'amd64':\n+ reg = emu.getRegister(envi.archs.amd64.REG_RDI)\n+ if self.vw.isValidPointer(reg):\n+ self.vw.makePointer(reg, follow=True)\ndef analyzeFunction(vw, fva):\n+ emulate = False\ndist = vw.getFunctionMeta(fva, 'MnemDist')\n- if 'stosb' in dist or 'stosd' in dist:\n+ for s in STOS:\n+ if s in dist:\n+ emulate = True\n+ break\n+\n+ if emulate:\nemu = vw.getEmulator()\ninstrwat = instrhook_watcher(vw, fva)\nemu.setEmulationMonitor(instrwat)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Changes to instrhook func ananlysis module per code review feedback
|
718,770 |
31.05.2020 23:45:43
| 14,400 |
7a20a960b0e586a5ea553db8e52b7b5d373679a9
|
some changes recommended by
|
[
{
"change_type": "MODIFY",
"old_path": "envi/__init__.py",
"new_path": "envi/__init__.py",
"diff": "@@ -53,6 +53,8 @@ IF_RET = 0x10 # Set if this instruction terminates a procedure\nIF_COND = 0x20 # Set if this instruction is conditional\nIF_REPEAT = 0x40 # set if this instruction repeats (including 0 times)\n+IF_BRANCH_COND = IF_COND | IF_BRANCH\n+\n# Branch flags (flags returned by the getBranches() method on an opcode)\nBR_PROC = 1<<0 # The branch target is a procedure (call <foo>)\nBR_COND = 1<<1 # The branch target is conditional (jz <foo>)\n@@ -164,6 +166,14 @@ class ArchitectureModule:\nThis hook allows an architecture to correct VA and Architecture, such\nas is necessary for ARM/Thumb.\n+\n+ \"info\" should be a dictionary with the {'arch': ARCH_FOO}\n+\n+ eg. for ARM, the ARM disassembler would hand in\n+ {'arch': ARCH_ARMV7}\n+\n+ and if va is odd, that architecture's implementation would return\n+ (va & -2), {'arch': ARCH_THUMB}\n'''\nreturn va, info\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -5286,7 +5286,7 @@ class ArmDisasm:\ndef getEndian(self):\n'''\n- set endianness for the architecture.\n+ get endianness for the architecture.\nENDIAN_LSB and ENDIAN_MSB are appropriate return values\n'''\nreturn self.endian\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/__init__.py",
"new_path": "vivisect/analysis/__init__.py",
"diff": "@@ -7,6 +7,9 @@ for different phases of analysis on different platforms.\nimport logging\nlogger = logging.getLogger(__name__)\n+ARM_ARCHS = ('arm', 'thumb', 'thumb16')\n+\n+\ndef addAnalysisModules(vw):\nimport vivisect\n@@ -33,7 +36,7 @@ def addAnalysisModules(vw):\nvw.addImpApi('windows', 'amd64')\nvw.addStructureModule('ntdll', 'vstruct.defs.windows.win_6_1_amd64.ntdll')\n- elif arch in ('arm', 'thumb', 'thumb16'):\n+ elif arch in ARM_ARCHS:\nvw.addImpApi('windows','arm')\nvw.addFuncAnalysisModule('vivisect.analysis.arm.renaming')\n@@ -63,7 +66,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch in ('arm', 'thumb', 'thumb16'):\n+ elif arch in ARM_ARCHS:\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n# See if we got lucky and got arg/local hints from symbols\n@@ -79,7 +82,6 @@ def addAnalysisModules(vw):\n# elfplt wants to be run before generic.entrypoints.\nvw.addAnalysisModule(\"vivisect.analysis.elf.elfplt\")\n- # due to inconsistencies in plt layouts, we'll keep this as a func module as well\nvw.addAnalysisModule(\"vivisect.analysis.generic.entrypoints\")\nvw.addAnalysisModule(\"vivisect.analysis.elf\")\n@@ -92,10 +94,9 @@ def addAnalysisModules(vw):\n# add va set for tracking thunk_bx function(s)\nvw.addVaSet('thunk_bx', ( ('fva', vivisect.VASET_ADDRESS), ) )\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.thunk_bx\")\n- elif arch in ('arm', 'thumb', 'thumb16'):\n+ elif arch in ARM_ARCHS:\nvw.addVaSet('thunk_reg', ( ('fva', vivisect.VASET_ADDRESS), ('reg', vivisect.VASET_INTEGER), ))\nvw.addFuncAnalysisModule('vivisect.analysis.arm.thunk_reg')\n- #vw.addFuncAnalysisModule('vivisect.analysis.arm.elfplt')\nvw.addFuncAnalysisModule('vivisect.analysis.arm.renaming')\nvw.addAnalysisModule(\"vivisect.analysis.generic.funcentries\")\n@@ -113,11 +114,12 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.i386.calling\")\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch in ('arm', 'thumb', 'thumb16'):\n+ elif arch in ARM_ARCHS:\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\n# Find import thunks\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.thunks\")\n+ # due to inconsistencies in plt layouts, we'll keep this as a func module as well\nvw.addFuncAnalysisModule(\"vivisect.analysis.elf.elfplt\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.pointers\")\n@@ -143,7 +145,7 @@ def addAnalysisModules(vw):\nelif arch == 'amd64':\nvw.addFuncAnalysisModule(\"vivisect.analysis.amd64.emulation\")\n- elif arch in ('arm', 'thumb', 'thumb16'):\n+ elif arch in ARM_ARCHS:\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule('vivisect.analysis.arm.renaming')\n@@ -160,7 +162,7 @@ def addAnalysisModules(vw):\nvw.addFuncAnalysisModule(\"vivisect.analysis.generic.codeblocks\")\n- if arch in ('arm', 'thumb', 'thumb16'):\n+ if arch in ARM_ARCHS:\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule('vivisect.analysis.arm.renaming')\n@@ -175,7 +177,7 @@ def addAnalysisModules(vw):\n#vw.addAnalysisModule(\"vivisect.analysis.generic.pointertables\")\nvw.addAnalysisModule(\"vivisect.analysis.generic.emucode\")\n- if arch in ('arm', 'thumb', 'thumb16'):\n+ if arch in ARM_ARCHS:\nvw.addFuncAnalysisModule(\"vivisect.analysis.arm.emulation\")\nvw.addFuncAnalysisModule('vivisect.analysis.arm.renaming')\n"
},
{
"change_type": "DELETE",
"old_path": "vivisect/analysis/arm/elfplt.py",
"new_path": null,
"diff": "-\"\"\"\n-If a \"function\" is in the plt it's a wrapper for something in the GOT.\n-Make that apparent.\n-\"\"\"\n-\n-import envi\n-import vivisect\n-\n-import logging\n-logger = logging.getLogger(__name__)\n-\n-def analyze(vw):\n- \"\"\"\n- Do simple linear disassembly of the .plt section if present.\n- \"\"\"\n- return\n- for sva,ssize,sname,sfname in vw.getSegments():\n- if sname != \".plt\":\n- continue\n- nextva = sva + ssize\n- while sva < nextva:\n- vw.makeCode(sva)\n- ltup = vw.getLocation(sva)\n- sva += ltup[vivisect.L_SIZE]\n-\n-\n-MAX_INSTR_COUNT = 3\n-\n-def analyzeFunction(vw, funcva):\n- '''\n- Function Analysis Module. This gets run on all functions, so we need to identify that we're\n- in a PLT quickly.\n-\n- Emulates the first few instructions of each PLT function to determine the correct offset\n- into the Global Offset Table. Then tags names, etc...\n- '''\n- seg = vw.getSegment(funcva)\n- if seg == None:\n- logger.debug(\"no segment for funcva 0x%x\", funcva)\n- return\n-\n- segva, segsize, segname, segfname = seg\n-\n- if segname not in (\".plt\", \".plt.got\"):\n- logger.debug(\"not in PLT segment for funcva 0x%x (%r)\", funcva, segname)\n- return\n-\n-\n- emu = vw.getEmulator()\n- emu.setProgramCounter(funcva)\n- offset = 0\n- branch = False\n- for cnt in range(MAX_INSTR_COUNT):\n- op = emu.parseOpcode(funcva + offset)\n- if op.iflags & envi.IF_BRANCH == 0:\n- emu.executeOpcode(op)\n- offset += len(op)\n- continue\n- branch = True\n- break\n-\n- if not branch:\n- logger.debug(\"no branch found for funcva 0x%x (after %r instrs)\", funcva, cnt)\n- return\n-\n- loctup = None\n- oper1 = op.opers[1]\n- opval = oper1.getOperAddr(op, emu=emu)\n- loctup = vw.getLocation(opval)\n-\n- if loctup == None:\n- logger.debug(\"no location found for funcva 0x%x (%r)\", funcva, oper1)\n- return\n-\n- if loctup[vivisect.L_LTYPE] != vivisect.LOC_IMPORT:\n- logger.debug(\"0x%x: %r != %r (LOC_IMPORT)\", funcva, loctup[vivisect.L_LTYPE], vivisect.LOC_IMPORT)\n-\n- vw.addXref(op.va, opval, vivisect.REF_DATA)\n- tva = vw.readMemoryPtr(opval)\n- if vw.isValidPointer(tva):\n- vw.addXref(op.va, tva, vivisect.REF_CODE)\n-\n- gotname = vw.getName(opval)\n- vw.makeFunctionThunk(funcva, gotname)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -86,13 +86,14 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nif starteip - self.last_lr_pc <= 4:\n# this is a call. the compiler updated lr\nlogger.info(\"CALL by mov lr, pc; bx <foo> at 0x%x\", starteip)\n- ### DO SOMETHING?? identify new function like emucode.\n+ tgtva = op.opers[-1].getOperValue(op)\n+ self.vw.makeFunction(tgtva)\nelif op.opcode == INS_ADD and op.opers[0].reg == REG_PC:\n# simple branch code\nif emu.vw.getVaSetRow('SwitchCases', op.va) == None:\nbase, tbl = analyzeADDPC(emu, op, starteip, self)\n- if not None in (base, tbl):\n+ if None not in (base, tbl):\ncount = len(tbl)\nself.switchcases += 1\nemu.vw.setVaSetRow('SwitchCases', (op.va, op.va, count) )\n@@ -101,18 +102,15 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\n# simple branch code\nif emu.vw.getVaSetRow('SwitchCases', op.va) == None:\nbase, tbl = analyzeSUBPC(emu, op, starteip, self)\n- if not None in (base, tbl):\n+ if None not in (base, tbl):\ncount = len(tbl)\nself.switchcases += 1\nemu.vw.setVaSetRow('SwitchCases', (op.va, op.va, count) )\n-\nif op.iflags & envi.IF_BRANCH:\ntry:\ntgt = op.getOperValue(0, emu)\n- #if self.verbose: print(\"BRANCH: \", hex(tgt), hex(op.va), hex(op.va))\n-\nif tgt == op.va:\nlogger.info(\"0x%x: +++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\", op.va)\nif op.va not in self.infloops:\n@@ -121,12 +119,12 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nvw.addVaSet('InfiniteLoops', (('va', vivisect.VASET_ADDRESS, 'function', vivisect.VASET_STRING)))\nself.vw.setVaSetRow('InfiniteLoops', (op.va, self.fva))\n- except Exception, e:\n- # FIXME: make raise Exception?\n+ except Exception as e:\n+ emumon.logAnomaly(emu, fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\nlogger.info(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\n- except Exception, e:\n- # FIXME: make raise Exception?\n+ except Exception as e:\n+ emumon.logAnomaly(emu, fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\nlogger.exception(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\n@@ -142,14 +140,16 @@ argnames = {\n3: ('r3', 3),\n}\n+\ndef archargname(idx):\nret = argnames.get(idx)\n- if ret == None:\n+ if ret is None:\nname = 'arg%d' % idx\nelse:\nname, idx = ret\nreturn name\n+\ndef buildFunctionApi(vw, fva, emu, emumon):\nargc = 0\nfuncargs = []\n@@ -170,12 +170,13 @@ def buildFunctionApi(vw, fva, emu, emumon):\nelse:\nargc = targc\n- funcargs = [ ('int',archargname(i)) for i in xrange(argc) ]\n+ funcargs = [ ('int',archargname(i)) for i in range(argc) ]\napi = ('int',None,callconv,None,funcargs)\nvw.setFunctionApi(fva, api)\nreturn api\n+\ndef analyzeFunction(vw, fva):\n#print(\"++ Arm EMU fmod: 0x%x\" % fva)\nemu = vw.getEmulator()\n@@ -211,7 +212,7 @@ def analyzeFunction(vw, fva):\nbaseoff = cc.getStackArgOffset(emu, argc)\n# Register our stack args as function locals\n- for i in xrange( stcount ):\n+ for i in range(stcount):\nvw.setFunctionLocal(fva, baseoff + ( i * 4 ), LSYM_FARG, i+stackidx)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/thunk_reg.py",
"new_path": "vivisect/analysis/arm/thunk_reg.py",
"diff": "@@ -72,7 +72,7 @@ def analyzeFunction(vw, fva):\nif newtmode != tmode:\nemu.setFlag(PSR_T_bit, tmode)\n- if op.iflags & (envi.IF_BRANCH | envi.IF_COND) == (envi.IF_BRANCH | envi.IF_COND):\n+ if op.iflags & (envi.IF_BRANCH_COND) == (envi.IF_BRANCH_COND):\nbreak\nif not len(op.opers):\n@@ -110,9 +110,7 @@ def analyzeFunction(vw, fva):\ntry:\nemu.runFunction(fva, maxhit=1)\nexcept:\n- logger.warn(\"Error emulating function 0x%x\\n\\t%r\", fva, emumon.emuanom)\n-\n- if vw.verbose: sys.stderr.write('=')\n+ logger.exception(\"Error emulating function 0x%x\\n\\t%r\", fva, emumon.emuanom)\n# now roll through tracked references and make xrefs/comments\nitems = emumon.tracker.items()\n@@ -144,7 +142,7 @@ def analyzeFunction(vw, fva):\ncmt = \"0x%x: %s\" % (tgt, vw.reprPointer(tgt))\nif curcmt is None or not len(curcmt):\nvw.setComment(va, cmt)\n- elif not cmt in curcmt:\n+ elif cmt not in curcmt:\ncmt = \"0x%x: %s ;\\n %s\" % (tgt, vw.reprPointer(tgt), curcmt)\nvw.setComment(va, cmt)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
some changes recommended by @rakuyo
|
718,770 |
06.06.2020 00:50:13
| 14,400 |
c798af7ec62ba18e32ac6f40eb9631672046048d
|
thumb disasm updates
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -339,7 +339,7 @@ def branch_misc(va, val, val2): # bl and misc control\nif not (imod or m):\n# hint\n- mnem = \"CPS Hint... fix me\"\n+ mnem = \"CPS Hint\"\nif imod & 2:\nopers = [\n@@ -358,20 +358,17 @@ def branch_misc(va, val, val2): # bl and misc control\nreturn COND_AL, opcode, mnem, opers, flags, 0\n- #elif op == 0b0111011:\n- # raise Exception(\"FIXME: Misc control instrs p A6-235\") should be covered by \"op & 0b111 == 0b011\"\n-\nelif op == 0b0111100:\nraise Exception(\"FIXME: BXJ p A8-352\")\n- #elif op == 0b0111101: # subs PC, LR, #imm (see special case ERET above)... unnecessary?\n- # imm8 = val2 & 0xff\n- # opers = (\n- # ArmRegOper(REG_PC),\n- # ArmRegOper(REG_LR),\n- # ArmImmOper(imm8),\n- # )\n- # return COND_AL, None, 'sub', opers, IF_PSR_S, 0\n+ elif op == 0b0111101: # subs PC, LR, #imm (see special case ERET above)...\n+ imm8 = val2 & 0xff\n+ opers = (\n+ ArmRegOper(REG_PC),\n+ ArmRegOper(REG_LR),\n+ ArmImmOper(imm8),\n+ )\n+ return COND_AL, None, 'sub', opers, IF_PSR_S, 0\nelif op == 0b0111110:\nRd = (val2 >> 8) & 0xf\n@@ -1551,7 +1548,7 @@ def coproc_simd_32(va, val1, val2):\n#print \"coproc_simd_32\"\n### return armd.doDecode(va, val32, 'THUMB2', 0) lol! trying to leverage Arm code that just aint there! CONSIDER: finish this, then move it into ARM, then call there....\n# FIXME: coalesce ARM/Thumb32 decoding schemes so they can use the same decoders (ie. they return the same things: opcode, mnem, olist, flags)\n- # FIXME: MANY THUMB2 instruction encodings model their \"Always Execute\" ARM equivalents.\n+ # NOTE: MANY THUMB2 instruction encodings model their \"Always Execute\" ARM equivalents.\ncoproc = (val2>>8) & 0xf\nop1 = (val1>>4) & 0x3f\nop = (val2>>4) & 1\n@@ -1561,7 +1558,6 @@ def coproc_simd_32(va, val1, val2):\n#print bin(coproc), bin(op1),bin(op)\nif op1 & 0b110000 == 0b110000:\n- print(\"AdvSIMD from CoprocSIMD. How did we get here? This should be impossible!\")\nreturn adv_simd_32(va, val1, val2)\nif op1 & 0b111110 == 0:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
thumb disasm updates
|
718,770 |
06.06.2020 12:49:23
| 14,400 |
7d39535797201c596fd020075e46d43c1893220b
|
yay! advsimd/coproc/fp done.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -1669,7 +1669,6 @@ def coproc_simd_32(va, val1, val2):\nelse:\n# coproc = 0b101x - ARM7A/M p251\n- # FIXME: REMOVE WHEN DONE IMPLEMENTING\nopcode = 0\niflags = 0\nopers = []\n@@ -1685,10 +1684,9 @@ def coproc_simd_32(va, val1, val2):\nelif op1 & 0b111110 == 0b000100:\n# adv simd fp (A7-277)\n- logger.warn(\"AdvSIMD from CoprocSIMD... do we actually end up here?\")\n# 64-bit transfers between ARM core and extension registers on page A7-279\n- return adv_simd_32(va, val1, val2)\n+ return adv_xfer_arm_ext_64(va, val1, val2)\nelif op1 & 0b100000 == 0 and not (op1 & 0b111010 == 0):\n# extension register load/store instructions A7-274\n@@ -1697,21 +1695,13 @@ def coproc_simd_32(va, val1, val2):\n# adv simd fp (a7-272)\ntmop1 = op1 & 0b11011\n- if op1 & 0b11110 == 0b00100:\n- # 64 bit transverse between ARM core and extension registers (a7-277)\n- bytez = struct.pack(\"<HH\", val1, val2)\n- raise envi.InvalidInstruction( #FIXME!!!!\n- mesg=\"IMPLEMENT: 64-bit transverse between ARM core and extension registers\",\n- bytez=bytez, va=va)\n-\n-\n- # EXPECT TO NOT REACH HERE UNLESS WE MEAN BUSINESS. otherwise this needs to be in an else:\nif (op1 & 0b11010) in (0b10, 0b11010):\nbytez = struct.pack(\"<HH\", val1, val2)\nraise InvalidInstruction(mesg=\"INVALID ENCODING\", bytez=bytez, va=va)\nl = op1 & 1 # vldm or vstm\nindiv = (op1 & 0b10010) == 0b10000\n+\n# writeback should be handled by operand\nimm8 = (val2 & 0xff) >> 1\nimm32 = imm8 << 3\n@@ -1766,7 +1756,7 @@ def coproc_simd_32(va, val1, val2):\n)\nelse:\nbytez = struct.pack(\"<HH\", val1, val2)\n- raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_32\", bytez=bytez, va=va)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: coproc_advsimd_fp\", bytez=bytez, va=va)\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n@@ -1905,6 +1895,81 @@ def adv_xfer_arm_ext_32(va, val1, val2):\nreturn COND_AL, opcode, mnem, opers, iflags, simdflags\n+def adv_xfer_arm_ext_64(va, val1, val2):\n+ # VMOV instruction decoding\n+ # except: for coprocs 10 and 11. MRRC and MCRR\n+ val = (val1 << 16) | val2\n+\n+ if (val1 >> 12) & 0xf == 0b1111:\n+ bytez = struct.pack(\"<I\", val)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_64: cannot be T==1 in Thumb, or cond=0b1111 in ARM\", bytez=bytez, va=va)\n+\n+ op = (val2 >> 4) & 0xf\n+ C = (val2 >> 8) & 1\n+\n+ if op & 0b1101 == 1:\n+ # the decoding for both directions is mostly the same\n+ op = (val1 >> 4) & 1\n+\n+ rt2 = val1 & 0xf\n+ rt = (val2 >> 12) & 0xf\n+\n+ vm = val2 & 0xf\n+ m = (val2 >> 5) & 1\n+ Vm = (vm << 1) | m\n+\n+ if C == 0:\n+ # 2xARM <-> 2xSinglePrecision registers\n+ Vm = rctx.getRegisterIndex('s%d' % Vm)\n+\n+ if op == 0:\n+ # from ARM to Ext regs\n+ opers = (\n+ ArmRegOper(Vm, va),\n+ ArmRegOper(Vm + 1, va),\n+ ArmRegOper(rt, va),\n+ ArmRegOper(rt2, va),\n+ )\n+\n+ else:\n+ # from Ext to ARM regs\n+ opers = (\n+ ArmRegOper(rt, va),\n+ ArmRegOper(rt2, va),\n+ ArmRegOper(Vm, va),\n+ ArmRegOper(Vm + 1, va),\n+ )\n+\n+ else:\n+ # 2xARM <-> 1xDoublePrecision register\n+ Vm = rctx.getRegisterIndex('d%d' % Vm)\n+\n+ if op == 0:\n+ # from ARM to Ext regs\n+ opers = (\n+ ArmRegOper(Vm, va),\n+ ArmRegOper(rt, va),\n+ ArmRegOper(rt2, va),\n+ )\n+\n+ else:\n+ # from Ext to ARM regs\n+ opers = (\n+ ArmRegOper(rt, va),\n+ ArmRegOper(rt2, va),\n+ ArmRegOper(Vm, va),\n+ )\n+\n+ else:\n+ bytez = struct.pack(\"<I\", val)\n+ raise InvalidInstruction(mesg=\"INVALID ENCODING: adv_xfer_arm_ext_64: op is not '00x1'\", bytez=bytez, va=va)\n+\n+ '''\n+ In [8]: ad.disasm('345b46ec'.decode('hex'), 0, 0)\n+ Out[8]: vmov d9, r5, r6\n+ '''\n+ return COND_AL, INS_VMOV, 'vmov', opers, 0, 0\n+\nbcc_ops = {\n0b0000: (INS_BCC,'beq', envi.IF_COND, COND_EQ),\n0b0001: (INS_BCC,'bne', envi.IF_COND, COND_NE),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
yay! advsimd/coproc/fp done.
|
718,770 |
07.06.2020 22:45:43
| 14,400 |
a118f2751f0e8791cd404193a1912e562901b0d6
|
logging the exception
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/pointers.py",
"new_path": "vivisect/analysis/generic/pointers.py",
"diff": "@@ -50,7 +50,7 @@ def analyze(vw):\ndone.append((lva, tva))\nlogger.info('pointer(3): 0x%x -> 0x%x', lva, tva)\nexcept Exception:\n- logger.info(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (lva, tva))\n+ logger.exception(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (lva, tva))\n# Now, lets find likely free-hanging pointers\nfor addr, pval in vw.findPointers():\n@@ -61,7 +61,7 @@ def analyze(vw):\ndone.append((addr, pval))\nlogger.info('pointer(4): 0x%x -> 0x%x', addr, pval)\nexcept Exception:\n- logger.info(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (addr, pval))\n+ logger.exception(\"followPointer() failed for 0x%.8x (pval: 0x%.8x)\" % (addr, pval))\n# Now let's see what these guys should be named (if anything)\nfor ptr, tgt in done:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
logging the exception
|
718,770 |
07.06.2020 23:14:27
| 14,400 |
dfca9ef5c2d2ca2362d9be6fe6d5d4d612dcb9ef
|
silent emulation exception mode
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -983,6 +983,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nreturn False\nself.iscode[va] = True\nemu = self.getEmulator()\n+ emu.setMeta('silent', True)\nwat = v_emucode.watcher(self, va)\nemu.setEmulationMonitor(wat)\ntry:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -331,6 +331,7 @@ class WorkspaceEmulator:\ntry:\nself.emumon.prehook(self, op, starteip)\nexcept Exception as e:\n+ if not self.getMeta('silent'):\nlogger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon prehook)\", funcva, starteip, op, e)\n@@ -347,6 +348,7 @@ class WorkspaceEmulator:\ntry:\nself.emumon.posthook(self, op, endeip)\nexcept Exception as e:\n+ if not self.getMeta('silent'):\nlogger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon posthook)\", funcva, starteip, op, e)\nif self.emustop:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -207,7 +207,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.emumon.prehook(self, op, starteip)\nexcept Exception as e:\nif not self.getMeta('silent'):\n- logger.warn(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon prehook)\", funcva, starteip, op, e)\n+ logger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon prehook)\", funcva, starteip, op, e)\nif self.emustop:\nreturn\n@@ -223,7 +223,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.emumon.posthook(self, op, endeip)\nexcept Exception as e:\nif not self.getMeta('silent'):\n- logger.warn(\"funcva: 0x%x opva: 0x%x: %r %r (in emumon posthook)\", funcva, starteip, op, e)\n+ logger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon posthook)\", funcva, starteip, op, e)\nif self.emustop:\nreturn\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
silent emulation exception mode
|
718,770 |
07.06.2020 23:24:37
| 14,400 |
de00dba215425d2956000830c351952e4e5c30d8
|
ELF aarch64 removal
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -114,7 +114,6 @@ arch_names = {\nElf.EM_386:'i386',\nElf.EM_X86_64:'amd64',\nElf.EM_MSP430:'msp430',\n- Elf.EM_ARM_AARCH64:'aarch64',\n}\narchcalls = {\n@@ -123,7 +122,6 @@ archcalls = {\n'arm':'armcall',\n'thumb':'armcall',\n'thumb16':'armcall',\n- 'aarch64':'a64call',\n}\ndef loadElfIntoWorkspace(vw, elf, filename=None, baseaddr=None):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
ELF aarch64 removal
|
718,770 |
08.06.2020 10:08:53
| 14,400 |
e53247955594387cd2fbb0202e9eb4f87ae217e9
|
lots of minor fixes and tweaks per code review
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/__init__.py",
"new_path": "envi/archs/arm/__init__.py",
"diff": "@@ -29,7 +29,6 @@ class ArmModule(envi.ArchitectureModule):\ndef archGetBreakInstr(self):\nraise Exception (\"weird... what are you trying to do here? ARM has a complex breakpoint instruction\")\n- return\ndef archGetNopInstr(self):\nreturn ('\\x00\\x00\\x60\\xe3', '\\xe3\\x60\\x00\\x00')[self._endian] #FIXME: this is only ARM mode. this arch mod should cover both. the ENVI architecture doesn't support this model yet.\n@@ -111,7 +110,6 @@ class ThumbModule(envi.ArchitectureModule):\ndef archGetBreakInstr(self):\nraise Exception (\"weird... what are you trying to do here? ARM has a complex breakpoint instruction\")\n- return\ndef archGetNopInstr(self):\nreturn ('\\xc0\\x46', '\\x46\\xc0')[self._endian]\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -98,16 +98,16 @@ iencmul_codes = {\n#0b011101010011: (\"smmulr\", (0,4,2), 0),\n}\n-def sh_lsl(num, shval, size=4):\n+def sh_lsl(num, shval, size=4, emu=None):\nreturn (num&e_bits.u_maxes[size]) << shval\n-def sh_lsr(num, shval, size=4):\n+def sh_lsr(num, shval, size=4, emu=None):\nreturn (num&e_bits.u_maxes[size]) >> shval\n-def sh_asr(num, shval, size=4):\n+def sh_asr(num, shval, size=4, emu=None):\nreturn num >> shval\n-def sh_ror(num, shval, size=4):\n+def sh_ror(num, shval, size=4, emu=None):\nreturn ((num >> shval) | (num << ((8*size)-shval))) & e_bits.u_maxes[size]\ndef sh_rrx(num, shval, size=4, emu=None):\n@@ -115,9 +115,9 @@ def sh_rrx(num, shval, size=4, emu=None):\nnewC = num & 1\nif emu is not None:\n- flags = emu.getFlags()\n- oldC = (flags>>PSR_C) & 1\n- emu.setFlags(flags & PSR_C_mask | newC)\n+ oldC = emu.getFlag(PSR_C_bit)\n+ if emu.getMeta('forrealz', False):\n+ emu.setFlag(PSR_C_bit, newC)\nelse:\n# total hack! should we just bomb here without an emu?\noldC = 0\n@@ -4196,7 +4196,7 @@ class ArmRegShiftRegOper(ArmOperand):\ndef getOperValue(self, op, emu=None, codeflow=False):\nif emu is None:\nreturn None\n- return shifters[self.shtype](emu.getRegister(self.reg), emu.getRegister(self.shreg))\n+ return shifters[self.shtype](emu.getRegister(self.reg), emu.getRegister(self.shreg), emu=emu)\ndef render(self, mcanv, op, idx):\nrname = arm_regs[self.reg][0]\n@@ -4244,11 +4244,11 @@ class ArmRegShiftImmOper(ArmOperand):\ndef getOperValue(self, op, emu=None, codeflow=False):\nif self.reg == REG_PC:\n- return shifters[self.shtype](self.va, self.shimm)\n+ return shifters[self.shtype](self.va, self.shimm, emu=emu)\nif emu is None:\nreturn None\n- return shifters[self.shtype](emu.getRegister(self.reg), self.shimm)\n+ return shifters[self.shtype](emu.getRegister(self.reg), self.shimm, emu=emu)\ndef render(self, mcanv, op, idx):\nrname = arm_regs[self.reg][0]\n@@ -4304,7 +4304,7 @@ class ArmImmOper(ArmOperand):\nreturn True\ndef getOperValue(self, op, emu=None, codeflow=False):\n- return shifters[self.shtype](self.val, self.shval, self.size)\n+ return shifters[self.shtype](self.val, self.shval, self.size, emu=emu)\ndef render(self, mcanv, op, idx):\nval = self.getOperValue(op)\n@@ -4426,7 +4426,7 @@ class ArmScaledOffsetOper(ArmOperand):\nbase = self._getOperBase(emu)\npom = (-1, 1)[(self.pubwl>>3)&1]\n- addval = shifters[self.shtype]( emu.getRegister( self.offset_reg ), self.shval )\n+ addval = shifters[self.shtype](emu.getRegister(self.offset_reg), self.shval, emu=emu)\n# if U==0, subtract\naddval *= pom\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -133,11 +133,6 @@ conditionals = [\ntop_bits_32 = [(e_bits.u_maxes[4] ^ ((e_bits.u_maxes[4]>>x))) for x in range(4*8)]\n-LSB_FMT = [0, 'B', '<H', 0, '<I', 0, 0, 0, '<Q',]\n-MSB_FMT = [0, 'B', '>H', 0, '>I', 0, 0, 0, '>Q',]\n-LSB_FMT_SIGNED = [0, 'b', '<h', 0, '<i', 0, 0, 0, '<q',]\n-MSB_FMT_SIGNED = [0, 'b', '>h', 0, '>i', 0, 0, 0, '>q',]\n-\n# SIMD support\nOP_F16 = 1\nOP_F32 = 2\n@@ -215,13 +210,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif len(bytes) != size:\nraise Exception(\"Read Gave Wrong Length At 0x%.8x (va: 0x%.8x wanted %d got %d)\" % (self.getProgramCounter(),addr, size, len(bytes)))\n- endian_fmt = (LSB_FMT, MSB_FMT)[self.getEndian()]\n- return struct.unpack(endian_fmt[size], bytes)[0]\n+ fmtstr = e_bits.getFormat(size, self.getEndian())\n+ return struct.unpack(fmtstr, bytes)[0]\ndef writeMemValue(self, addr, value, size):\n- endian_fmt = (LSB_FMT, MSB_FMT)[self.getEndian()]\n+ fmtstr = e_bits.getFormat(size, self.getEndian())\nmask = e_bits.u_maxes[size]\n- bytes = struct.pack(endian_fmt[size], (value & mask))\n+ bytes = struct.pack(fmtstr, (value & mask))\nself.writeMemory(addr, bytes)\ndef readMemSignedValue(self, addr, size):\n@@ -231,8 +226,8 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif len(bytes) != size:\nraise Exception(\"Read Gave Wrong Length At 0x%.8x (va: 0x%.8x wanted %d got %d)\" % (self.getProgramCounter(),addr, size, len(bytes)))\n- endian_fmt = (LSB_FMT_SIGNED, MSB_FMT_SIGNED)[self.getEndian()]\n- return struct.unpack(endian_fmt[size], bytes)[0]\n+ fmtstr = e_bits.getFormat(size, self.getEndian(), signed=True)\n+ return struct.unpack(fmtstr, bytes)[0]\ndef parseOpcode(self, va, arch=envi.ARCH_DEFAULT):\n'''\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -7,9 +7,6 @@ from envi import InvalidInstruction\nfrom envi.archs.arm.disasm import *\narmd = ArmDisasm()\n-#FIXME: check to make sure ldrb/ldrh are handled consistently, wrt: IF_B and IF_H. emulation would like all the same.\n-\n-\nO_REG = 0\nO_IMM = 1\n@@ -20,9 +17,12 @@ OperType = (\nArmImmOper,\nArmPcOffsetOper,\n)\n-def shmaskval(value, shval, mask): #FIXME: unnecessary to make this another fn call. will be called a bajillion times.\n+\n+\n+def shmaskval(value, shval, mask):\nreturn (value >> shval) & mask\n+\nclass simpleops:\ndef __init__(self, *operdef):\nself.operdef = operdef\n@@ -34,7 +34,7 @@ class simpleops:\nret.append( oper )\nreturn COND_AL, (ret), None\n-#imm5_rm_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 6, 0x1f))\n+\nrm_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG, 6, 0x7))\nimm3_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 6, 0x7))\nimm8_rd = simpleops((O_REG, 8, 0x7), (O_IMM, 0, 0xff))\n@@ -43,10 +43,9 @@ rn_rdm = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))\nrm_rdn = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))\nrm_rd_imm0 = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 0, 0))\nimm8 = simpleops((O_IMM, 8, 0xff))\n-#imm11 = simpleops((O_IMM, 11, 0x7ff))\n-\nsh4_imm1 = simpleops((O_IMM, 3, 0x1))\n+\ndef d1_rm4_rd3(va, value):\n# 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3)\nrdbit = shmaskval(value, 4, 0x8)\n@@ -54,6 +53,7 @@ def d1_rm4_rd3(va, value):\nrm = shmaskval(value, 3, 0xf)\nreturn COND_AL,(ArmRegOper(rd, va=va),ArmRegOper(rm, va=va)), None\n+\ndef rm_rn_rt(va, value):\ntsize = (4,2,1,1,4,2,1,2)[(value>>9)&7]\nrt = shmaskval(value, 0, 0x7) # target\n@@ -63,6 +63,7 @@ def rm_rn_rt(va, value):\noper1 = ArmRegOffsetOper(rn, rm, va, pubwl=0x18, tsize=tsize)\nreturn COND_AL,(oper0,oper1), None\n+\ndef imm54_rn_rt(va, value):\nimm = shmaskval(value, 4, 0x7c)\nrn = shmaskval(value, 3, 0x7)\n@@ -71,6 +72,7 @@ def imm54_rn_rt(va, value):\noper1 = ArmImmOffsetOper(rn, imm, (va&0xfffffffc)+4, pubwl=0x18, tsize=4)\nreturn COND_AL,(oper0,oper1), None\n+\ndef imm55_rn_rt(va, value):\nimm = shmaskval(value, 5, 0x3e)\nrn = shmaskval(value, 3, 0x7)\n@@ -79,6 +81,7 @@ def imm55_rn_rt(va, value):\noper1 = ArmImmOffsetOper(rn, imm, (va&0xfffffffc)+4, pubwl=0x18, tsize=2)\nreturn COND_AL,(oper0,oper1), None\n+\ndef imm56_rn_rt(va, value):\nimm = shmaskval(value, 6, 0x1f)\nrn = shmaskval(value, 3, 0x7)\n@@ -87,6 +90,7 @@ def imm56_rn_rt(va, value):\noper1 = ArmImmOffsetOper(rn, imm, (va&0xfffffffc)+4, pubwl=0x18, tsize=1)\nreturn COND_AL,(oper0,oper1), None\n+\ndef rd_sp_imm8(va, value): # add\nrd = shmaskval(value, 8, 0x7)\nimm = shmaskval(value, 0, 0xff) * 4\n@@ -95,6 +99,7 @@ def rd_sp_imm8(va, value): # add\noper2 = ArmImmOper(imm, va=va)\nreturn COND_AL,(oper0,oper1,oper2), None\n+\ndef rd_sp_imm8d(va, value): # add\nrd = shmaskval(value, 8, 0x7)\nimm = shmaskval(value, 0, 0xff) * 4\n@@ -103,6 +108,7 @@ def rd_sp_imm8d(va, value): # add\noper1 = ArmImmOffsetOper(REG_SP, imm, (va&0xfffffffc)+4, pubwl=0x18)\nreturn COND_AL,(oper0,oper1), None\n+\ndef rd_pc_imm8(va, value): # add\nrd = shmaskval(value, 8, 0x7)\nimm = e_bits.signed(shmaskval(value, 0, 0xff), 1) * 4\n@@ -111,6 +117,7 @@ def rd_pc_imm8(va, value): # add\noper1 = ArmImmOper((va&0xfffffffc) + 4 + imm)\nreturn COND_AL,(oper0,oper1), None\n+\ndef rd_pc_imm8d(va, value): # add\nrd = shmaskval(value, 8, 0x7)\nimm = e_bits.signed(shmaskval(value, 0, 0xff), 1) * 4\n@@ -119,6 +126,7 @@ def rd_pc_imm8d(va, value): # add\noper1 = ArmImmOffsetOper(REG_PC, imm, (va&0xfffffffc)+4, pubwl=0x18)\nreturn COND_AL,(oper0,oper1), None\n+\ndef rt_pc_imm8d(va, value): # ldr\nrt = shmaskval(value, 8, 0x7)\nimm = e_bits.unsigned((value & 0xff), 1) << 2\n@@ -126,6 +134,7 @@ def rt_pc_imm8d(va, value): # ldr\noper1 = ArmImmOffsetOper(REG_PC, imm, (va&0xfffffffc))\nreturn COND_AL,(oper0,oper1), None\n+\ndef rm4_shift3(va, value): #bx/blx\niflags = None\notype, shval, mask = O_REG, 3, 0xf\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -27,8 +27,8 @@ from envi.tests.armthumb_tests import advsimdtests\nlogger = logging.getLogger(__name__)\n-GOOD_TESTS = 5946\n-GOOD_EMU_TESTS = 1174\n+GOOD_TESTS = 5947\n+GOOD_EMU_TESTS = 1175\n'''\nThis dictionary will contain all instructions supported by ARM to test\nFields will contain following information:\n@@ -1107,6 +1107,7 @@ instrs = [\n(REV_ALL_ARM, '5434a3e7', 0x4560, 'sbfx r3, r4, #0x08, #0x03', 0, ()),\n(REV_ALL_ARM, '14f713e7', 0x4560, 'sdiv r3, r4, r7', 0, ()),\n(REV_ALL_ARM, '14f733e7', 0x4560, 'udiv r3, r4, r7', 0, ()),\n+ (REV_ALL_ARM, '3f5b46ec', 0x4560, 'vmov d31, r5, r6', 0, ()),\n#(REV_ALL_ARM, 'f000f0e7', 0x4560, 'udf #0x00', 0, ()), #This forces an undefined instruction. Commented out normally.\n#all v codes are suspect at this time - not implimented but may not be correct here either\n(REV_ALL_ARM, '173704f2', 0x4560, 'vaba.s8 d3, d4, d7', 0, ()),\n@@ -1418,7 +1419,6 @@ instrs = [\n]\ninstrs.extend(advsimdtests)\n-#instrs = advsimdtests\n# temp scratch: generated these while testing\n['0de803c0','8de903c0','ade903c0','2de803c0','1de803c0','3de803c0','9de903c0','bde903c0',]\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -120,11 +120,11 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nself.vw.setVaSetRow('InfiniteLoops', (op.va, self.fva))\nexcept Exception as e:\n- emumon.logAnomaly(emu, fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\n+ self.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\nlogger.info(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\nexcept Exception as e:\n- emumon.logAnomaly(emu, fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\n+ self.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\nlogger.exception(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -37,8 +37,8 @@ def analyzePLT(vw, ssva, ssize):\nlogger.info('making code: 0x%x', sva)\ntry:\nvw.makeCode(sva)\n- except Exception as e:\n- logger.exception('0x%x: exception: %r', sva, e)\n+ except Exception:\n+ logger.exception('0x%x: exception', sva)\nltup = vw.getLocation(sva)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -207,7 +207,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.emumon.prehook(self, op, starteip)\nexcept Exception as e:\nif not self.getMeta('silent'):\n- logger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon prehook)\", funcva, starteip, op, e)\n+ logger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon prehook: %r)\", funcva, starteip, op, e, self.emumon)\nif self.emustop:\nreturn\n@@ -223,7 +223,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.emumon.posthook(self, op, endeip)\nexcept Exception as e:\nif not self.getMeta('silent'):\n- logger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon posthook)\", funcva, starteip, op, e)\n+ logger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon posthook: %r)\", funcva, starteip, op, e, self.emumon)\nif self.emustop:\nreturn\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
lots of minor fixes and tweaks per code review
|
718,773 |
08.06.2020 14:01:44
| 18,000 |
1ecaa1d723cc33e430a415d371bdfca992f6c9ce
|
Fixes PE parsing bug which prevents adding exported functions that are only exported by ordinal
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -339,6 +339,11 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nexports = pe.getExports()\nfor rva, ord, name in exports:\neva = rva + baseaddr\n+\n+ # Functions exported by ordinal only have no name\n+ if name is None:\n+ name = \"Ordinal_\" + str(ord)\n+\ntry:\nvw.setVaSetRow('pe:ordinals', (eva, ord))\nvw.addExport(eva, EXP_UNTYPED, name, fname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Fixes PE parsing bug which prevents adding exported functions that are only exported by ordinal
|
718,770 |
10.06.2020 00:35:14
| 14,400 |
6210062f48d3a44b7be08d19a9f5788f84665635
|
adv simd and vcvt stuff... s/getFloatValue() added to ArmRegOper
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -90,15 +90,16 @@ IF_DAIB_B = 5<<(IF_DAIB_SHFT-1) # Before mask\nIF_DAIB_I = 3<<(IF_DAIB_SHFT-1) # Before mask\n### what do these do? i can't find reference to them in use\n+IFS_ADV_SIMD = 1<<0 # Advanced SIMD instructions... it matters\nIFS_VQ = 1<<1 # Adv SIMD: operation uses saturating arithmetic\nIFS_VR = 1<<2 # Adv SIMD: operation performs rounding\nIFS_VD = 1<<3 # Adv SIMD: operation doubles the result\nIFS_VH = 1<<4 # Adv SIMD: operation halves the result\n-IFS_SYS_MODE = 1<<8 # instruction is encoded to be executed in SYSTEM mode, not USER mode\n+IFS_SYS_MODE = 1<<5 # instruction is encoded to be executed in SYSTEM mode, not USER mode\n####################################333\n+IFSOFFSET_DYNAMICS = 6\nIFS = [\n- None,\n'.f32.s32',\n'.f64.s32',\n'.f32.u32',\n@@ -150,10 +151,9 @@ IFS = [\n'.f16.f32',\n]\n-for ifx in range(1, len(IFS)):\n- ifs = IFS[ifx]\n+for ifx, ifs in enumerate(IFS):\ngblname = \"IFS\" + ifs.upper().replace('.','_')\n- globals()[gblname] = ifx\n+ globals()[gblname] = ifx + IFSOFFSET_DYNAMICS\nOF_W = 1<<8 # Write back to\nOF_UM = 1<<9 # Usermode, or if r15 included set current SPSR -> CPSR\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -2779,7 +2779,7 @@ adv_simd_2regs_misc = (\n('vneg', INS_VNEG, ADV_SIMD_F8, 0,0, 0),\n('vneg', INS_VNEG, ADV_SIMD_F8, 1,1, 0),\n- ############## HALF WAY DONE! MAKE COMPLETE\n+ ##############\n# a=10 b=0000x\n('vswp', INS_VSWP, ADV_SIMD_NONE, 0,0, 0),\n('vswp', INS_VSWP, ADV_SIMD_NONE, 1,1, 0),\n@@ -3053,6 +3053,7 @@ def _do_adv_simd_32(val, va, u):\n(a, b, u, c),\nbytez=struct.pack('<L', val), va=va)\n+ simdflags |= IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags # no iflags, only simdflags for this one\nelif (a & 0x17) == 0x10 and (c & 0x9) == 1:\n@@ -3072,11 +3073,11 @@ def _do_adv_simd_32(val, va, u):\nif handler is None:\nraise envi.InvalidInstruction(mesg=\"Invalid AdvSIMD Opcode Encoding: modified immediate out of range\",\nbytez=struct.pack('<L', val), va=va)\n- dt, size, val = handler(abcdefgh)\n+ simdflags, size, val = handler(abcdefgh)\nd >>= q\n- if dt in (IFS_F8, IFS_F16, IFS_F32, IFS_F64):\n+ if simdflags in (IFS_F8, IFS_F16, IFS_F32, IFS_F64):\nopers = (\nArmRegOper(rctx.getRegisterIndex(rbase%d)),\nArmFloatOper(val, size=size),\n@@ -3087,7 +3088,8 @@ def _do_adv_simd_32(val, va, u):\nArmImmOper(val, size=size),\n)\n- return opcode, mnem, opers, 0, dt # no iflags, only simdflags for this one\n+ simdflags |= IFS_ADV_SIMD\n+ return opcode, mnem, opers, 0, simdflags # no iflags, only simdflags for this one\n# must be ordered after previous, since this mask collides\nelif ((a & 0x10) == 0x10 and (c & 0x9) in (1, 9)):\n@@ -3277,6 +3279,7 @@ def _do_adv_simd_32(val, va, u):\nArmImmOper(shift_amount),\n)\n+ simdflags |= IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\nelif ((a & 0x16) < 0x16):\n@@ -3311,6 +3314,7 @@ def _do_adv_simd_32(val, va, u):\nszu = sz + flagoff\nsimdflags = adv_simd_dts[szu]\n+ simdflags |= IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\n@@ -3350,6 +3354,7 @@ def _do_adv_simd_32(val, va, u):\nszu = sz + flagoff\nsimdflags = adv_simd_dts[szu]\n+ simdflags |= IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\n@@ -3372,7 +3377,7 @@ def _do_adv_simd_32(val, va, u):\nArmImmOper(imm4),\n)\n- simdflags = IFS_8\n+ simdflags = IFS_8 | IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\nelse:\n@@ -3409,6 +3414,7 @@ def _do_adv_simd_32(val, va, u):\n#print \"2reg_misc: 0x%x (a: 0x%x b: 0x%x idx: %d)\" % (val, a,b,szu)\nsimdflags = adv_simd_dts[szu]\n+ simdflags |= IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\nelif (b & 0xc) == 8:\n@@ -3424,8 +3430,7 @@ def _do_adv_simd_32(val, va, u):\nArmRegOper(rctx.getRegisterIndex('d%d'%m)),\n)\n- simdflags = IFS_8\n-\n+ simdflags = IFS_8 | IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\nelif (b == 0xc):\n@@ -3454,6 +3459,7 @@ def _do_adv_simd_32(val, va, u):\nArmRegScalarOper(rctx.getRegisterIndex('d%d'%m), index),\n)\n+ simdflags |= IFS_ADV_SIMD\nreturn opcode, mnem, opers, 0, simdflags\nreturn 0, 'NO VECTOR ENCODING COMPLETED', (), 0, 0\n@@ -4112,6 +4118,70 @@ class ArmRegOper(ArmOperand):\nreturn None\nemu.setRegister(self.reg, val)\n+ def getFloatValue(self, emu, elmtsz=None, elmtidx=None):\n+ '''\n+ Return the Float value from an element of a FP/SIMD register.\n+ If elmtsz is None, uses the register width as a guide (ie. one element)\n+ If elmtsz is provided, elmtidx should also be provided.\n+\n+ elmtsz is in *bytes*.\n+\n+ we store Floats as X-bit integers and double-convert\n+ '''\n+ if elmtsz is None:\n+ elmtsz = self.getWidth()\n+\n+ ifmt = e_bits.getFormat(self.getEndian(), elmtsz)\n+ ffmt = e_bits.getFloatFormat(self.getEndian(), elmtsz)\n+\n+ # get the 16-/32-/64-bit integer value\n+ metaval = emu.getRegister(self.reg)\n+ if elmtidx is not None:\n+ shiftsz = elmtidx * elmtsz * 8\n+ elmtmask = e_bits.u_maxes[elmtsz]\n+ metaval = (metaval >> shiftsz) & elmtmask\n+\n+ # convert it to the appropriate float\n+ metastr = struct.pack(ifmt, metaval)\n+ fval = struct.unpack(ffmt, metastr)\n+\n+ return fval\n+\n+ def setFloatValue(self, emu, val, elmtsz=None, elmtidx=None):\n+ '''\n+ Store a Float value to an element of a FP/SIMD register.\n+ If elmtsz is None, uses the register width as a guide (ie. one element)\n+ If elmtsz is provided, elmtidx should also be provided.\n+\n+ we store Floats as X-bit integers and double-convert\n+\n+ returns the integer value\n+ '''\n+ if elmtsz is None:\n+ elmtsz = self.getWidth()\n+\n+ ifmt = e_bits.getFormat(self.getEndian(), elmtsz)\n+ ffmt = e_bits.getFloatFormat(self.getEndian(), elmtsz)\n+\n+ # convert float to integer to store\n+ metastr = struct.pack(ffmt, val)\n+ ival = struct.unpack(ifmt, metastr)\n+\n+ if elmtidx is not None:\n+ # get current regsiter values, mask out the part we're about to write\n+ regval = emu.getRegister(self.reg)\n+ shiftsz = elmtidx * elmtsz * 8\n+ mask = -1 ^ (e_bits.u_maxes[elmtsz] << shiftsz)\n+ regval &= mask\n+\n+ # now shift the value to the right element slot and OR with regval\n+ ival <<= shiftsz\n+ regval |= ival\n+\n+ emu.setRegister(self.reg, regval)\n+\n+ return regval\n+\ndef render(self, mcanv, op, idx):\nrname = rctx.getRegisterName(self.reg)\nmcanv.addNameText(rname, typename='registers')\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1003,9 +1003,6 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn result;\n- #def i_vcvtr(self, op):\n- # raise Exception(\"IMPLEMENT ME: i_vcvtr\")\n-\ndef i_vcvt(self, op):\n'''\nconvert each element in a vector as float to int or int to float, 32-bit, round-to-zero/round-to-nearest\n@@ -1014,9 +1011,42 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nlogger.warn('%r\\t%r', op, op.opers)\nlogger.warn(\"complete implementing vcvt\")\n+ if op.iflags & IFS_ADV_SIMD:\n+ # this is an Advanced SIMD instruction\nsrcwidth = op.opers[0].getWidth()\n+ dstwidth = op.opers[1].getWidth()\nregcnt = srcwidth / 4\n+ if len(op.opers) == 3:\n+ # 3rd operand is fbits for Fixed Point numbers\n+ pass\n+\n+ else:\n+ # it's either Floating Point or Integer\n+ pass\n+\n+ else:\n+ # we let the register size sort out the details for non-ADV_SIMD stuff\n+ if op.simdflags & (if_second_F32 | if_second_F64 | if_second_F16):\n+ val = op.opers[1].getFloatValue(self)\n+\n+ else:\n+ val = op.opers[1].getOperValue(op, self)\n+\n+\n+ if len(op.opers) == 3:\n+ # 3rd operand is fbits for Fixed Point numbers\n+ pass\n+\n+ else:\n+ # it's either Floating Point or Integer\n+ if op.simdflags & (ifs_first_F32, ifs_first_F64):\n+ op.opers[0].setFloatValue(self, val)\n+ else:\n+ op.opers[0].setOperValue(op, self, val)\n+\n+\n+\nfirstOP = None\nif op.simdflags & ifs_first_F32:\n# get first vector element as F32\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/bits.py",
"new_path": "envi/bits.py",
"diff": "@@ -175,6 +175,17 @@ def getFormat(size, big_endian=False, signed=False):\n'''\nreturn master_fmts[signed][big_endian][size]\n+def getFloatFormat(size, big_endian=False):\n+ '''\n+ Returns the proper struct format for numbers up to 8 bytes in length\n+ Endianness and Signedness aware.\n+\n+ Only useful for *full individual* numbers... ie. 1, 2, 4, 8. Numbers\n+ of 24-bits (3), 40-bit (5), 48-bits (6) or 56-bits (7) are not accounted\n+ for here and will return None.\n+ '''\n+ return fmt_floats[big_endian][size]\n+\ndef parsebytes(bytes, offset, size, sign=False, bigend=False):\n\"\"\"\nMostly for pulling immediates out of strings...\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
adv simd and vcvt stuff... s/getFloatValue() added to ArmRegOper
|
718,770 |
10.06.2020 08:29:16
| 14,400 |
cbaff71cc79dfcfc651f3dad7b4f5d05b1517f3d
|
putting simdflags back to what it was... need to fix naming. this is not flags per se.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -79,6 +79,7 @@ IF_IE = 1<<43 # Interrupt Enable flag (used for CPS instruction)\nIF_ID = 1<<44 # Interrupt Disable flag (used for CPS instruction)\nIF_THUMB32 = 1<<50 # thumb32\n+IF_ADV_SIMD = 1<<51 # Advanced SIMD instructions... it matters\nIF_DAIB_SHFT = 56 # shift-bits to get DAIB bits down to 0. this chops off the \"is DAIB present\" bit that the following store.\nIF_DAIB_MASK = 7<<(IF_DAIB_SHFT-1)\n@@ -90,16 +91,15 @@ IF_DAIB_B = 5<<(IF_DAIB_SHFT-1) # Before mask\nIF_DAIB_I = 3<<(IF_DAIB_SHFT-1) # Before mask\n### what do these do? i can't find reference to them in use\n-IFS_ADV_SIMD = 1<<0 # Advanced SIMD instructions... it matters\nIFS_VQ = 1<<1 # Adv SIMD: operation uses saturating arithmetic\nIFS_VR = 1<<2 # Adv SIMD: operation performs rounding\nIFS_VD = 1<<3 # Adv SIMD: operation doubles the result\nIFS_VH = 1<<4 # Adv SIMD: operation halves the result\n-IFS_SYS_MODE = 1<<5 # instruction is encoded to be executed in SYSTEM mode, not USER mode\n+IFS_SYS_MODE = 1<<8 # instruction is encoded to be executed in SYSTEM mode, not USER mode\n####################################333\n-IFSOFFSET_DYNAMICS = 6\nIFS = [\n+ None,\n'.f32.s32',\n'.f64.s32',\n'.f32.u32',\n@@ -151,9 +151,11 @@ IFS = [\n'.f16.f32',\n]\n-for ifx, ifs in enumerate(IFS):\n+for ifx in range(1, len(IFS)):\n+ ifs = IFS[ifx]\ngblname = \"IFS\" + ifs.upper().replace('.','_')\n- globals()[gblname] = ifx + IFSOFFSET_DYNAMICS\n+ globals()[gblname] = ifx\n+\nOF_W = 1<<8 # Write back to\nOF_UM = 1<<9 # Usermode, or if r15 included set current SPSR -> CPSR\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -3053,8 +3053,7 @@ def _do_adv_simd_32(val, va, u):\n(a, b, u, c),\nbytez=struct.pack('<L', val), va=va)\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags # no iflags, only simdflags for this one\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelif (a & 0x17) == 0x10 and (c & 0x9) == 1:\n# one register and modified immediate\n@@ -3088,8 +3087,7 @@ def _do_adv_simd_32(val, va, u):\nArmImmOper(val, size=size),\n)\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags # no iflags, only simdflags for this one\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\n# must be ordered after previous, since this mask collides\nelif ((a & 0x10) == 0x10 and (c & 0x9) in (1, 9)):\n@@ -3279,8 +3277,7 @@ def _do_adv_simd_32(val, va, u):\nArmImmOper(shift_amount),\n)\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelif ((a & 0x16) < 0x16):\na = (val >> 8) & 0xf\n@@ -3314,8 +3311,7 @@ def _do_adv_simd_32(val, va, u):\nszu = sz + flagoff\nsimdflags = adv_simd_dts[szu]\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelif (c & 0x5) == 0x4:\n@@ -3354,8 +3350,7 @@ def _do_adv_simd_32(val, va, u):\nszu = sz + flagoff\nsimdflags = adv_simd_dts[szu]\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelif (a & 0x16) == 0x16:\n@@ -3377,8 +3372,8 @@ def _do_adv_simd_32(val, va, u):\nArmImmOper(imm4),\n)\n- simdflags = IFS_8 | IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ simdflags = IFS_8\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelse:\nif (c & 1) == 0:\n@@ -3414,8 +3409,7 @@ def _do_adv_simd_32(val, va, u):\n#print \"2reg_misc: 0x%x (a: 0x%x b: 0x%x idx: %d)\" % (val, a,b,szu)\nsimdflags = adv_simd_dts[szu]\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelif (b & 0xc) == 8:\n# vector table lookup VTBL, VTBX\n@@ -3430,8 +3424,8 @@ def _do_adv_simd_32(val, va, u):\nArmRegOper(rctx.getRegisterIndex('d%d'%m)),\n)\n- simdflags = IFS_8 | IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ simdflags = IFS_8\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nelif (b == 0xc):\n# vector duplicate VDUP (scalar)\n@@ -3459,8 +3453,7 @@ def _do_adv_simd_32(val, va, u):\nArmRegScalarOper(rctx.getRegisterIndex('d%d'%m), index),\n)\n- simdflags |= IFS_ADV_SIMD\n- return opcode, mnem, opers, 0, simdflags\n+ return opcode, mnem, opers, IF_ADV_SIMD, simdflags\nreturn 0, 'NO VECTOR ENCODING COMPLETED', (), 0, 0\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
putting simdflags back to what it was... need to fix naming. this is not flags per se.
|
718,770 |
10.06.2020 10:52:32
| 14,400 |
c11cf6b453fedbb69f0df5d1fbd6c66eb31b1216
|
tweaks to adjust to new mainline changes (e_exc), and cleanup const.py to remove old IFS_ "flags"
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -90,13 +90,6 @@ IF_IB = 7<<(IF_DAIB_SHFT-1) # Increment Before\nIF_DAIB_B = 5<<(IF_DAIB_SHFT-1) # Before mask\nIF_DAIB_I = 3<<(IF_DAIB_SHFT-1) # Before mask\n-### what do these do? i can't find reference to them in use\n-IFS_VQ = 1<<1 # Adv SIMD: operation uses saturating arithmetic\n-IFS_VR = 1<<2 # Adv SIMD: operation performs rounding\n-IFS_VD = 1<<3 # Adv SIMD: operation doubles the result\n-IFS_VH = 1<<4 # Adv SIMD: operation halves the result\n-IFS_SYS_MODE = 1<<8 # instruction is encoded to be executed in SYSTEM mode, not USER mode\n-####################################333\nIFS = [\nNone,\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "import struct\nimport envi\n+import envi.exc as e_exc\nimport envi.memory as e_mem\n-import envi.registers as e_reg\nimport envi.memcanvas as e_memcanvas\nimport envi.memcanvas.renderers as e_rend\nimport envi.archs.arm as arm\n@@ -1887,7 +1887,7 @@ class ArmInstructionSet(unittest.TestCase):\ntry:\n# try register first\nemu.setRegisterByName(tgt, val)\n- except e_reg.InvalidRegisterName, e:\n+ except e_exc.InvalidRegisterName, e:\n# it's not a register\nif type(tgt) == str and tgt.startswith(\"PSR_\"):\n# it's a flag\n@@ -1912,7 +1912,7 @@ class ArmInstructionSet(unittest.TestCase):\nsuccess = 0\nelse: # should be an else\nraise Exception(\"FAILED(reg): (%r test#%d) %s != 0x%x (observed: 0x%x) \\n\\t(setters: %r)\\n\\t(test: %r)\" % (op, tidx, tgt, val, testval, settersrepr, testsrepr))\n- except e_reg.InvalidRegisterName, e:\n+ except e_exc.InvalidRegisterName, e:\n# it's not a register\nif type(tgt) == str and tgt.startswith(\"PSR_\"):\n# it's a flag\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
tweaks to adjust to new mainline changes (e_exc), and cleanup const.py to remove old IFS_ "flags"
|
718,770 |
11.06.2020 23:51:54
| 14,400 |
a383cea093bd51d748add0c08f7f4f319ff33e9d
|
mods from review.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -80,6 +80,7 @@ IF_ID = 1<<44 # Interrupt Disable flag (used for CPS instruction)\nIF_THUMB32 = 1<<50 # thumb32\nIF_ADV_SIMD = 1<<51 # Advanced SIMD instructions... it matters\n+IF_SYS_MODE = 1<<52\nIF_DAIB_SHFT = 56 # shift-bits to get DAIB bits down to 0. this chops off the \"is DAIB present\" bit that the following store.\nIF_DAIB_MASK = 7<<(IF_DAIB_SHFT-1)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -169,7 +169,6 @@ DP_PSR_S = [IF_PSR_S for x in range(17)]\nfor x in dp_silS:\nDP_PSR_S[x] |= IF_PSR_S_SIL\n-# FIXME: dp_MOV was supposed to be a tuple of opcodes that could be converted to MOV's if offset from PC.\n# somehow this list has vanished into the ether. add seems like the right one here.\ndp_ADR = (INS_SUB, INS_ADD,)\n@@ -829,8 +828,8 @@ def p_mov_imm_stat(opval, va): # only one instruction: \"msr\"\nopcode = INS_MSR\nimmed = ((imm>>rot) + (imm<<(32-rot))) & 0xffffffff\n- #if mask & 3: # USER mode these will be 0\n- # iflags |= IF_SYS_MODE - only mention of IF_SYS_MODE, causing errors. does need fixing?\n+ if mask & 3: # USER mode these will be 0\n+ iflags |= IF_SYS_MODE\nolist = (\nArmPgmStatRegOper(r, mask),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
mods from review.
|
718,770 |
12.06.2020 00:57:50
| 14,400 |
07fe580172631487c501a59c66851552caf96b0c
|
`cleanup of revsh and rev16, logAnomaly, and a few other changes from code review.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -998,7 +998,7 @@ for pre in par_prefixes:\nelse:\nmnem = pre + suf\nopname = \"INS_\" + mnem.upper()\n- opcode = eval(opname)\n+ opcode = globals()[opname]\nparallel_mnem.append((mnem, opcode))\nparallel_mnem = tuple(parallel_mnem)\n@@ -1028,7 +1028,8 @@ for pre in xtnd_prefixes:\nxtnd_mnem.append((None, None))\nelse:\nmnem = pre+suf\n- opcode = eval('INS_' + mnem.upper())\n+ opname = 'INS_' + mnem.upper()\n+ opcode = globals()[opname]\nxtnd_mnem.append((mnem, opcode))\nxtnd_mnem = tuple(xtnd_mnem)\n@@ -1122,10 +1123,29 @@ def p_media_pack_sat_rev_extend(opval, va):\nArmRegOper(Rd, va=va),\nArmRegOper(Rm, va=va),\n)\n+\nelif opc1 == 3 and opc2 == 0xb: # byte rev pkt halfword\n- raise Exception('IMPLEMENT ME: byte rev pkt halfword')\n+ mnem = 'rev16'\n+ opcode = INS_REV16\n+\n+ Rd = (opval>>12) & 0xf\n+ Rm = opval & 0xf\n+ olist = (\n+ ArmRegOper(Rd, va=va),\n+ ArmRegOper(Rm, va=va),\n+ )\n+\nelif opc1 == 7 and opc2 == 0xb: # byte rev signed halfword\n- raise Exception('IMPLEMENT ME: byte rev signed halfword')\n+ mnem = 'revsh'\n+ opcode = INS_REVSH\n+\n+ Rd = (opval>>12) & 0xf\n+ Rm = opval & 0xf\n+ olist = (\n+ ArmRegOper(Rd, va=va),\n+ ArmRegOper(Rm, va=va),\n+ )\n+\nelif opc1 == 0 and opc2 == 0xb: # select bytes\nmnem = \"sel\"\nopcode = INS_SEL\n@@ -1137,6 +1157,7 @@ def p_media_pack_sat_rev_extend(opval, va):\nArmRegOper(Rn, va=va),\nArmRegOper(Rm, va=va),\n)\n+\nelif opc2 == 7: # sign extend\nidx = (opc1&3) + 8 * ((opval>>22) &1)\nRn = (opval>>16) & 0xf\n@@ -1169,6 +1190,7 @@ def p_media_pack_sat_rev_extend(opval, va):\nArmRegOper(Rm, va=va),\n)\nmnem, opcode = xtnd_mnem[idx]\n+\nelse:\nraise envi.InvalidInstruction(\nmesg=\"p_media_extend: invalid instruction %r.%r\" % (opc1, opc2),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1011,7 +1011,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nlogger.warn('%r\\t%r', op, op.opers)\nlogger.warn(\"complete implementing vcvt\")\n- if op.iflags & IFS_ADV_SIMD:\n+ if op.iflags & IF_ADV_SIMD:\n# this is an Advanced SIMD instruction\nsrcwidth = op.opers[0].getWidth()\ndstwidth = op.opers[1].getWidth()\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -27,7 +27,7 @@ from envi.tests.armthumb_tests import advsimdtests\nlogger = logging.getLogger(__name__)\n-GOOD_TESTS = 5947\n+GOOD_TESTS = 5949\nGOOD_EMU_TESTS = 1175\n'''\nThis dictionary will contain all instructions supported by ARM to test\n@@ -833,6 +833,8 @@ instrs = [\n(REV_ALL_ARM, '173084e6', 0x4560, 'pkhbt r3, r4, r7', 0, ()),\n(REV_ALL_ARM, '573384e6', 0x4560, 'pkhtb r3, r4, r7, asr #6', 0, ()),\n(REV_ALL_ARM, '573084e6', 0x4560, 'pkhtb r3, r4, r7', 0, ()),\n+ (REV_ALL_ARM, 'b34fffe6', 0x4560, 'revsh r4, r3', 0, ()),\n+ (REV_ALL_ARM, 'b34fbfe6', 0x4560, 'rev16 r4, r3', 0, ()),\n(REV_ALL_ARM, '543007e1', 0x4560, 'qadd r3, r4, r7', 0, ()),\n(REV_ALL_ARM, '173f24e6', 0x4560, 'qadd16 r3, r4, r7', 0, ()),\n(REV_ALL_ARM, '973f24e6', 0x4560, 'qadd8 r3, r4, r7', 0, ()),\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -120,11 +120,11 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nself.vw.setVaSetRow('InfiniteLoops', (op.va, self.fva))\nexcept Exception as e:\n- self.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\n+ self.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\" % (op.va, op, e))\nlogger.info(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\nexcept Exception as e:\n- self.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\", op.va, op, e)\n+ self.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\" % (op.va, op, e))\nlogger.exception(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
`cleanup of revsh and rev16, logAnomaly, and a few other changes from code review.
|
718,770 |
12.06.2020 01:42:48
| 14,400 |
d2476182328a785d6fcd1dd43a12d77535682021
|
mods per review (and unit tests too)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -2629,7 +2629,7 @@ adv_simd_3diffregs = (\n('vsubw', INS_VSUBW, ADV_SIMD_S8, 1, 1, 0),\n('vsubw', INS_VSUBW, ADV_SIMD_U8, 1, 1, 0),\n# a=4, u=0/1\n- ('vaddhn', INS_VADDHN, ADV_SIMD_I8+1, 0, 1, 1), # THIS IS TROUBLE... 9 instead of 8? i'm expecting a multiplicative problem\n+ ('vaddhn', INS_VADDHN, ADV_SIMD_I8+1, 0, 1, 1),\n('vraddhn', INS_VRADDHN, ADV_SIMD_I8+1, 0, 1, 1),\n# a=5, u=0/1\n('vabal', INS_VABAL, ADV_SIMD_S8, 1, 0, 0),\n@@ -2650,7 +2650,7 @@ adv_simd_3diffregs = (\n('vmlsl', INS_VMLSL, ADV_SIMD_S8, 1, 0, 0),\n('vmlsl', INS_VMLSL, ADV_SIMD_U8, 1, 0, 0),\n# a=0xb\n- ('vqdmlsl', INS_VQDMLSL, ADV_SIMD_S8, 1, 0, 0), # FIXME: TESTME thumb: 0xef9349a5, 0xefe34ba5\n+ ('vqdmlsl', INS_VQDMLSL, ADV_SIMD_S8, 1, 0, 0),\n(None, None, 0, 1, 0, 0),\n# a=0xc\n('vmull', INS_VMULL, ADV_SIMD_S8, 1, 0, 0),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_arm.py",
"new_path": "envi/tests/test_arch_arm.py",
"diff": "@@ -27,7 +27,7 @@ from envi.tests.armthumb_tests import advsimdtests\nlogger = logging.getLogger(__name__)\n-GOOD_TESTS = 5949\n+GOOD_TESTS = 5953\nGOOD_EMU_TESTS = 1175\n'''\nThis dictionary will contain all instructions supported by ARM to test\n@@ -1179,6 +1179,8 @@ instrs = [\n(REV_ALL_ARM, '0e3488f2', 0x4560, 'vaddhn.i16 d3, q4, q7', 0, ()),\n(REV_ALL_ARM, '0e3498f2', 0x4560, 'vaddhn.i32 d3, q4, q7', 0, ()),\n(REV_ALL_ARM, '0e34a8f2', 0x4560, 'vaddhn.i64 d3, q4, q7', 0, ()),\n+ (REV_ALL_ARM, 'c3efa544', 0x4561, 'vaddhn.i16 d20, q9, q10', 0, ()),\n+ (REV_ALL_ARM, 'e3efa544', 0x4561, 'vaddhn.i64 d20, q9, q10', 0, ()),\n(REV_ALL_ARM, '076084f2', 0x4560, 'vaddl.s8 q3, d4, d7', 0, ()),\n(REV_ALL_ARM, '076094f2', 0x4560, 'vaddl.s16 q3, d4, d7', 0, ()),\n(REV_ALL_ARM, '0760a4f2', 0x4560, 'vaddl.s32 q3, d4, d7', 0, ()),\n@@ -1366,8 +1368,8 @@ instrs = [\n(REV_ALL_ARM, '56f6e456', 0x4561, 'movw.w r6, r6, #0x6de4', 0, ()),\n(REV_ALL_ARM, '53f83450', 0x4561, 'ldr.w r5, [r3, r4, lsl #3]', 0, ()),\n- #(REV_ALL_ARM, 'a54be3ef', 0x4561, 'vqdmlsl.s32 q10, d19, d21', 0, ()),\n- #(REV_ALL_ARM, 'a54993ef', 0x4561, 'vqdmlal.s16 q2, d19, d21', 0, ()),\n+ (REV_ALL_ARM, 'e3efa54b', 0x4561, 'vqdmlsl.s32 q10, d19, d21', 0, ()),\n+ (REV_ALL_ARM, '93efa549', 0x4561, 'vqdmlal.s16 q2, d19, d21', 0, ()),\n(REV_ALL_ARM, 'aaefe440', 0x4561, 'vmla.i32 d4, d26, d4[1]', 0, ()),\n(REV_ALL_ARM, 'aaefe441', 0x4561, 'vmla.f32 d4, d26, d4[1]', 0, ()),\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
mods per review (and unit tests too)
|
718,770 |
13.06.2020 01:21:15
| 14,400 |
404c0b419408ab470beef3a2ac9a43897b808c50
|
cleanup per code review.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -163,7 +163,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.mem_access_lock = threading.Lock()\n# FIXME: this should be None's, and added in for each real coproc... but this will work for now.\n- self.coprocs = [CoProcEmulator(x) for x in xrange(16)]\n+ self.coprocs = [CoProcEmulator(x) for x in range(16)]\nself.int_handlers = {}\n@@ -336,7 +336,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n'''\nset the CPSR for the current ARM processor mode\n'''\n- self.setCPSR(psr, mask=0xffff0000)\n+ self.setCPSR(psr, mask=REG_APSR_MASK)\ndef getSPSR(self, mode):\n'''\n@@ -707,20 +707,19 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\n# do multiples based on base and count. unlike ldm, these must be consecutive\nif flags & IF_DAIB_I == IF_DAIB_I:\n- for reg in xrange(count):\n+ for reg in range(count):\nregval = self.readMemValue(addr, size)\nself.setRegister(reg, regval)\naddr += size\nelse:\n- for reg in xrange(count-1, -1, -1):\n+ for reg in range(count-1, -1, -1):\naddr -= size\nregval = self.readMemValue(addr, size)\nself.setRegister(reg, regval)\nif updatereg:\nself.setRegister(srcreg,addr)\n- #FIXME: add \"shared memory\" functionality? prolly just in ldrex which will be handled in i_ldrex\n- # is the following necessary?\n+\nnewpc = self.getRegister(REG_PC) # check whether pc has changed\nif pc != newpc:\nself.setThumbMode(newpc & 1)\n@@ -848,21 +847,21 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif IsZero(exp):\n# Produce zero if value is zero\nif IsZero(frac):\n- type = FPType_Zero\n+ ftype = FPType_Zero\nvalue = 0.0;\nelse:\n- type = FPType_Nonzero\n+ ftype = FPType_Nonzero\nvalue = 2^-14 * (UInt(frac) * 2^-10);\nelif IsOnes(exp) and (fpscr_val>>26)&1 == 0: # Infinity or NaN in IEEE format\nif IsZero(frac):\n- type = FPType_Infinity\n+ ftype = FPType_Infinity\nvalue = 2^1000000;\nelse:\n- type = (FPType_SNaN, FPType_QNaN)[(frac>>9)&1]\n+ ftype = (FPType_SNaN, FPType_QNaN)[(frac>>9)&1]\nvalue = 0.0\nelse:\n- type = FPType_Nonzero\n+ ftype = FPType_Nonzero\nvalue = 2^(UInt(exp)-15) * (1.0 + UInt(frac) * 2^-10);\nelif N == 32:\n@@ -872,22 +871,22 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif IsZero(exp):\n# Produce zero if value is zero or flush-to-zero is selected.\nif IsZero(frac) or (fpscr_val>>24) & 1 == 1:\n- type = FPType_Zero\n+ ftype = FPType_Zero\nvalue = 0.0\nif not IsZero(frac): # Denormalized input flushed to zero\nFPProcessException(FPExc_InputDenorm, fpscr_val);\nelse:\n- type = FPType_Nonzero\n+ ftype = FPType_Nonzero\nvalue = 2^-126 * (UInt(frac) * 2^-23);\nelif IsOnes(exp):\nif IsZero(frac):\n- type = FPType_Infinity\n+ ftype = FPType_Infinity\nvalue = 2^1000000;\nelse:\n- type = (FPType_SNaN, FPType_QNaN)[(frac>>22)&1]\n+ ftype = (FPType_SNaN, FPType_QNaN)[(frac>>22)&1]\nvalue = 0.0;\nelse:\n- type = FPType_Nonzero\n+ ftype = FPType_Nonzero\nvalue = 2^(UInt(exp)-127) * (1.0 + UInt(frac) * 2^-23);\nelse: # N == 64\nsign = (fpval>>63) & 1\n@@ -896,27 +895,27 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif IsZero(exp):\n# Produce zero if value is zero or flush-to-zero is selected.\nif IsZero(frac) or (fpscr_val>>24) & 1 == 1:\n- type = FPType_Zero\n+ ftype = FPType_Zero\nvalue = 0.0\nif not IsZero(frac): # Denormalized input flushed to zero\nFPProcessException(FPExc_InputDenorm, fpscr_val)\nelse:\n- type = FPType_Nonzero\n+ ftype = FPType_Nonzero\nvalue = 2^-1022 * (UInt(frac) * 2^-52)\nelif IsOnes(exp):\nif IsZero(frac):\n- type = FPType_Infinity\n+ ftype = FPType_Infinity\nvalue = 2^1000000\nelse:\n- type = (FPType_SNaN, FPType_QNaN)[(frac>>51) & 1]\n+ ftype = (FPType_SNaN, FPType_QNaN)[(frac>>51) & 1]\nvalue = 0.0\nelse:\n- type = FPType_Nonzero\n+ ftype = FPType_Nonzero\nvalue = 2^(UInt(exp)-1023) * (1.0 + UInt(frac) * 2^-52)\nif sign == '1': value = -value\n- return (type, sign, value)\n+ return (ftype, sign, value)\ndef FPToFixed(operand, M, fraction_bits, unsigned, round_towards_zero, fpscr_controlled):\n@@ -928,14 +927,14 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif round_towards_zero:\nfpscr_val |= 0b00000000110000000000000000000000\n- (type,sign,value) = FPUnpack(operand, fpscr_val)\n+ (ftype,sign,value) = FPUnpack(operand, fpscr_val)\n# For NaNs and infinities, FPUnpack() has produced a value that will round to the\n# required result of the conversion. Also, the value produced for infinities will\n# cause the conversion to overflow and signal an Invalid Operation floating-point\n# exception as required. NaNs must also generate such a floating-point exception.\n- if type == FPType_SNaN or type == FPType_QNaN:\n+ if ftype == FPType_SNaN or ftype == FPType_QNaN:\nFPProcessException(FPExc_InvalidOp, fpscr_val)\n# Scale value by specified number of fraction bits, then start rounding to an integer\n@@ -1186,13 +1185,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\npc = self.getRegister(REG_PC) # store for later check\nif flags & IF_DAIB_I == IF_DAIB_I:\n- for reg in xrange(16):\n+ for reg in range(16):\nif (1<<reg) & regmask:\nregval = self.readMemValue(addr, 4)\nself.setRegister(reg, regval)\naddr += 4\nelse:\n- for reg in xrange(15, -1, -1):\n+ for reg in range(15, -1, -1):\nif (1<<reg) & regmask:\naddr -= 4\nregval = self.readMemValue(addr, 4)\n@@ -1200,8 +1199,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nif updatereg:\nself.setRegister(srcreg,addr)\n- #FIXME: add \"shared memory\" functionality? prolly just in ldrex which will be handled in i_ldrex\n- # is the following necessary?\n+\nnewpc = self.getRegister(REG_PC) # check whether pc has changed\nif pc != newpc:\nself.setThumbMode(newpc & 1)\n@@ -1366,7 +1364,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_str(self, op):\n# hint: covers str, strb, strbt, strd, strh, strsh, strsb, strt (any instr where the syntax is str{condition}stuff)\n- # need to check that t variants only allow non-priveleged access (strt, strht etc)\n+ # TODO: need to check that t variants only allow non-priveleged access (strt, strht etc)\nval = self.getOperValue(op, 0)\nself.setOperValue(op, 1, val)\n@@ -1974,6 +1972,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_cps(self, op):\nlogger.warn(\"CPS: 0x%x %r\" % (op.va, op))\n+ # FIXME: at some point we need ot do a priviledge check\ndef i_pld2(self, op):\nlogger.warn(\"FIXME: 0x%x: %s - in emu\" % (op.va, op))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -44,7 +44,6 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nloctup = emu.vw.getLocation(starteip)\nif loctup is None:\n- # do we want to hand this off to makeCode?\n#print \"emulation: prehook: new LOC_OP fva: 0x%x starteip: 0x%x flags: 0x%x\" % (self.fva, starteip, op.iflags)\narch = (envi.ARCH_ARMV7, envi.ARCH_THUMB)[(starteip & 1) | tmode]\nemu.vw.makeCode(starteip & -2, arch=arch)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
cleanup per code review.
|
718,765 |
15.06.2020 18:01:28
| 14,400 |
8cdda0863e9811f68b3733aec5d54d1abbcde566
|
Cleanup
better exception catching
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/switchcase.py",
"new_path": "vivisect/analysis/generic/switchcase.py",
"diff": "@@ -52,7 +52,7 @@ def scanUp(vw, emu, startva, regidx, valu):\nloc = vw.getLocation(startva)\nwhile loc is not None and vw.getCodeBlock(loc[v_const.L_VA]) == cb:\nop = vw.parseOpcode(loc[0])\n- if len(op.opers) and op.opers[0].isReg() and getRealRegIdx(emu, op.opers[0].reg) == regidx:\n+ if len(op.opers) > 1 and op.opers[0].isReg() and getRealRegIdx(emu, op.opers[0].reg) == regidx:\nif valu == emu.getOperValue(op, 1):\nreturn True\nloc = vw.getLocation(loc[0] - 1)\n@@ -96,8 +96,12 @@ def getSwitchBase(vw, op, vajmp, emu=None):\n# TODO: Want a more arch-independent way of doing this\narrayOper = movOp.opers[1]\n- if (not isinstance(arrayOper, e_i386.i386SibOper)) and (not (arrayOper.scale % 4 == 0)):\n- vw.verbprint(\"0x%x: Either arrayoper is not an i386SibOper or scale is wrong: %s\" % (op.va, repr(arrayOper)))\n+ if not isinstance(arrayOper, e_i386.i386SibOper):\n+ vw.verbprint(\"0x%x: arrayOper is not an i386SibOper: %s\" % (op.va, repr(arrayOper)))\n+ return\n+\n+ if arrayOper.scale % 4 != 0:\n+ vw.verbprint(\"0x%x: arrayoper scale is wrong: (%d mod 4 != 0)\" % (op.va, arrayOper.scale))\nreturn\nscale = arrayOper.scale\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/instrhook.py",
"new_path": "vivisect/analysis/i386/instrhook.py",
"diff": "@@ -42,7 +42,7 @@ class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\ndef analyzeFunction(vw, fva):\nemulate = False\n- dist = vw.getFunctionMeta(fva, 'MnemDist')\n+ dist = vw.getFunctionMeta(fva, 'MnemDist', default=[])\nfor s in STOS:\nif s in dist:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Cleanup (#287)
better exception catching
|
718,770 |
23.06.2020 12:56:40
| 14,400 |
33e23e3afca5a99558ea6ed2209400000646de89
|
IFS comments and fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/const.py",
"new_path": "envi/archs/arm/const.py",
"diff": "@@ -92,6 +92,8 @@ IF_DAIB_B = 5<<(IF_DAIB_SHFT-1) # Before mask\nIF_DAIB_I = 3<<(IF_DAIB_SHFT-1) # Before mask\n+# NOTE: unlike IF_*, IFS_* are *NOT* flags. they are indices into the IFS list.\n+# thus, opcode.simdflags is *not* flags, but one index. only one can be used at a time.\nIFS = [\nNone,\n'.f32.s32',\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -140,16 +140,29 @@ OP_F64 = 3\nOP_S32 = 4\nOP_U32 = 5\n-ifs_first_F32 = (IFS_F32_S32 | IFS_F32_U32 | IFS_F32_F64 | IFS_F32_F16)\n-ifs_second_F32 = (IFS_S32_F32 | IFS_U32_F32 | IFS_F64_F32 | IFS_F16_F32)\n-ifs_first_S32 = (IFS_S32_F32 | IFS_S32_F64 | IFS_S32_F32)\n-ifs_second_S32 = (IFS_F32_S32 | IFS_F64_S32 | IFS_F32_S32)\n-ifs_first_U32 = (IFS_U32_F32 | IFS_U32_F64)\n-ifs_second_U32 = (IFS_F64_U32 | IFS_F32_U32)\n-ifs_first_F64 = (IFS_F64_S32 | IFS_F64_U32 | IFS_F64_F32)\n-ifs_second_F64 = (IFS_S32_F64 | IFS_U32_F64 | IFS_F32_F64)\n-ifs_first_F16 = IFS_F16_F32\n-ifs_second_F16 = IFS_F32_F16\n+# ifs_first* and ifs_second* are a way of grouping like-SIMD options based on\n+# first or second operand. since each \"flag\" indicates *all* operands, we\n+# need a way to group them logically to make decisions about the source(s) and\n+# destinations. these are helpers for i_vcvt()\n+\n+# NOTE: IFS_* \"flags\" are not flags, but indices into the IFS list in const.py\n+\n+ifs_first_F32 = (IFS_F32_S32, IFS_F32_U32, IFS_F32_F64, IFS_F32_F16)\n+ifs_second_F32 = (IFS_S32_F32, IFS_U32_F32, IFS_F64_F32, IFS_F16_F32)\n+ifs_first_S32 = (IFS_S32_F32, IFS_S32_F64, IFS_S32_F32)\n+ifs_second_S32 = (IFS_F32_S32, IFS_F64_S32, IFS_F32_S32)\n+ifs_first_U32 = (IFS_U32_F32, IFS_U32_F64)\n+ifs_second_U32 = (IFS_F64_U32, IFS_F32_U32)\n+ifs_first_F64 = (IFS_F64_S32, IFS_F64_U32, IFS_F64_F32)\n+ifs_second_F64 = (IFS_S32_F64, IFS_U32_F64, IFS_F32_F64)\n+ifs_first_F16 = (IFS_F16_F32,)\n+ifs_second_F16 = (IFS_F32_F16,)\n+\n+ifs_first_F32_F64 = ifs_first_F32 + ifs_first_F64\n+ifs_first_F32_F64_F16 = ifs_first_F32 + ifs_first_F64 + ifs_first_F16\n+\n+ifs_second_F32_F64 = ifs_second_F32 + ifs_second_F64\n+ifs_second_F32_F64_F16 = ifs_second_F32 + ifs_second_F64 + ifs_second_F16\nclass ArmEmulator(ArmRegisterContext, envi.Emulator):\n@@ -795,7 +808,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ndef i_vcmpe(self, op):\ntry:\n- size = (4,8)[bool(op.iflags & IFS_F64)]\n+ size = (4,8)[bool(op.simdflags == IFS_F64)]\nsrc1 = self.getOperValue(op, 0)\nsrc2 = self.getOperValue(op, 1)\n@@ -1026,7 +1039,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nelse:\n# we let the register size sort out the details for non-ADV_SIMD stuff\n- if op.simdflags & (if_second_F32 | if_second_F64 | if_second_F16):\n+ if op.simdflags in if_second_F32_F64_F16:\nval = op.opers[1].getFloatValue(self)\nelse:\n@@ -1039,7 +1052,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nelse:\n# it's either Floating Point or Integer\n- if op.simdflags & (ifs_first_F32, ifs_first_F64):\n+ if op.simdflags in ifs_first_F32_F64:\nop.opers[0].setFloatValue(self, val)\nelse:\nop.opers[0].setOperValue(op, self, val)\n@@ -1047,29 +1060,29 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nfirstOP = None\n- if op.simdflags & ifs_first_F32:\n+ if op.simdflags in ifs_first_F32:\n# get first vector element as F32\nfirstOP = OP_F32\n- elif op.simdflags & ifs_first_S32:\n+ elif op.simdflags in ifs_first_S32:\nfirstOP = OP_S32\n- elif op.simdflags & ifs_first_U32:\n+ elif op.simdflags in ifs_first_U32:\nfirstOP = OP_U32\n- elif op.simdflags & ifs_first_F64:\n+ elif op.simdflags in ifs_first_F64:\nfirstOP = OP_F64\n- elif op.simdflags & ifs_first_F16:\n+ elif op.simdflags in ifs_first_F16:\nfirstOP = OP_F16\nsecOP = None\n- if op.simdflags & ifs_second_F32:\n+ if op.simdflags in ifs_second_F32:\n# get second vector element as F32\nsecOP = OP_F32\n- elif op.simdflags & ifs_second_S32:\n+ elif op.simdflags in ifs_second_S32:\nsecOP = OP_S32\n- elif op.simdflags & ifs_second_U32:\n+ elif op.simdflags in ifs_second_U32:\nsecOP = OP_U32\n- elif op.simdflags & ifs_second_F64:\n+ elif op.simdflags in ifs_second_F64:\nsecOP = OP_F64\n- elif op.simdflags & ifs_second_F16:\n+ elif op.simdflags in ifs_second_F16:\nsecOP = OP_F16\nraise Exception(\"IMPLEMENT ME: i_vcvt\")\n@@ -1077,84 +1090,84 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nfor reg in range(regcnt):\n#frac_bits = 64 - op.opers[2].val\n# pA8_870\n- if op.simdflags & IFS_F32_S32:\n+ if op.simdflags == IFS_F32_S32:\npass\n- elif op.simdflags & IFS_F32_U32:\n+ elif op.simdflags == IFS_F32_U32:\npass\n- elif op.simdflags & IFS_S32_F32:\n+ elif op.simdflags == IFS_S32_F32:\npass\n- elif op.simdflags & IFS_U32_F32:\n+ elif op.simdflags == IFS_U32_F32:\npass\n# pA8_872\n- elif op.simdflags & IFS_U16_F32:\n+ elif op.simdflags == IFS_U16_F32:\npass\n- elif op.simdflags & IFS_S16_F32:\n+ elif op.simdflags == IFS_S16_F32:\npass\n- elif op.simdflags & IFS_U32_F32:\n+ elif op.simdflags == IFS_U32_F32:\npass\n- elif op.simdflags & IFS_S32_F32:\n+ elif op.simdflags == IFS_S32_F32:\npass\n- elif op.simdflags & IFS_U16_F64:\n+ elif op.simdflags == IFS_U16_F64:\npass\n- elif op.simdflags & IFS_S16_F64:\n+ elif op.simdflags == IFS_S16_F64:\npass\n- elif op.simdflags & IFS_U32_F64:\n+ elif op.simdflags == IFS_U32_F64:\npass\n- elif op.simdflags & IFS_S32_F64:\n+ elif op.simdflags == IFS_S32_F64:\npass\n- elif op.simdflags & IFS_F32_U16:\n+ elif op.simdflags == IFS_F32_U16:\npass\n- elif op.simdflags & IFS_F32_S16:\n+ elif op.simdflags == IFS_F32_S16:\npass\n- elif op.simdflags & IFS_F32_U32:\n+ elif op.simdflags == IFS_F32_U32:\npass\n- elif op.simdflags & IFS_F32_S32:\n+ elif op.simdflags == IFS_F32_S32:\npass\n- elif op.simdflags & IFS_F64_U16:\n+ elif op.simdflags == IFS_F64_U16:\npass\n- elif op.simdflags & IFS_F64_S16:\n+ elif op.simdflags == IFS_F64_S16:\npass\n- elif op.simdflags & IFS_F64_U32:\n+ elif op.simdflags == IFS_F64_U32:\npass\n- elif op.simdflags & IFS_F64_S32:\n+ elif op.simdflags == IFS_F64_S32:\npass\nelif len(op.opers) == 2:\nfor reg in range(regcnt):\n#frac_bits = 64 - op.opers[1].val\n# pA8_866 (868?)\n- if op.simdflags & IFS_F32_S32:\n+ if op.simdflags == IFS_F32_S32:\npass\n- elif op.simdflags & IFS_F32_U32:\n+ elif op.simdflags == IFS_F32_U32:\npass\n- elif op.simdflags & IFS_S32_F32:\n+ elif op.simdflags == IFS_S32_F32:\npass\n- elif op.simdflags & IFS_U32_F32:\n+ elif op.simdflags == IFS_U32_F32:\npass\n# pA8-868 (870?)\n- elif op.simdflags & IFS_F64_S32:\n+ elif op.simdflags == IFS_F64_S32:\npass\n- elif op.simdflags & IFS_F64_U32:\n+ elif op.simdflags == IFS_F64_U32:\npass\n- elif op.simdflags & IFS_S32_F64:\n+ elif op.simdflags == IFS_S32_F64:\npass\n- elif op.simdflags & IFS_U32_F64:\n+ elif op.simdflags == IFS_U32_F64:\npass\n# pA8-874\n- elif op.simdflags & IFS_F64_F32:\n+ elif op.simdflags == IFS_F64_F32:\npass\n- elif op.simdflags & IFS_F32_F64:\n+ elif op.simdflags == IFS_F32_F64:\npass\n# pA8-876\n- elif op.simdflags & IFS_F16_F32:\n+ elif op.simdflags == IFS_F16_F32:\npass\n- elif op.simdflags & IFS_F32_F16:\n+ elif op.simdflags == IFS_F32_F16:\npass\nelse:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
IFS comments and fixes
|
718,770 |
26.06.2020 19:15:33
| 14,400 |
d7f829174a659055d96b57fd8ff56e59db825a7f
|
refactoring IfThen. it works like the manual states now.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -55,6 +55,19 @@ class CoProcEmulator: # useful for prototyping, but should be subclassed\nlogger.info(\"CoProcEmu(%s): mrrc(%r)\", self.ident, parms)\n+class FPProcessException(Exception):\n+ pass\n+\n+\n+class ITException(Exception):\n+ def __init__(self, va, itbase, itsize):\n+ self.va = va\n+ self.itbase = itbase\n+ self.itsize = itsize\n+\n+ def __repr__(self):\n+ return \"Error with Thumb IT state: va:0x%x ITSTATE: 0x%x/%x\" % (self.va, self.itbase, self.itsize)\n+\ndef _getRegIdx(idx, mode):\nif idx >= REGS_VECTOR_TABLE_IDX:\nreturn reg_table[idx]\n@@ -264,16 +277,52 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nself.setMeta('forrealz', True)\nnewpc = None\nstartpc = self.getProgramCounter()\n- skip = False\n- # IT block handling\n- if self.itcount:\n- self.itcount -= 1\n+ # IT block handling (THUMB mode only! Undefined in ARM mode!)\n+ # itbase will have the following process (see ARMv7 manual)\n+ # [7:5] [4] [3] [2] [1] [0]\n+ # cond_base P1 P2 P3 P4 1 Entry point for 4-instruction IT block\n+ # cond_base P1 P2 P3 1 0 Entry point for 3-instruction IT block\n+ # cond_base P1 P2 1 0 0 Entry point for 2-instruction IT block\n+ # cond_base P1 1 0 0 0 Entry point for 1-instruction IT block\n+ # 000 0 0 0 0 0 Normal execution, not in an IT block\n+\n+ itbase = self.getRegister(REG_IT_BASE)\n+ if itbase:\n+ # first a few sanity checks. we'll choose to survive the ARM mode,\n+ # but bail on odd IT flags.\n+ tmode = self.getFlag(PSR_T_bit)\n+ if not tmode:\n+ logger.warn(\"emulator: 0x%x: %r IT block in ARM mode\", op.va, op)\n+\n+ itcount = self.getRegister(REG_IT_SIZE)\n+ if not (itcount & 0xf):\n+ logger.warn(\"log: ITException: 0x%x 0x%x/%x: 0x%x\", op.va, self.getRegister(REG_IT_BASE), self.getRegister(REG_IT_SIZE), itcount)\n+ # this is undefined! should not be here.\n+ raise ITException(op.va, self.getRegister(REG_IT_BASE), self.getRegister(REG_IT_SIZE))\n+\n+ p1 = (itcount >> 4) & 1\n+\n+ # handle housekeeping. this should keep this clause from happening next\n+ # instruction, but doesn't indicate anything now.\n+ itcount <<= 1\n+ if not (itcount & 0xf): # bottom 4 bits must have at least 1 bit set\n+ # when done, reset all the IT flags to 0\n+ self.setRegister(REG_IT_BASE, 0)\n+ self.setRegister(REG_IT_SIZE, 0)\n+ else:\n+ self.setRegister(REG_IT_SIZE, itcount)\n- if not (self.itmask & 1):\n- skip = True\n- self.itmask >>= 1\n+ # evaluate the expression against the current state\n+ firstcond = self.getRegister(REG_IT_BASE)\n+ condcheck = conditionals[firstcond]\n+ condval = condcheck(self.getRegister(REG_FLAGS))\n+ # p1 indicates whether we're <firstcond> or <NOT firstcond>\n+ if not p1:\n+ condval = not condval\n+\n+ else:\n# standard conditional handling\ncondval = (op.prefixes >= 0xe)\n@@ -282,7 +331,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ncondval = condcheck(self.getRegister(REG_FLAGS))\n# the actual execution... if we're supposed to.\n- if condval and not skip:\n+ if condval:\nmeth = self.op_methods.get(op.mnem, None)\nif meth is None:\nraise envi.UnsupportedInstruction(self, op)\n@@ -1310,14 +1359,13 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\ni_vldr = i_mov\n- # TESTME: IT functionality\ndef i_it(self, op):\nif self.itcount:\nraise Exception(\"IT block within an IT block!\")\n- self.itcount, self.ittype, self.itmask = op.opers[0].getCondData()\n- condcheck = conditionals[self.ittype]\n- self.itva = op.va\n+ itbase, itsize = op.opers[0].getITSTATEdata()\n+ self.setRegister(REG_IT_BASE, itbase)\n+ self.setRegister(REG_IT_SIZE, itsize)\ni_ite = i_it\ni_itt = i_it\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/regs.py",
"new_path": "envi/archs/arm/regs.py",
"diff": "@@ -134,7 +134,8 @@ PSR_Z = 30 # zero\nPSR_C = 29 # carry\nPSR_V = 28 # oVerflow\nPSR_Q = 27\n-PSR_IT = 25\n+PSR_IT_BASE = 25\n+PSR_IT_SIZE = 10\nPSR_J = 24\nPSR_DNM = 20\nPSR_GE = 16\n@@ -172,14 +173,14 @@ psr_fields[PSR_DNM+1] = \"DNM+1\"\npsr_fields[PSR_DNM+2] = \"DNM+2\"\npsr_fields[PSR_DNM+3] = \"DNM+3\"\npsr_fields[PSR_J] = \"J\"\n-psr_fields[PSR_IT] = \"IT\"\n-psr_fields[PSR_IT+1] = \"IT+1\"\n-psr_fields[PSR_IT-15] = \"IT+2\" # IT is split into two sections\n-psr_fields[PSR_IT-14] = \"IT+3\"\n-psr_fields[PSR_IT-13] = \"IT+4\"\n-psr_fields[PSR_IT-12] = \"IT+5\"\n-psr_fields[PSR_IT-11] = \"IT+6\"\n-psr_fields[PSR_IT-10] = \"IT+7\"\n+psr_fields[PSR_IT_BASE] = \"IT_BASE\"\n+psr_fields[PSR_IT_BASE+1] = \"IT_BASE+1\"\n+psr_fields[PSR_IT_BASE+2] = \"IT_BASE+2\"\n+psr_fields[PSR_IT_SIZE] = \"IT_SIZE\" # IT is split into two sections\n+psr_fields[PSR_IT_SIZE+1] = \"IT_SIZE+1\" # IT is split into two sections\n+psr_fields[PSR_IT_SIZE+2] = \"IT_SIZE+2\" # IT is split into two sections\n+psr_fields[PSR_IT_SIZE+3] = \"IT_SIZE+3\" # IT is split into two sections\n+psr_fields[PSR_IT_SIZE+4] = \"IT_SIZE+4\" # IT is split into two sections\npsr_fields[PSR_Q] = \"Q\"\npsr_fields[PSR_V] = \"V\"\npsr_fields[PSR_C] = \"C\"\n@@ -195,14 +196,16 @@ arm_status_metas = [\n(\"J\", REG_FLAGS, PSR_J, 1, \"Jazelle Mode bit\"),\n(\"GE\",REG_FLAGS, PSR_GE, 4, \"Greater/Equal flag\"),\n(\"DNM\",REG_FLAGS, PSR_DNM, 4, \"DO NOT MODIFY bits\"),\n- (\"IT0\",REG_FLAGS, PSR_IT, 1, \"IfThen 0 bit\"),\n- (\"IT1\",REG_FLAGS, PSR_IT+1, 1, \"IfThen 1 bit\"),\n- (\"IT2\",REG_FLAGS, PSR_IT+2, 1, \"IfThen 2 bit\"),\n- (\"IT3\",REG_FLAGS, PSR_IT+3, 1, \"IfThen 3 bit\"),\n- (\"IT4\",REG_FLAGS, PSR_IT+4, 1, \"IfThen 4 bit\"),\n- (\"IT5\",REG_FLAGS, PSR_IT+5, 1, \"IfThen 5 bit\"),\n- (\"IT6\",REG_FLAGS, PSR_IT+6, 1, \"IfThen 6 bit\"),\n- (\"IT7\",REG_FLAGS, PSR_IT+7, 1, \"IfThen 7 bit\"),\n+ (\"IT_BASE0\",REG_FLAGS, PSR_IT_BASE, 1, \"IfThen 0 bit\"),\n+ (\"IT_BASE1\",REG_FLAGS, PSR_IT_BASE+1, 1, \"IfThen 1 bit\"),\n+ (\"IT_BASE2\",REG_FLAGS, PSR_IT_BASE+2, 1, \"IfThen 2 bit\"),\n+ (\"IT_SIZE0\",REG_FLAGS, PSR_IT_SIZE, 1, \"IfThen 0 bit\"),\n+ (\"IT_SIZE1\",REG_FLAGS, PSR_IT_SIZE+1, 1, \"IfThen 1 bit\"),\n+ (\"IT_SIZE2\",REG_FLAGS, PSR_IT_SIZE+2, 1, \"IfThen 2 bit\"),\n+ (\"IT_SIZE3\",REG_FLAGS, PSR_IT_SIZE+3, 1, \"IfThen 3 bit\"),\n+ (\"IT_SIZE4\",REG_FLAGS, PSR_IT_SIZE+4, 1, \"IfThen 4 bit\"),\n+ ('IT_SIZE',REG_FLAGS, PSR_IT_SIZE, 5, \"IfThen Block Size\"),\n+ ('IT_BASE',REG_FLAGS, PSR_IT_BASE, 3, \"IfThen Base Condition\"),\n(\"E\", REG_FLAGS, PSR_E, 1, \"Data Endian bit\"),\n(\"A\", REG_FLAGS, PSR_A, 1, \"Imprecise Abort Disable bit\"),\n(\"I\", REG_FLAGS, PSR_I, 1, \"IRQ disable bit\"),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -592,9 +592,9 @@ def it_hints(va, val):\nitoper = ThumbITOper(mask, firstcond)\ncount, cond, data = itoper.getCondData()\nnextfew = it_strs[count][data]\n- mnem = 'it' + nextfew\n+ mnem = 'it' + nextfew # as much as it pains me to strcat here.\n- return COND_AL,(itoper,), 0, None, mnem\n+ return COND_AL,(itoper,), 0, INS_IT, mnem\nopcode, mnem = it_hints_others[firstcond]\n@@ -624,15 +624,18 @@ class ThumbITOper(ArmOperand):\nfiz = self.firstcond & 1\nflags = 1\ncount = self.getCondInstrCount()\n- print bin(fiz), bin(self.mask)\n+ #print bin(fiz), bin(self.mask)\nfor x in range(count):\nbit = bool(((self.mask>>(3-x))&1) == fiz)\n- print x, bit, bin(flags)\n+ #print x, bit, bin(flags)\nflags |= (bit << (x+1))\nreturn flags\ndef getCondData(self):\n+ '''\n+ deprecated: 2020-06-24\n+ '''\nmask = self.mask\ncond = self.firstcond\ncount = 0\n@@ -653,14 +656,19 @@ class ThumbITOper(ArmOperand):\nreturn count, self.firstcond, data\n+ def getITSTATEdata(self):\n+ '''\n+ this is the data to put into the ITSTATE register (1 byte of the CPSR)\n+ '''\n+ return self.firstcond, self.mask\n+\ndef repr(self, op):\nmask = self.mask\ncount, cond, data = self.getCondData()\nfcond = cond_codes.get(cond)\n- nextfew = it_strs[count][data]\n- return \"%s %s\" % (nextfew, fcond)\n+ return \"%s\" % (fcond)\ndef render(self, mcanv, op, idx):\nmask = self.mask\n@@ -668,8 +676,7 @@ class ThumbITOper(ArmOperand):\ncount, cond, data = self.getCondData()\nfcond = cond_codes.get(cond)\n- nextfew = it_strs[count][data]\n- mcanv.addText(\"%s %s\" % (nextfew, fcond))\n+ mcanv.addText(\"%s\" % (fcond))\ndef getOperValue(self, idx, emu=None):\nreturn None\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
refactoring IfThen. it works like the manual states now.
|
718,770 |
26.06.2020 22:31:38
| 14,400 |
85f53e9f3a3a0f3647e29aca4153cd948f11ef0b
|
logging line for ELFPLT analysis
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -33,6 +33,7 @@ def analyzePLT(vw, ssva, ssize):\nbranchvas = []\nwhile sva < nextseg:\n+ logger.debug('analyzePLT(0x%x, 0x%x) first pass: sva: 0x%x nextseg: 0x%x', ssva, ssize, sva, nextseg)\nif vw.getLocation(sva) is None:\nlogger.info('making code: 0x%x', sva)\ntry:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
logging line for ELFPLT analysis
|
718,765 |
27.07.2020 17:18:32
| 14,400 |
bd1f0ccd35c337c31badd22cbbcc2357db556875
|
Address issue makeName being passed none
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -2268,6 +2268,9 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\nbaseva = self.getFunction(va)\nbasename = self.name_by_va.get(baseva, None)\n+ if self.isFunction(va):\n+ basename = 'sub_0%x' % va\n+\n# by filename\nif basename is None:\nbasename = self.getFileByVa(va)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/base.py",
"new_path": "vivisect/base.py",
"diff": "@@ -381,6 +381,9 @@ class VivWorkspaceCore(object, viv_impapi.ImportApi):\nif self.isFunction(va):\nfnode = self._call_graph.getFunctionNode(va)\n+ if name is None:\n+ self._call_graph.delNodeProp(fnode, 'repr')\n+ else:\nself._call_graph.setNodeProp(fnode, 'repr', name)\ndef _handleADDMMAP(self, einfo):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/tests/testvivisect.py",
"new_path": "vivisect/tests/testvivisect.py",
"diff": "@@ -159,3 +159,24 @@ class VivisectTest(unittest.TestCase):\ndef test_posix_impapi(self):\npass\n+\n+ def test_make_noname(self):\n+ vw = self.vdir_vw\n+ name = 'TheBinaryAnalysisPlantsCrave'\n+ va = 0x08058691\n+ vw.makeName(va, name)\n+ self.assertEqual(vw.getName(va), name)\n+\n+ vw.makeName(va, None)\n+ self.assertIsNone(vw.getName(va))\n+ self.assertEqual(vw.getName(va, smart=True), 'vdir.rpl_mbrtowc+0x31')\n+\n+ fva = 0x08058660\n+ oldname = vw.getName(fva)\n+ self.assertEqual(oldname, 'vdir.rpl_mbrtowc')\n+ vw.makeName(fva, None)\n+ noname = 'sub_0%x' % fva\n+ self.assertEqual(vw.getName(fva), None)\n+ self.assertEqual(vw.getName(fva, smart=True), noname)\n+ # set it back just in case\n+ vw.makeName(fva, oldname)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Address issue #90, makeName being passed none (#295)
|
718,765 |
03.08.2020 17:14:03
| 14,400 |
385798a0d25bef2f17c57b19631a3b526a785aa4
|
save work and move init files to new pr
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -2581,7 +2581,7 @@ class VivWorkspace(e_mem.MemoryObject, viv_base.VivWorkspaceCore):\ndef getLocationDistribution(self):\n# NOTE: if this changes, don't forget the report module!\n- totsize = float(0)\n+ totsize = 0\nfor mapva, mapsize, mperm, mname in self.getMemoryMaps():\ntotsize += mapsize\nloctot = 0\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/tests/testvivisect.py",
"new_path": "vivisect/tests/testvivisect.py",
"diff": "import io\nimport unittest\n+import envi\n+\nimport vivisect\n+import vivisect.exc as v_exc\n+import vivisect.const as v_const\nimport vivisect.tests.helpers as helpers\n@@ -10,6 +14,107 @@ class VivisectTest(unittest.TestCase):\ndef setUpClass(cls):\ncls.chgrp_vw = helpers.getTestWorkspace('linux', 'i386', 'chgrp.llvm')\ncls.vdir_vw = helpers.getTestWorkspace('linux', 'i386', 'vdir.llvm')\n+ cls.gcc_vw = helpers.getTestWorkspace('linux', 'amd64', 'gcc-7')\n+\n+ def test_basic_apis(self):\n+ '''\n+ Test a bunch of the simpler workspace APIs\n+ '''\n+ vw = self.gcc_vw\n+ self.assertEqual(set(['Emulation Anomalies', 'EntryPoints', 'WeakSymbols', 'FileSymbols', 'SwitchCases', 'EmucodeFunctions', 'PointersFromFile', 'FuncWrappers', 'CodeFragments', 'DynamicBranches', 'Bookmarks', 'NoReturnCalls']), set(vw.getVaSetNames()))\n+\n+ vw.getPrevLocation()\n+ vw.getRenderInfo()\n+ self.assertEqual((0x449e10, 1, v_const.LOC_OP, envi.ARCH_AMD64), vw.getLocationByName('gcc_7.main'))\n+ vw.getLocationRange()\n+ vw.getLocations()\n+ vw.getFunctionBlocks()\n+\n+ # tuples are Name, Number of Locations, Size in bytes, Percentage of space\n+ ans = {0: ('Undefined', 0, 517544, 49),\n+ 1: ('Num/Int', 271, 1724, 0),\n+ 2: ('String', 4054, 153424, 14),\n+ 3: ('Unicode', 0, 0, 0),\n+ 4: ('Pointer', 5376, 43008, 4),\n+ 5: ('Opcode', 79516, 323664, 30),\n+ 6: ('Structure', 496, 11544, 1),\n+ 7: ('Clsid', 0, 0, 0),\n+ 8: ('VFTable', 0, 0, 0),\n+ 9: ('Import Entry', 141, 1128, 0),\n+ 10: ('Pad', 0, 0, 0)}\n+ dist = vw.getLocationDistribution()\n+ for loctype, locdist in dist.items():\n+ self.assertEqual(locdist, ans[loctype])\n+\n+ def test_repr(self):\n+ vw = self.gcc_vw\n+ ans = [\n+ (5040784, \"'Perform IPA Value Range Propagation.\\\\x00'\"),\n+ (4853125, \"'-fira-algorithm=\\\\x00'\"),\n+ (5040824, \"'-fira-algorithm=[CB|priority]\\\\tSet the used IRA algorithm.\\\\x00'\"),\n+ (4853142, \"'-fira-hoist-pressure\\\\x00'\"),\n+ (4853163, \"'-fira-loop-pressure\\\\x00'\"),\n+ (4853183, \"'-fira-region=\\\\x00'\"),\n+ (5041032, \"'-fira-region=[one|all|mixed]\\\\tSet regions for IRA.\\\\x00'\"),\n+ (4853197, \"'-fira-share-save-slots\\\\x00'\"),\n+ (5041088, \"'Share slots for saving different hard registers.\\\\x00'\"),\n+ (4853220, \"'-fira-share-spill-slots\\\\x00'\"),\n+ (5041144, \"'Share stack slots for spilled pseudo-registers.\\\\x00'\"),\n+ (4853244, \"'-fira-verbose=\\\\x00'\"),\n+ (5041264, \"'-fisolate-erroneous-paths-attribute\\\\x00'\"),\n+ (7345392, '4 BYTES: 0 (0x0000)'),\n+ (7345376, '8 BYTES: 0 (0x00000000)'),\n+ (5122144, '16 BYTES: 21528975894082904090066538856997790465 (0x1032547698badcfeefcdab8967452301)'),\n+ (7346240, 'BYTE: 0 (0x0)'),\n+ (7331776, 'IMPORT: *.__pthread_key_create'),\n+ (7331784, 'IMPORT: *.__libc_start_main'),\n+ (7331792, 'IMPORT: *.calloc'),\n+ (7331800, 'IMPORT: *.__gmon_start__'),\n+ (7331808, 'IMPORT: *.stderr'),\n+ (7331864, 'IMPORT: *.__strcat_chk'),\n+ (7331872, 'IMPORT: *.__uflow'),\n+ (7331880, 'IMPORT: *.mkstemps'),\n+ (7331888, 'IMPORT: *.getenv'),\n+ (7331896, 'IMPORT: *.dl_iterate_phdr'),\n+ (7331904, 'IMPORT: *.__snprintf_chk'),\n+ (7331912, 'IMPORT: *.free'),\n+ (4697393, 'mov rdx,qword [rsp + 8]'),\n+ (4697398, 'jmp 0x0047ab49'),\n+ (4749920, 'mov qword [rdi + 152],rsi'),\n+ (4749927, 'ret '),\n+ (4698912, 'sub rsp,8'),\n+ (4698916, 'call 0x0047b310'),\n+ (4698921, 'mov rdi,rax'),\n+ (4698924, 'call 0x0047b2f0'),\n+ (4698929, 'cs: nop word [rax + rax]'),\n+ (4698939, 'nop dword [rax + rax]'),\n+ (4698944, 'test rdi,rdi'),\n+ (4698947, 'push rbx'),\n+ (4698948, 'jz 0x0047b361'),\n+ (4698950, 'mov rbx,rdi'),\n+ (4698953, 'call 0x0047a450'),\n+ (4698958, 'mov rax,0xb8b1aabcbcd4d500'),\n+ ]\n+ for va, disp in ans:\n+ self.assertEqual(disp, vw.reprVa(va))\n+\n+ def test_naughty(self):\n+ '''\n+ Test us some error conditions\n+ '''\n+ vw = self.gcc_vw\n+ with self.assertRaises(v_exc.InvalidLocation):\n+ vw.delLocation(0x51515151)\n+\n+ with self.assertRaises(v_exc.InvalidFunction):\n+ vw.setFunctionMeta(0xdeadbeef, 'monty', 'python')\n+\n+ withs self.assertRaises(v_exc.InvalidLocation):\n+ vw.getLocationByName(0xabad1dea)\n+\n+ def test_basic_callers(self):\n+ vw.getXrefs()\n+ vw.getImportCallers()\ndef test_consecutive_jump_table(self):\nprimaryJumpOpVa = 0x804c9b6\n@@ -25,6 +130,10 @@ class VivisectTest(unittest.TestCase):\nself.assertEqual(len(prefs), 3)\ncmnt = self.chgrp_vw.getComment(0x804c9bd)\nself.assertEqual(cmnt, 'Other Case(s): 2, 6, 8, 11, 15, 20, 21, 34, 38, 40, 47')\n+\n+ cmnts = self.chgrp_vw.getComments()\n+ self.assertTrue(len(cmnts) > 1)\n+\n# 13 actual codeblocks and 1 xref to the jumptable itself\nsrefs = self.chgrp_vw.getXrefsFrom(secondJumpOpVa)\nself.assertEqual(len(srefs), 14)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/tools/graphutil.py",
"new_path": "vivisect/tools/graphutil.py",
"diff": "@@ -422,8 +422,8 @@ def getOpsFromPath(vw, fgraph, path):\n'''\nRetrieve the opcodes for a given path.\n- #FIXME cache opcodes in function graph for replay speed\n'''\n+ # FIXME cache opcodes in function graph for replay speed\nret = []\nfor nid,eid in path:\nnode = fgraph.getNode(nid)\n"
},
{
"change_type": "MODIFY",
"old_path": "vstruct/builder.py",
"new_path": "vstruct/builder.py",
"diff": "@@ -15,9 +15,10 @@ prim_types = [ None,\nvs_prim.v_uint16,\nNone,\nvs_prim.v_uint32,\n- None, None, None,\n- vs_prim.v_uint64\n- ]\n+ None,\n+ None,\n+ None,\n+ vs_prim.v_uint64]\n# VStruct Field Flags\nVSFF_POINTER = 1\n@@ -33,7 +34,7 @@ class VStructConstructor:\nclass VStructBuilder:\ndef __init__(self, defs=(), enums=()):\n- self._vs_defs = {}\n+ self._vs_defs = {} # name, size, kids\nself._vs_ctors = {}\nself._vs_enums = {}\nself._vs_namespaces = {}\n@@ -100,6 +101,7 @@ class VStructBuilder:\nreturn ret\ndef addVStructDef(self, vsdef):\n+ # TODO: if we see a dot in the name, should we automagically create a namespace?\nvsname = vsdef[0]\nself._vs_defs[vsname] = vsdef\n"
},
{
"change_type": "MODIFY",
"old_path": "vstruct/cparse.py",
"new_path": "vstruct/cparse.py",
"diff": "@@ -48,9 +48,11 @@ class StructParser:\nself.vs_ctypes.update({\n('long',): vs_prim.v_int64,\n('long', 'int'): vs_prim.v_int64,\n+ ('long', 'long'): vs_prim.v_int64,\n('unsigned', 'long',): vs_prim.v_uint64,\n('unsigned', 'long', 'int'): vs_prim.v_uint64,\n+ ('unsigned', 'long', 'long'): vs_prim.v_uint64,\n})\ndef _getVsChildElements(self, astelem):\n"
},
{
"change_type": "MODIFY",
"old_path": "vstruct/primitives.py",
"new_path": "vstruct/primitives.py",
"diff": "@@ -25,6 +25,7 @@ class v_bitmask(object):\n'''Returns a list of names where apply the AND of the mask and val is non-zero'''\nreturn [v for k, v in self._vs_reverseMap.items() if (val & k) != 0]\n+\nclass v_base(object):\ndef __init__(self):\nself._vs_meta = {}\n@@ -36,10 +37,18 @@ class v_base(object):\nself._vs_meta[name] = value\n# Sub-classes (primitive base, or VStruct must have these\n- def vsParse(self, bytes): return NotImplemented\n- def vsCalculate(self): pass\n- def vsIsPrim(self): return NotImplemented\n- def vsGetTypeName(self): return NotImplemented\n+ def vsParse(self, bytes):\n+ return NotImplemented\n+\n+ def vsCalculate(self):\n+ pass\n+\n+ def vsIsPrim(self):\n+ return NotImplemented\n+\n+ def vsGetTypeName(self):\n+ return NotImplemented\n+\nclass v_prim(v_base):\ndef __init__(self):\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "vstruct/tests/test_builder.py",
"diff": "+import os\n+import binascii\n+import unittest\n+\n+import vstruct\n+import vstruct.cparse as vs_cparse\n+import vstruct.builder as vs_builder\n+\n+\n+csrc_simple = '''\n+struct monty {\n+ int life;\n+ char of;\n+ long brian;\n+};\n+'''\n+\n+csrc_nested = '''\n+struct python {\n+ unsigned short meaning;\n+ struct andthe {\n+ unsigned long int of;\n+ char life[20];\n+ } holygrail;\n+ int hollywood[64];\n+ unsigned char bow[5];\n+};\n+'''\n+\n+\n+class VstructBuilderTest(unittest.TestCase):\n+\n+ def test_init(self):\n+ simple = vs_cparse.ctorFromCSource(csrc_simple)\n+ nested = vs_cparse.ctorFromCSource(csrc_nested)\n+\n+ bldr = vs_builder.VStructBuilder()\n+ bldr.addVStructCtor('pe.simple', simple)\n+ bldr.addVStructCtor('elf.nested', nested)\n+ self.assertEqual(set(['pe.simple', 'elf.nested']), set(bldr.getVStructNames()))\n+\n+ bldr.delVStructCtor('elf.nested')\n+ self.assertEqual(['pe.simple'], bldr.getVStructNames())\n+\n+ def test_constructor(self):\n+ pass\n+\n+ def test_namespaces(self):\n+ simple = vs_cparse.ctorFromCSource(csrc_simple)\n+ nested = vs_cparse.ctorFromCSource(csrc_nested)\n+ bldr = vs_builder.VStructBuilder()\n+ subb = vs_builder.VStructBuilder()\n+\n+ bldr.addVStructNamespace('subname', subb)\n+ bldr.addVStructNamespace('dupname', subb)\n+\n+ self.assertTrue(bldr.hasVStructNamespace('subname'))\n+ self.assertEqual(set(bldr.getVStructNamespaces()), set([('subname', subb), ('dupname', subb)]))\n+\n+ def test_build_vstruct(self):\n+ bldr = vs_builder.VStructBuilder()\n+\n+ def test_get_pycode(self):\n+ pass\n"
},
{
"change_type": "MODIFY",
"old_path": "vstruct/tests/testbasic.py",
"new_path": "vstruct/tests/testbasic.py",
"diff": "@@ -17,9 +17,6 @@ class woot(vstruct.VStruct):\nclass VStructTest(unittest.TestCase):\n- #def setUp(self):\n- #def tearDown(self):\n-\ndef test_vstruct_basicstruct(self):\nv = vstruct.VStruct()\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/win32.py",
"new_path": "vtrace/platforms/win32.py",
"diff": "@@ -2108,7 +2108,6 @@ class Win32SymbolParser:\nreturn si\ndef symInit(self):\n-\ndbghelp.SymInitialize(self.phandle, self.sympath, False)\ndbghelp.SymSetOptions(self.symopts)\n"
},
{
"change_type": "DELETE",
"old_path": "vtrace/platforms/windll/__init__.py",
"new_path": "vtrace/platforms/windll/__init__.py",
"diff": ""
},
{
"change_type": "DELETE",
"old_path": "vtrace/platforms/windll/amd64/__init__.py",
"new_path": "vtrace/platforms/windll/amd64/__init__.py",
"diff": ""
},
{
"change_type": "DELETE",
"old_path": "vtrace/platforms/windll/i386/__init__.py",
"new_path": "vtrace/platforms/windll/i386/__init__.py",
"diff": ""
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
save work and move init files to new pr
|
718,765 |
04.08.2020 11:14:29
| 14,400 |
cdfbb1e2ca85d002b749da29977c2ded9a25714f
|
intel opcode maps
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "@@ -1040,6 +1040,16 @@ tbl32_660F38[0x23] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | O\ntbl32_660F38[0x24] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_D | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovsxwq\", 0, 0, 0)\ntbl32_660F38[0x25] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_Q | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovsxdq\", 0, 0, 0)\n+tbl32_660F38[0x28] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pmuldq\", 0, 0, 0)\n+tbl32_660F38[0x29] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pcmpeqq\", 0, 0, 0)\n+tbl32_660F38[0x2A] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_M | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"movntdqa\", 0, 0, 0)\n+tbl32_660F38[0x2B] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"packusdw\", 0, 0, 0)\n+tbl32_660F38[0x2C] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_M | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"maskmovps\", 0, 0, 0)\n+tbl32_660F38[0x2D] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_M | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"maskmovpd\", 0, 0, 0)\n+tbl32_660F38[0x2E] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_M | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_V | OPTYPE_x | OP_W, ARG_NONE, cpu_AMD64, \"maskmovps\", 0, 0, 0)\n+tbl32_660F38[0x2F] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_M | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_V | OPTYPE_x | OP_W, ARG_NONE, cpu_AMD64, \"maskmovpd\", 0, 0, 0)\n+\n+\n# TODO: There's a ymm version on this one that has a memory size of 128. Dammit\ntbl32_660F38[0x30] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_Q | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovzxbw\", 0, 0, 0)\ntbl32_660F38[0x31] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_D | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovzxbd\", 0, 0, 0)\n@@ -1047,7 +1057,14 @@ tbl32_660F38[0x32] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | O\ntbl32_660F38[0x33] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_Q | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovzxwd\", 0, 0, 0)\ntbl32_660F38[0x34] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_D | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovzxwq\", 0, 0, 0)\ntbl32_660F38[0x35] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_Q | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovzxdq\", 0, 0, 0)\n-\n+tbl32_660F38[0x36] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"permd\", 0, 0, 0)\n+tbl32_660F38[0x37] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pcmpgtq\", 0, 0, 0)\n+tbl32_660F38[0x38] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pminsb\", 0, 0, 0)\n+tbl32_660F38[0x39] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pminsd\", 0, 0, 0)\n+tbl32_660F38[0x3A] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pminuw\", 0, 0, 0)\n+tbl32_660F38[0x3B] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pminud\", 0, 0, 0)\n+tbl32_660F38[0x3C] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pmaxsb\", 0, 0, 0)\n+tbl32_660F38[0x3D] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pmaxsd\", 0, 0, 0)\ntbl32_660F38[0x3E] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pmaxuw\", 0, 0, 0)\ntbl32_660F38[0x3F] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"pmaxud\", 0, 0, 0)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opcode86.py",
"new_path": "envi/archs/i386/opcode86.py",
"diff": "@@ -816,6 +816,7 @@ tbl32_0F01_rest = [\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n+# 0f01e0\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n@@ -830,7 +831,7 @@ tbl32_0F01_rest = [\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n-(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n+(0, INS_SYSTEM, OP_REG | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2, \"rdpkru\", e_i386_regs.REG_EAX, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, INS_OTHER, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, \"swapgs\", 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n@@ -932,6 +933,12 @@ tbl32_660F38[0x22] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | O\ntbl32_660F38[0x23] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovsxwd\", 0, 0, 0)\ntbl32_660F38[0x24] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovsxwq\", 0, 0, 0)\ntbl32_660F38[0x25] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovsxdq\", 0, 0, 0)\n+\n+tbl32_660F38[0x28] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pmuldq\", 0, 0, 0)\n+tbl32_660F38[0x29] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pcmpeqq\", 0, 0, 0)\n+tbl32_660F38[0x2A] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_M | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"movntdqa\", 0, 0, 0)\n+tbl32_660F38[0x2B] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"packusdw\", 0, 0, 0)\n+\ntbl32_660F38[0x30] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovzxbw\", 0, 0, 0)\ntbl32_660F38[0x31] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovzxbd\", 0, 0, 0)\ntbl32_660F38[0x32] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_w | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovzxbq\", 0, 0, 0)\n@@ -939,6 +946,16 @@ tbl32_660F38[0x33] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | O\ntbl32_660F38[0x34] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovzxwq\", 0, 0, 0)\ntbl32_660F38[0x35] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovzxdq\", 0, 0, 0)\n+tbl32_660F38[0x37] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pcmpgtq\", 0, 0, 0)\n+tbl32_660F38[0x38] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pminsb\", 0, 0, 0)\n+tbl32_660F38[0x39] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pminsd\", 0, 0, 0)\n+tbl32_660F38[0x3A] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pminuw\", 0, 0, 0)\n+tbl32_660F38[0x3B] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pminud\", 0, 0, 0)\n+tbl32_660F38[0x3C] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pmaxsb\", 0, 0, 0)\n+tbl32_660F38[0x3D] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pmaxsd\", 0, 0, 0)\n+tbl32_660F38[0x3E] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pmaxuw\", 0, 0, 0)\n+tbl32_660F38[0x3F] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pmaxud\", 0, 0, 0)\n+\ntbl32_660F38[0x1c] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsb\", 0, 0, 0)\ntbl32_660F38[0x1d] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsw\", 0, 0, 0)\ntbl32_660F38[0x1e] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsd\", 0, 0, 0)\n@@ -1162,8 +1179,8 @@ tbl32_0FC7_rest = [\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n-(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n-(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n+(0, INS_SYSTEM, ADDRMETH_R | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, 0, 'rdrand', 0, 0, 0),\n+(0, INS_SYSTEM, ADDRMETH_R | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, 0, 'rdseed', 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n]\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
intel opcode maps (#299)
|
718,765 |
05.08.2020 10:32:41
| 14,400 |
659366fabca57386793099a9da2c97260a149451
|
exception naming
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/disasm.py",
"new_path": "envi/archs/arm/disasm.py",
"diff": "@@ -4143,8 +4143,9 @@ class ArmRegOper(ArmOperand):\nif elmtsz is None:\nelmtsz = self.getWidth()\n- ifmt = e_bits.getFormat(emu.getEndian(), elmtsz)\n- ffmt = e_bits.getFloatFormat(emu.getEndian(), elmtsz)\n+ # TODO: signed?\n+ ifmt = e_bits.getFormat(elmtsz, big_endian=emu.getEndian()==ENDIAN_MSB)\n+ ffmt = e_bits.getFloatFormat(elmntsz, big_endian=emu.getEndian()==ENDIAN_MSB)\n# get the 16-/32-/64-bit integer value\nmetaval = emu.getRegister(self.reg)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/amd64/emulation.py",
"new_path": "vivisect/analysis/amd64/emulation.py",
"diff": "-import sys\n-\n-import vivisect\n+import vivisect.exc as v_exc\nimport vivisect.impemu as viv_imp\nimport vivisect.impemu.monitor as viv_monitor\nimport envi\nimport envi.archs.amd64 as e_amd64\n-from envi.registers import RMETA_NMASK\nfrom vivisect.const import *\n@@ -25,7 +22,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\ndef prehook(self, emu, op, starteip):\nif op in self.badops:\n- raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (starteip, repr(op) ))\n+ raise v_exc.BadOpBytes(op.va)\nviv_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -2,6 +2,7 @@ import sys\nimport logging\nimport vivisect\n+import vivisect.exc as v_exc\nimport vivisect.impemu.monitor as viv_monitor\nimport vivisect.analysis.generic.codeblocks as viv_cb\n@@ -9,7 +10,6 @@ import envi\nimport envi.archs.arm as e_arm\nfrom envi.archs.arm.regs import *\n-from envi.registers import RMETA_NMASK\nfrom envi.archs.arm.const import *\nfrom vivisect.const import *\n@@ -38,7 +38,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\n#if self.verbose: print( \"tmode: %x emu: 0x%x flags: 0x%x \\t %r\" % (tmode, starteip, op.iflags, op))\nif op in self.badops:\nemu.stopEmu()\n- raise Exception(\"Hit known BADOP at 0x%.8x %s (fva: 0x%x)\" % (starteip, repr(op), self.fva))\n+ raise v_exc.BadOpBytes(op.va)\nviv_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/emucode.py",
"new_path": "vivisect/analysis/generic/emucode.py",
"diff": "@@ -6,6 +6,7 @@ if they are code by emulation behaviorial analysis.\n\"\"\"\nimport envi\nimport vivisect\n+import vivisect.exc as v_exc\nfrom envi.archs.i386.opconst import *\nimport vivisect.impemu.monitor as viv_imp_monitor\n@@ -71,7 +72,7 @@ class watcher(viv_imp_monitor.EmulationMonitor):\nif op in self.badops:\nemu.stopEmu()\n- raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (eip,repr(op)))\n+ raise v_exc.BadOpBytes(op.va)\nif op.iflags & envi.IF_RET:\nself.hasret = True\n@@ -83,7 +84,7 @@ class watcher(viv_imp_monitor.EmulationMonitor):\nif self.vw.isFunction(eip):\nemu.stopEmu()\n# FIXME: this is a problem. many time legit code falls into other functions... \"hydra\" functions are more and more common.\n- raise Exception(\"Fell Through Into Function: %.8x\" % eip)\n+ raise v_exc.BadOpBytes(op.va)\nloc = self.vw.getLocation(eip)\nif loc != None:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/pointers.py",
"new_path": "vivisect/analysis/generic/pointers.py",
"diff": "@@ -54,7 +54,7 @@ def analyze(vw):\n# Now, lets find likely free-hanging pointers\nfor addr, pval in vw.findPointers():\n- if vw.isDeadData(pval):\n+ if vw.isDeadData(pval) or vw.isLocation(addr):\ncontinue\ntry:\nlogger.info('pointer(4): 0x%x -> 0x%x', addr, pval)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/calling.py",
"new_path": "vivisect/analysis/i386/calling.py",
"diff": "@@ -7,6 +7,7 @@ import collections\nimport vivisect.impemu.monitor as viv_imp_monitor\n+import vivisect.exc as v_exc\nfrom vivisect.const import *\nimport vivisect.analysis.generic.switchcase as vag_switch\n@@ -47,7 +48,7 @@ class AnalysisMonitor(viv_imp_monitor.AnalysisMonitor):\ndef prehook(self, emu, op, starteip):\nif op in self.badops:\n- raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (starteip, repr(op) ))\n+ raise v_exc.BadOpBytes(op.va)\nviv_imp_monitor.AnalysisMonitor.prehook(self, emu, op, starteip)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/i386/instrhook.py",
"new_path": "vivisect/analysis/i386/instrhook.py",
"diff": "@@ -5,6 +5,7 @@ This module should be run after codeblocks analyis pass.\n\"\"\"\nimport envi\n+import vivisect.exc as v_exc\nimport vivisect.impemu.monitor as viv_imp_monitor\nverbose = False\n@@ -28,7 +29,7 @@ class instrhook_watcher (viv_imp_monitor.EmulationMonitor):\ndef prehook(self, emu, op, eip):\nif op in self.badops:\nemu.stopEmu()\n- raise Exception(\"Hit known BADOP at 0x%.8x %s\" % (eip, repr(op)))\n+ raise v_exc.BadOpBytes(op.va)\nif op.mnem in STOS:\nif self.arch == 'i386':\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/exc.py",
"new_path": "vivisect/exc.py",
"diff": "@@ -20,9 +20,13 @@ class InvalidFunction(Exception):\nException.__init__(self, \"VA 0x%.8x is not a function\" % va)\nclass InvalidCodeBlock(Exception):\n- def __init__(self, cbva):\n+ def __init__(self, va):\nException.__init__(self, 'VA 0x%.8x is not in a code block!' % va)\n+class BadOpBytes(Exception):\n+ def __init__(self, va):\n+ Exception.__init__(self, 'Hit known badop bytes at va 0x%.8x ' % va)\n+\nclass UnknownCallingConvention(Exception):\ndef __init__(self, fva, cc=None):\nException.__init__(self, \"Function 0x%.8x has unknown CallingConvention: %s\" % (fva, cc))\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -8,6 +8,8 @@ import envi.memory as e_mem\nimport visgraph.pathcore as vg_path\n+import vivisect.exc as v_exc\n+\nfrom vivisect.const import *\nimport logging\n@@ -359,6 +361,8 @@ class WorkspaceEmulator:\nif self.emumon:\ntry:\nself.emumon.prehook(self, op, starteip)\n+ except v_exc.BadOpBytes as e:\n+ logger.debug(str(e))\nexcept Exception as e:\nif not self.getMeta('silent'):\nlogger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon prehook)\", funcva, starteip, op, e)\n@@ -374,6 +378,8 @@ class WorkspaceEmulator:\nif self.emumon:\ntry:\nself.emumon.posthook(self, op, endeip)\n+ except v_exc.BadOpBytes as e:\n+ logger.debug(str(e))\nexcept Exception as e:\nif not self.getMeta('silent'):\nlogger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon posthook)\", funcva, starteip, op, e)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
exception naming
|
718,765 |
13.08.2020 00:00:10
| 14,400 |
3147afe284b790509affb1e33800577cb0dd63c5
|
don't crash on openbsd lacking dynamics
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/elf/elfplt.py",
"new_path": "vivisect/analysis/elf/elfplt.py",
"diff": "@@ -56,6 +56,7 @@ logger = logging.getLogger(__name__)\nMAGIC_PLT_SIZE = 16\n+\ndef analyze(vw):\n\"\"\"\nDo simple linear disassembly of the .plt section if present.\n@@ -64,6 +65,7 @@ def analyze(vw):\nfor sva, ssize in getPLTs(vw):\nanalyzePLT(vw, sva, ssize)\n+\ndef getGOT(vw, fileva):\n'''\nReturns GOT location for the file which contains the address fileva.\n@@ -116,15 +118,13 @@ def getGOT(vw, fileva):\nvw.setFileMeta(filename, 'GOT', (gotva, gotsize))\nreturn gotva, gotsize\n+\ndef getPLTs(vw):\nplts = []\n- pltva = None\n# Thought: This is DT_PLTGOT, although each ELF will/may have their own DT_PLTGOT.\nfor va, size, name, fname in vw.getSegments():\nif name.startswith(\".plt\") or name == '.rela.plt':\n- pltva = va\n- pltsize = size\n- plts.append((pltva, pltsize))\n+ plts.append((va, size))\n# pull GOT info from Dynamics\nfor fname in vw.getFiles():\n@@ -141,11 +141,12 @@ def getPLTs(vw):\nfor pltva, pltsize in plts:\nif FGOT == pltva:\nnewish = False\n- if newish:\n+ if newish and FGOT and FGOTSZ:\nplts.append((FGOT, FGOTSZ))\nreturn plts\n+\ndef analyzePLT(vw, ssva, ssize):\ntry:\n'''\n@@ -390,7 +391,10 @@ def analyzePLT(vw, ssva, ssize):\nvw.makeFunction(sva)\nexcept Exception as e:\n- logger.exception('analyzePLT(0x%x, %r)', ssva, ssize)\n+ import pdb\n+ pdb.set_trace()\n+ logger.error('analyzePLT(0x%x, %r): %s', ssva, ssize, str(e))\n+\nMAX_OPS = 10\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
don't crash on openbsd lacking dynamics
|
718,765 |
13.08.2020 01:54:40
| 14,400 |
3625f5fb7901740cc57d2407ac11176a1b2bcc37
|
fond why it's failing
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -124,7 +124,7 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nexcept Exception as e:\nself.logAnomaly(emu, self.fva, \"0x%x: (%r) ERROR: %s\" % (op.va, op, e))\n- logger.exception(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\n+ logger.error(\"0x%x: (%r) ERROR: %s\", op.va, op, e)\ndef posthook(self, emu, op, starteip):\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/pointers.py",
"new_path": "vivisect/analysis/generic/pointers.py",
"diff": "@@ -54,7 +54,7 @@ def analyze(vw):\n# Now, lets find likely free-hanging pointers\nfor addr, pval in vw.findPointers():\n- if vw.isDeadData(pval) or vw.isLocation(addr):\n+ if vw.isDeadData(pval):\ncontinue\ntry:\nlogger.info('pointer(4): 0x%x -> 0x%x', addr, pval)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "-import sys\nimport envi\nimport logging\n-import traceback\nimport envi.archs.arm as e_arm\n-import vivisect\n+import vivisect.exc as v_exc\nimport vivisect.impemu.emulator as v_i_emulator\nimport visgraph.pathcore as vg_path\n@@ -205,6 +203,8 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nif self.emumon:\ntry:\nself.emumon.prehook(self, op, starteip)\n+ except v_exc.BadOpBytes as e:\n+ logger.debug(repr(e))\nexcept Exception as e:\nif not self.getMeta('silent'):\nlogger.warn(\"funcva: 0x%x opva: 0x%x: %r (%r) (in emumon prehook: %r)\", funcva, starteip, op, e, self.emumon)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fond why it's failing
|
718,765 |
14.08.2020 15:49:44
| 14,400 |
f734e327123654af624027e81920fc4af19f9e00
|
version bump and incorporate atlas's walkTree tests
|
[
{
"change_type": "MODIFY",
"old_path": "setup.py",
"new_path": "setup.py",
"diff": "@@ -9,7 +9,7 @@ setup(\nname='vivisect',\nauthor='Vivisect',\nauthor_email='',\n- version='0.1.0rc2',\n+ version='0.1.0rc3',\nurl='https://github.com/vivisect/vivisect',\npackages=find_packages(),\nzip_safe=False,\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_analysis.py",
"new_path": "vivisect/symboliks/tests/test_analysis.py",
"diff": "import unittest\n-import vivisect.symboliks.common as vsc\nimport vivisect.symboliks.analysis as vsym_analysis\nfrom vivisect.tests.helpers import MockVw\n@@ -47,69 +46,3 @@ def cb_astNodeCount(path, obj, ctx):\nif len(path) > ctx['depth']:\nctx['depth'] = len(path)\n# print(\"\\n\\t%r\\n\\t\\t%s\" % (obj, '\\n\\t\\t'.join([repr(x) for x in path])))\n-\n-\n-class WalkTreeTest(unittest.TestCase):\n-\n- def test_coverage(self):\n- '''\n- ((mem[piva_global(0xbfbfee08):1] | (mem[(arg0 + 72):4] & 0xffffff00)) + piva_global())\n- '''\n- ids = []\n- piva1 = vsc.Var('piva_global', 4)\n- ids.append(piva1._sym_id)\n- arg = vsc.Const(0xbfbfee08, 4)\n- ids.append(arg._sym_id)\n- call = vsc.Call(piva1, 4, argsyms=[arg])\n- ids.append(call._sym_id)\n- con = vsc.Const(1, 4)\n- ids.append(con._sym_id)\n- mem1 = vsc.Mem(call, con)\n- ids.append(mem1._sym_id)\n-\n- arg = vsc.Arg(0, 4)\n- ids.append(arg._sym_id)\n- addop = vsc.Const(72, 4)\n- ids.append(addop._sym_id)\n- add = vsc.o_add(arg, addop, 4)\n- ids.append(add._sym_id)\n- con = vsc.Const(4, 4)\n- ids.append(con._sym_id)\n- memac = vsc.Mem(add, con)\n- ids.append(memac._sym_id)\n- andop = vsc.Const(0xffffff00, 4)\n- ids.append(andop._sym_id)\n- mem2 = vsc.o_and(memac, andop, 4)\n- ids.append(mem2._sym_id)\n- memor = vsc.o_or(mem1, mem2, 4)\n- ids.append(memor._sym_id)\n-\n- piva2 = vsc.Var('piva_global', 4)\n- ids.append(piva2._sym_id)\n- call2 = vsc.Call(piva2, 4, argsyms=[])\n- ids.append(call2._sym_id)\n- add = vsc.o_add(memor, call2, 4)\n- ids.append(add._sym_id)\n-\n- traveled_ids = []\n- def walkerTest(path, symobj, ctx):\n- traveled_ids.append(symobj._sym_id)\n-\n- add.walkTree(walkerTest)\n- self.assertEqual(traveled_ids, ids)\n- self.assertEqual('((mem[piva_global(0xbfbfee08):1] | (mem[(arg0 + 72):4] & 0xffffff00)) + piva_global())', str(add))\n-\n- def test_cleanwalk(self):\n- '''\n- test that we don't accidentally populate the solver cache while walking the tree\n- '''\n- symstr = \"o_add(o_xor(o_sub(Var('eax', 4), Const(98, 4), 4), Const(127, 4), 4), Const(4, 4), 4)\"\n- symobj = vsc.evalSymbolik(symstr)\n- objs = []\n- def walker(path, symobj, ctx):\n- objs.append(symobj)\n- symobj.walkTree(walker)\n-\n- self.assertEquals(len(objs), 7)\n- for obj in objs:\n- self.assertEquals(obj.cache, {})\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "vivisect/symboliks/tests/test_walkTree.py",
"diff": "+import unittest\n+\n+from vivisect.symboliks.common import Arg, Var, Const, Mem, Call, \\\n+ o_add, o_sub, o_xor, o_and, o_or, \\\n+ evalSymbolik\n+\n+\n+def walkTree_cb(path, cur, ctx):\n+ ctx['path'].append(cur)\n+\n+\n+class TestWalkTree(unittest.TestCase):\n+ def test_mem(self):\n+ ctx = {'path': []}\n+ ast = o_sub(\n+ o_add(\n+ o_xor(\n+ o_and(\n+ o_sub(\n+ Mem(\n+ o_add(\n+ #Arg(0,width=8)\n+ Const(0x20000000,8)\n+ ,Const(0x00000030,8)\n+ ,8)\n+ , Const(0x00000008,8)\n+ )\n+ ,o_add(\n+ Mem(\n+ o_add(\n+ Mem(\n+ #Arg(0,width=8)\n+ Const(0x20000000,8)\n+ , Const(0x00000008,8))\n+ ,Const(0x00000048,8)\n+ ,8)\n+ ,Const(0x00000008,8))\n+ ,Const(0x00000001,8)\n+ ,8)\n+ ,8)\n+ ,Const(0xffffffff,4)\n+ ,4)\n+ ,o_and(\n+ o_sub(\n+ Mem(\n+ o_add(\n+ #Arg(0,width=8)\n+ Const(0x20000000,8)\n+ ,Const(0x00000030,8)\n+ ,8)\n+ , Const(0x00000008,8))\n+ ,o_add(\n+ Mem(\n+ o_add(\n+ Mem(\n+ #Arg(0,width=8)\n+ Const(0x20000000,8)\n+ , Const(0x00000008,8))\n+ ,Const(0x00000048,8)\n+ ,8)\n+ , Const(0x00000008,8))\n+ ,Const(0x00000001,8)\n+ ,8)\n+ ,8)\n+ ,Const(0xffffffff,4)\n+ ,4)\n+ ,4)\n+ ,Const(0x00000001,8)\n+ ,8)\n+ ,Const(0x00000001,8)\n+ ,8)\n+ flattened = [Const(0x20000000,8),\n+ Const(0x00000030,8),\n+ o_add(Const(0x20000000,8),Const(0x00000030,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),\n+ Const(0x20000000,8),\n+ Const(0x00000008,8),\n+ Mem(Const(0x20000000,8), Const(0x00000008,8)),\n+ Const(0x00000048,8),\n+ o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),\n+ Const(0x00000001,8),\n+ o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),\n+ o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),\n+ Const(0xffffffff,4),\n+ o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),\n+ Const(0x20000000,8),\n+ Const(0x00000030,8),\n+ o_add(Const(0x20000000,8),Const(0x00000030,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),\n+ Const(0x20000000,8),\n+ Const(0x00000008,8),\n+ Mem(Const(0x20000000,8), Const(0x00000008,8)),\n+ Const(0x00000048,8),\n+ o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),\n+ Const(0x00000001,8),\n+ o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),\n+ o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),\n+ Const(0xffffffff,4),\n+ o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),\n+ o_xor(o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),4),\n+ Const(0x00000001,8),\n+ o_add(o_xor(o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),4),Const(0x00000001,8),8),\n+ Const(0x00000001,8),\n+ o_sub(o_add(o_xor(o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),4),Const(0x00000001,8),8),Const(0x00000001,8),8)]\n+\n+ ast.walkTree(walkTree_cb, ctx)\n+ self.assertEqual(ctx['path'], flattened)\n+ self.assertEqual(ctx['path'][-1], ast)\n+\n+ def test_moarmem(self):\n+ ctx = {'path': []}\n+ ast = o_sub(o_add(o_xor(o_and(o_sub(Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8),Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8),Const(0x00000008,8)),Const(0x00000048,8),8),Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem( o_add( Const(0x20000000,8) ,Const(0x00000030,8) ,8) , Const(0x00000008,8)) ,o_add( Mem( o_add( Mem( Const(0x20000000,8) , Const(0x00000008,8)) ,Const(0x00000048,8) ,8) , Const(0x00000008,8)) ,Const(0x00000001,8) ,8) ,8) ,Const(0xffffffff,4) ,4) ,4) ,Const(0x00000001,8) ,8) ,Const(0x00000001,8) ,8)\n+\n+ ast.walkTree(walkTree_cb, ctx)\n+ flattened = [Arg(0,width=8),\n+ Const(0x00000030,8),\n+ o_add(Arg(0,width=8),Const(0x00000030,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8), Const(0x00000008,8)),\n+ Const(0x20000000,8),\n+ Const(0x00000008,8),\n+ Mem(Const(0x20000000,8), Const(0x00000008,8)),\n+ Const(0x00000048,8),\n+ o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),\n+ Const(0x00000001,8),\n+ o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),\n+ o_sub(Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),\n+ Const(0xffffffff,4),\n+ o_and(o_sub(Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),\n+ Const(0x20000000,8),\n+ Const(0x00000030,8),\n+ o_add(Const(0x20000000,8),Const(0x00000030,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),\n+ Const(0x20000000,8),\n+ Const(0x00000008,8),\n+ Mem(Const(0x20000000,8), Const(0x00000008,8)),\n+ Const(0x00000048,8),\n+ o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8),\n+ Const(0x00000008,8),\n+ Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),\n+ Const(0x00000001,8),\n+ o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),\n+ o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),\n+ Const(0xffffffff,4),\n+ o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),\n+ o_xor(o_and(o_sub(Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),4),\n+ Const(0x00000001,8),\n+ o_add(o_xor(o_and(o_sub(Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),4),Const(0x00000001,8),8),\n+ Const(0x00000001,8),\n+ o_sub(o_add(o_xor(o_and(o_sub(Mem(o_add(Arg(0,width=8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),o_and(o_sub(Mem(o_add(Const(0x20000000,8),Const(0x00000030,8),8), Const(0x00000008,8)),o_add(Mem(o_add(Mem(Const(0x20000000,8), Const(0x00000008,8)),Const(0x00000048,8),8), Const(0x00000008,8)),Const(0x00000001,8),8),8),Const(0xffffffff,4),4),4),Const(0x00000001,8),8),Const(0x00000001,8),8)]\n+\n+ self.assertEqual(ast, evalSymbolik(repr(ast)))\n+ self.assertEqual(ctx['path'], flattened)\n+ self.assertEqual(ctx['path'][-1], ast)\n+\n+ def test_nested(self):\n+ ctx = {'path': []}\n+ ast = o_add(o_add(o_add(o_add(o_sub(o_sub(o_add(o_add(o_add(o_add( o_add(o_add(o_sub(o_sub(o_sub(o_sub(o_sub(o_sub(o_sub(Const(0xbfb00000,8), Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000068,8),8),Const(0x00000068,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),o_add(o_add(o_add(o_sub(o_sub(o_sub(o_sub(o_sub(o_sub(o_sub(Const(0xff010,8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000068,8),8),Const(0x00000068,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8)\n+ ast.walkTree(walkTree_cb, ctx)\n+ self.assertEqual(ast.reduce(), Const(0xbfbfeff0, 8))\n+ self.assertEqual(ctx['path'][-1], ast)\n+ self.assertEqual(len(ctx['path']), 59)\n+\n+ def test_flatten_constant(self):\n+ ctx = {'path': []}\n+ ast = o_add(o_add(o_add(Const(0x00000000, 8), Const(0x00000001, 8) ,8),\n+ o_add(Const(0x00000002,8), Const(0x00000003, 8), 8),\n+ 8),\n+ Const(0x00000004,8),\n+ 8)\n+ flattened = [Const(0x00000000,8),\n+ Const(0x00000001,8),\n+ o_add(Const(0x00000000,8),Const(0x00000001,8),8),\n+ Const(0x00000002,8),\n+ Const(0x00000003,8),\n+ o_add(Const(0x00000002,8),Const(0x00000003,8),8),\n+ o_add(o_add(Const(0x00000000,8),Const(0x00000001,8),8),o_add(Const(0x00000002,8),Const(0x00000003,8),8),8),\n+ Const(0x00000004,8),\n+ o_add(o_add(o_add(Const(0x00000000,8),Const(0x00000001,8),8),o_add(Const(0x00000002,8),Const(0x00000003,8),8),8),Const(0x00000004,8),8),]\n+\n+ ast.walkTree(walkTree_cb, ctx)\n+ self.assertEqual(ctx['path'][-1], ast)\n+ self.assertEqual(ctx['path'], flattened)\n+ self.assertEqual(Const(0xa, 8), ast.reduce())\n+\n+ ctx = {'path': []}\n+ ast = o_add(o_add(o_sub(o_add(o_sub(Const(0xbfb00000,8),\n+ Const(0x00000008,8),\n+ 8),\n+ o_add(Const(0x000ff000,8),\n+ Const(0x00000008,8),\n+ 8),\n+ 8),\n+ Const(0x00000008,8),\n+ 8),\n+ Const(0x00000008, 8),\n+ 8),\n+ Const(0x00000008,8),\n+ 8)\n+ flattened = [Const(0xbfb00000, 8),\n+ Const(0x00000008, 8),\n+ o_sub(Const(0xbfb00000, 8), Const(0x00000008, 8), 8),\n+ Const(0x000ff000,8),\n+ Const(0x00000008,8),\n+ o_add(Const(0x000ff000,8), Const(0x00000008,8), 8),\n+ o_add(o_sub(Const(0xbfb00000, 8), Const(0x00000008, 8), 8),o_add(Const(0x000ff000,8), Const(0x00000008,8), 8), 8),\n+ Const(0x00000008,8),\n+ o_sub(o_add(o_sub(Const(0xbfb00000,8),Const(0x00000008,8), 8), o_add(Const(0x000ff000,8), Const(0x00000008,8), 8), 8), Const(0x00000008,8), 8),\n+ Const(0x00000008, 8),\n+ o_add(o_sub(o_add(o_sub(Const(0xbfb00000,8), Const(0x00000008,8), 8), o_add(Const(0x000ff000,8), Const(0x00000008,8), 8), 8), Const(0x00000008,8), 8), Const(0x00000008, 8), 8),\n+ Const(0x00000008,8),\n+ o_add(o_add(o_sub(o_add(o_sub(Const(0xbfb00000,8), Const(0x00000008,8), 8), o_add(Const(0x000ff000,8), Const(0x00000008,8), 8), 8), Const(0x00000008,8), 8), Const(0x00000008, 8), 8), Const(0x00000008,8), 8) ]\n+ ast.walkTree(walkTree_cb, ctx)\n+ self.assertEqual(ctx['path'], flattened)\n+ self.assertEqual(Const(0xbfbff008, 8), ast.reduce())\n+\n+ def test_memarg(self):\n+ ctx = {'path': []}\n+ ast = o_add(o_add(o_sub(o_add(o_sub(Const(0xbfb00000, 8),\n+ Mem(Arg(0, width=8), Const(0x00000008, 8)),\n+ 8),\n+ o_add(Const(0x000ff000, 8),\n+ Const(0x00000008, 8),\n+ 8),\n+ 8),\n+ Const(0x00000008,8),\n+ 8),\n+ Const(0x00000008,8),\n+ 8),\n+ Const(0x00000008,8),\n+ 8)\n+ flattened = [Const(0xbfb00000,8),\n+ Arg(0,width=8),\n+ Const(0x00000008,8),\n+ Mem(Arg(0,width=8), Const(0x00000008,8)),\n+ o_sub(Const(0xbfb00000,8),Mem(Arg(0,width=8), Const(0x00000008,8)),8),\n+ Const(0x000ff000,8),\n+ Const(0x00000008,8),\n+ o_add(Const(0x000ff000,8),Const(0x00000008,8),8),\n+ o_add(o_sub(Const(0xbfb00000,8),Mem(Arg(0,width=8), Const(0x00000008,8)),8),o_add(Const(0x000ff000,8),Const(0x00000008,8),8),8),\n+ Const(0x00000008,8),\n+ o_sub(o_add(o_sub(Const(0xbfb00000,8),Mem(Arg(0,width=8), Const(0x00000008,8)),8),o_add(Const(0x000ff000,8),Const(0x00000008,8),8),8),Const(0x00000008,8),8),\n+ Const(0x00000008,8),\n+ o_add(o_sub(o_add(o_sub(Const(0xbfb00000,8),Mem(Arg(0,width=8), Const(0x00000008,8)),8),o_add(Const(0x000ff000,8),Const(0x00000008,8),8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),\n+ Const(0x00000008,8),\n+ o_add(o_add(o_sub(o_add(o_sub(Const(0xbfb00000,8),Mem(Arg(0,width=8), Const(0x00000008,8)),8),o_add(Const(0x000ff000,8),Const(0x00000008,8),8),8),Const(0x00000008,8),8),Const(0x00000008,8),8),Const(0x00000008,8),8)]\n+ ast.walkTree(walkTree_cb, ctx)\n+ self.assertEqual(ctx['path'][-1], ast)\n+ self.assertEqual(ctx['path'], flattened)\n+ answer = o_add(o_sub(Const(0x00000000,8),Mem(Arg(0,width=8), Const(0x00000008,8)),8),Const(0xbfbff010,8),8)\n+ self.assertEqual(answer, ast.reduce())\n+\n+ def test_coverage(self):\n+ '''\n+ ((mem[piva_global(0xbfbfee08):1] | (mem[(arg0 + 72):4] & 0xffffff00)) + piva_global())\n+ '''\n+ ids = []\n+ piva1 = Var('piva_global', 4)\n+ ids.append(piva1._sym_id)\n+ arg = Const(0xbfbfee08, 4)\n+ ids.append(arg._sym_id)\n+ call = Call(piva1, 4, argsyms=[arg])\n+ ids.append(call._sym_id)\n+ con = Const(1, 4)\n+ ids.append(con._sym_id)\n+ mem1 = Mem(call, con)\n+ ids.append(mem1._sym_id)\n+\n+ arg = Arg(0, 4)\n+ ids.append(arg._sym_id)\n+ addop = Const(72, 4)\n+ ids.append(addop._sym_id)\n+ add = o_add(arg, addop, 4)\n+ ids.append(add._sym_id)\n+ con = Const(4, 4)\n+ ids.append(con._sym_id)\n+ memac = Mem(add, con)\n+ ids.append(memac._sym_id)\n+ andop = Const(0xffffff00, 4)\n+ ids.append(andop._sym_id)\n+ mem2 = o_and(memac, andop, 4)\n+ ids.append(mem2._sym_id)\n+ memor = o_or(mem1, mem2, 4)\n+ ids.append(memor._sym_id)\n+\n+ piva2 = Var('piva_global', 4)\n+ ids.append(piva2._sym_id)\n+ call2 = Call(piva2, 4, argsyms=[])\n+ ids.append(call2._sym_id)\n+ add = o_add(memor, call2, 4)\n+ ids.append(add._sym_id)\n+\n+ traveled_ids = []\n+ def walkerTest(path, symobj, ctx):\n+ traveled_ids.append(symobj._sym_id)\n+\n+ add.walkTree(walkerTest)\n+ self.assertEqual(traveled_ids, ids)\n+ self.assertEqual('((mem[piva_global(0xbfbfee08):1] | (mem[(arg0 + 72):4] & 0xffffff00)) + piva_global())', str(add))\n+\n+ def test_cleanwalk(self):\n+ '''\n+ test that we don't accidentally populate the solver cache while walking the tree\n+ '''\n+ symstr = \"o_add(o_xor(o_sub(Var('eax', 4), Const(98, 4), 4), Const(127, 4), 4), Const(4, 4), 4)\"\n+ symobj = evalSymbolik(symstr)\n+ objs = []\n+ def walker(path, symobj, ctx):\n+ objs.append(symobj)\n+ symobj.walkTree(walker)\n+\n+ self.assertEquals(len(objs), 7)\n+ for obj in objs:\n+ self.assertEquals(obj.cache, {})\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
version bump and incorporate atlas's walkTree tests
|
718,770 |
18.08.2020 07:37:28
| 14,400 |
1e5436cbee3c13d72a93e737477b2d71f5fe522c
|
minor bug fixes in ARM disassembly and emulation. helps get rid of some of the unittest error messages (yes, that's why they're there ;)
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/arm/emu.py",
"new_path": "envi/archs/arm/emu.py",
"diff": "@@ -1066,7 +1066,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nreturn result;\n- def i_vcvt(self, op):\n+ def i_vcvt_TODO(self, op):\n'''\nconvert each element in a vector as float to int or int to float, 32-bit, round-to-zero/round-to-nearest\n@@ -1225,7 +1225,7 @@ class ArmEmulator(ArmRegisterContext, envi.Emulator):\nraise Exception(\"i_vcvt with strange number of opers: %r\" % op.opers)\n- i_vcvtr = i_vcvt\n+ #i_vcvtr = i_vcvt\ndef i_ldm(self, op):\nif len(op.opers) == 2:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/platarch/arm.py",
"new_path": "vivisect/impemu/platarch/arm.py",
"diff": "@@ -267,7 +267,7 @@ class ArmWorkspaceEmulator(v_i_emulator.WorkspaceEmulator, e_arm.ArmEmulator):\nself.emumon.logAnomaly(self, starteip, str(e))\nlogger.debug('runFunction breaking after exception (fva: 0x%x): %s', funcva, e)\n- logger.exception('')\n+ #logger.exception('')\nbreak # If we exc during execution, this branch is dead.\nclass ThumbWorkspaceEmulator(ArmWorkspaceEmulator):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
minor bug fixes in ARM disassembly and emulation. helps get rid of some of the unittest error messages (yes, that's why they're there ;) (#305)
|
718,770 |
20.08.2020 12:50:08
| 14,400 |
6024e0a457d7a922ab2b3f77d96788a50d267827
|
bugfix since msgpack added strict_map_key and we break that
thanks for verification and pushing back for best quality.
|
[
{
"change_type": "MODIFY",
"old_path": "cobra/__init__.py",
"new_path": "cobra/__init__.py",
"diff": "@@ -27,6 +27,8 @@ try:\ndumpargs['use_bin_type'] = 1\nif msgpack.version < (1, 0, 0):\nloadargs['encoding'] = 'utf-8'\n+ else:\n+ loadargs['strict_map_key'] = False\nexcept ImportError:\nmsgpack = None\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugfix since msgpack added strict_map_key and we break that (#307)
thanks @rakuy0 for verification and pushing back for best quality.
|
718,765 |
08.09.2020 15:44:58
| 14,400 |
f11f4e1e739a40cbbbdd9fb770b1a64ba1a6ffb2
|
A wild changelog appeared!
Add initial changelog.
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": "CHANGELOG.rst",
"diff": "+******************\n+Vivisect Changelog\n+******************\n+\n+v0.1.0 - 2020-09-08\n+===================\n+Features\n+--------\n+- Symbolik Reduction Speedup.\n+ (`#309 <https://github.com/vivisect/vivisect/pull/309>`)\n+- Codebase cleanup in preparation to move to python 3.\n+ (`#293 <https://github.com/vivisect/vivisect/pull/293>`)\n+- Support for integrating with revsync.\n+ (`#304 <https://github.com/vivisect/vivisect/pull/304>`)\n+- Expand unittest coverage.\n+ (`#303 <https://github.com/vivisect/vivisect/pull/303>`)\n+- ELF tweaks for ARM binaries.\n+ (`#290 <https://github.com/vivisect/vivisect/pull/290>`)\n+- More opcode mappings for intel.\n+ (`#299 <https://github.com/vivisect/vivisect/pull/299>`)\n+- Upgrade cxxfilt.\n+ (`#302 <https://github.com/vivisect/vivisect/pull/302>`)\n+\n+Fixes\n+-----\n+- Make creation of $HOME/.viv directory user configurable.\n+ (`#310 <https://github.com/vivisect/vivisect/pull/310>`)\n+- Msgpack strict_map_key bugfix.\n+ (`#307 <https://github.com/vivisect/vivisect/pull/307>`)\n+- ARM disassembly and emulation bugfixes.\n+ (`#305 <https://github.com/vivisect/vivisect/pull/305>`)\n+- PyPI fix for vtrace.\n+ (`#300 <https://github.com/vivisect/vivisect/pull/300>`)\n+- Calling convention fixes\n+ (`#301 <https://github.com/vivisect/vivisect/pull/301>`)\n+\n+\n+v0.1.0rc1 - 2020-07-30\n+======================\n+- Initial Pypi Release\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
A wild changelog appeared! (#312)
Add initial changelog.
|
718,770 |
25.09.2020 07:38:11
| 14,400 |
44e12e66b1c6f300230b7be758e9de078983c25e
|
minor bugfix for handling deleted codeblocks
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/generic/codeblocks.py",
"new_path": "vivisect/analysis/generic/codeblocks.py",
"diff": "@@ -130,7 +130,8 @@ def analyzeFunction(vw, funcva):\n# So we don't add a codeblock if we're re-analyzing a function\n# (like during dynamic branch analysis)\nbsize = blocks[bva]\n- if bva not in oldblocks:\n+ tmpcb = vw.getCodeBlock(bva)\n+ if bva not in oldblocks or tmpcb is None: # sometimes codeblocks can be deleted if owned by multiple functions\nvw.addCodeBlock(bva, bsize, funcva)\nelif bsize != oldblocks[bva]:\nvw.delCodeBlock(bva)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
minor bugfix for handling deleted codeblocks (#317)
|
718,770 |
28.09.2020 07:53:43
| 14,400 |
3ac90dcbb5724b00bdb7b816062c6ccfb445c386
|
import emulator to handle dynamic branches (switchcases) using only xrefs
* modify import emulator to handle dynamic branches (switchcases) using only xrefs.
* bugfix: forgot that getBranches returns REF_CODE/BR_DEREF options which are *not* direct code branches (eg. PLT).
added __ctype_b_loc to impapi
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/impapi/posix/i386.py",
"new_path": "vivisect/impapi/posix/i386.py",
"diff": "@@ -938,5 +938,6 @@ api = {\n'plt_wctomb':( 'int', None, 'cdecl', '*.wctomb', (('void *', 'ptr'), ('int', None)) ),\n'plt_wprintf':( 'int', None, 'cdecl', '*.wprintf', (('int', None),) ),\n'plt_wscanf':( 'int', None, 'cdecl', '*.wscanf', (('int', None),) ),\n+ 'plt___ctype_b_loc':( 'int', None, 'cdecl', '*.__ctype_b_loc', () ),\n} # END\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/impemu/emulator.py",
"new_path": "vivisect/impemu/emulator.py",
"diff": "@@ -272,6 +272,19 @@ class WorkspaceEmulator:\nret.append((bva, bpath))\npaths.add(bva)\n+ if op.iflags & envi.IF_BRANCH \\\n+ and not op.iflags & envi.IF_COND \\\n+ and len(xrefs):\n+ # we've hit a branch that doesn't go anywhere. probably a switchcase we don't handle here.\n+ for xrfr, xrto, xrt, xrflag in xrefs:\n+ # skip existing, skip DEREFS\n+ if xrto in paths or xrflag & envi.BR_DEREF:\n+ continue\n+\n+ bpath = self.getBranchNode(self.curpath, xrto)\n+ ret.append((xrto, bpath))\n+ paths.add(xrto)\n+\n# let's also take into account some of the dynamic branches we may have found\n# like our table pointers\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
import emulator to handle dynamic branches (switchcases) using only xrefs (#314)
* modify import emulator to handle dynamic branches (switchcases) using only xrefs.
* bugfix: forgot that getBranches returns REF_CODE/BR_DEREF options which are *not* direct code branches (eg. PLT).
added __ctype_b_loc to impapi
|
718,774 |
29.09.2020 07:19:01
| -7,200 |
8a28f46f76f60feb236bb8a5786feaad33346aaa
|
Fix: syntax error discovered by pytocs
* Fix: Non-terminated string constant
`visgraph/renderers/svgrend.py` is missing a terminating apostrophe on line 41.
* Incorrect extra closing parenthesis removed
* Possible missing comment character '#'
|
[
{
"change_type": "MODIFY",
"old_path": "vdb/testmods/hookbptest.py",
"new_path": "vdb/testmods/hookbptest.py",
"diff": "@@ -222,4 +222,4 @@ class HookBpTest6(v_testmods.VtracePythonTest):\n# TODO: I don't think these are run....\nif __name__ == '__main__':\nimport sys\n- sys.exit(31) TODO: tests for something NOT in impapi\n+ sys.exit(31) # TODO: tests for something NOT in impapi\n"
},
{
"change_type": "MODIFY",
"old_path": "visgraph/renderers/svgrend.py",
"new_path": "visgraph/renderers/svgrend.py",
"diff": "@@ -38,7 +38,7 @@ class SvgGraphRenderer(vg_render.GraphRenderer):\ndef endRender(self):\n# Actually write out the file.\n- with open(self.svgfile, 'wb) as f:\n+ with open(self.svgfile, 'wb') as f:\nf.write('<?xml version=\"1.0\" standalone=\"no\"?>\\n')\n#f.write('<!DOCTYPE svg PUBLIC \"-//W3C//DTD SVG 1.1//EN http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd\" >\\n')\nxsize = self._vg_canvas_width\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/macho.py",
"new_path": "vivisect/parsers/macho.py",
"diff": "@@ -33,7 +33,7 @@ def _loadMacho(vw, filebytes, filename=None, baseaddr=None):\n# grab md5 and sha256 hashes before we modify the bytes\nfhash = viv_parsers.md5Bytes(filebytes)\n- sha256 = v_parsers.sha256Bytes(filebytes))\n+ sha256 = v_parsers.sha256Bytes(filebytes)\n# Check for the FAT binary magic...\nif binascii.hexlify(filebytes[:4]) in ('cafebabe', 'bebafeca'):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Fix: syntax error discovered by pytocs (#318)
* Fix: Non-terminated string constant
`visgraph/renderers/svgrend.py` is missing a terminating apostrophe on line 41.
* Incorrect extra closing parenthesis removed
* Possible missing comment character '#'
Co-authored-by: atlas0fd00m <atlas@r4780y.com>
|
718,765 |
13.10.2020 23:20:50
| 14,400 |
db708eb31da8dba90e27973be1a7dc59b06dfcee
|
bad intel. no soup for you.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "@@ -402,9 +402,9 @@ tbl32_0F = [\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n-( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n-( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n-( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),\n+(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n+(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n+(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n# 0f20\n( 0, INS_MOV, ADDRMETH_R | OPTYPE_q | OP_W, ADDRMETH_C | OPTYPE_q | OP_R, ARG_NONE, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opcode86.py",
"new_path": "envi/archs/i386/opcode86.py",
"diff": "@@ -317,9 +317,9 @@ tbl32_0F = [\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n-(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n-(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n-(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0),\n+(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n+(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n+(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n(0, INS_OTHER, ADDRMETH_E | OPTYPE_v, ARG_NONE, ARG_NONE, cpu_80386, \"nop\", 0, 0, 0),\n# 0f20\n( 0, INS_MOV, ADDRMETH_R | OPTYPE_d | OP_W, ADDRMETH_C | OPTYPE_d | OP_R, ARG_NONE, cpu_80386, \"mov\", 0, 0, 0),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_amd64.py",
"new_path": "envi/tests/test_arch_amd64.py",
"diff": "@@ -60,6 +60,22 @@ amd64SingleByteOpcodes = [\n('push', '48fff0', 'push rax', 'push rax'),\n('pop', '488ff0', 'pop rax', 'pop rax'),\n('pop', '488ffb', 'pop rbx', 'pop rbx'),\n+ ('nop', '660f1cf8', 'nop ax', 'nop ax'),\n+ ('nop', '660f1df8', 'nop ax', 'nop ax'),\n+ ('nop', '660f1ef8', 'nop ax', 'nop ax'),\n+ ('nop', '660f1ff8', 'nop ax', 'nop ax'),\n+ ('nop', 'f20f1cfb', 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f20f1dfb', 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f20f1efb', 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f20f1ffb', 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f30f1cfa', 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', 'f30f1dfa', 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', 'f30f1efa', 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', 'f30f1ffa', 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', '0f1cfa', 'nop edx', 'nop edx'),\n+ ('nop', '0f1dfa', 'nop edx', 'nop edx'),\n+ ('nop', '0f1efa', 'nop edx', 'nop edx'),\n+ ('nop', '0f1ffa', 'nop edx', 'nop edx'),\n('ud2', '0f0b', 'ud2 ', 'ud2 '),\n('FISTTP', 'db08', 'fisttp dword [rax]', 'fisttp dword [rax]'),\n('FISTTP 2', 'df08', 'fisttp word [rax]', 'fisttp word [rax]'),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_i386.py",
"new_path": "envi/tests/test_arch_i386.py",
"diff": "@@ -41,6 +41,22 @@ i386SingleByteOpcodes = [\n('TEST', '84db', 0x40, 'test bl,bl', 'test bl,bl'),\n('POP', '5D', 0x40, 'pop ebp', 'pop ebp'),\n('POP', '5B', 0x40, 'pop ebx', 'pop ebx'),\n+ ('nop', '660f1cf8', 0x40, 'nop ax', 'nop ax'),\n+ ('nop', '660f1df8', 0x40, 'nop ax', 'nop ax'),\n+ ('nop', '660f1ef8', 0x40, 'nop ax', 'nop ax'),\n+ ('nop', '660f1ff8', 0x40, 'nop ax', 'nop ax'),\n+ ('nop', 'f20f1cfb', 0x40, 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f20f1dfb', 0x40, 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f20f1efb', 0x40, 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f20f1ffb', 0x40, 'repnz: nop ebx', 'repnz: nop ebx'),\n+ ('nop', 'f30f1cfa', 0x40, 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', 'f30f1dfa', 0x40, 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', 'f30f1efa', 0x40, 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', 'f30f1ffa', 0x40, 'rep: nop edx', 'rep: nop edx'),\n+ ('nop', '0f1cfa', 0x40, 'nop edx', 'nop edx'),\n+ ('nop', '0f1dfa', 0x40, 'nop edx', 'nop edx'),\n+ ('nop', '0f1efa', 0x40, 'nop edx', 'nop edx'),\n+ ('nop', '0f1ffa', 0x40, 'nop edx', 'nop edx'),\n]\ni386MultiByteOpcodes = [\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bad intel. no soup for you. (#326)
|
718,765 |
23.11.2020 15:22:33
| 18,000 |
ff7975d98268a39d038cfa7d589c94655abc23aa
|
Speed up for setSymKid, and a few decoding fixes
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "@@ -1337,7 +1337,7 @@ tbl32_F30FC7_rest = list( tbl32_0FC7_rest )\ndesc_0FC7_00BF = (tbl32_0FC7_00BF, 3, 3, 0x07, 0, 0xbf, TBL_0FC7_rest)\n-desc_0FC7_rest = (tbl32_0FC7_rest, 3, 0, 0x07, 0xc0, 0xff)\n+desc_0FC7_rest = (tbl32_0FC7_rest, 3, 3, 0x07, 0xc0, 0xff)\ndesc_660FC7_00BF = (tbl32_660FC7_00BF, 3, 3, 0x07, 3, 0xff, TBL_660FC7_rest)\ndesc_660FC7_rest = (tbl32_660FC7_rest, 3, 3, 0x07, 0xc0, 0xff)\ndesc_F30FC7_00BF = (tbl32_F30FC7_00BF, 3, 3, 0x07, 3, 0xff, TBL_F30FC7_rest)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opcode86.py",
"new_path": "envi/archs/i386/opcode86.py",
"diff": "@@ -2233,7 +2233,7 @@ tables86=[\n(tbl32_0FAE_00BF, 3, 0x07, 0, 0xbf, 53), # 22\n(tbl32_0FBA, 3, 0x07, 0, 0xff), # 23\n(tbl32_0FC7_00BF, 3, 0x07, 0, 0xbf, 25), # 24\n- (tbl32_0FC7_rest, 0, 0x07, 0xc0, 0xff), # 25\n+ (tbl32_0FC7_rest, 3, 0x07, 0xc0, 0xff), # 25\n(tbl32_fpuD8_00BF, 3, 0x07, 0, 0xbf, 27), # 26\n(tbl32_fpuD8_rest, 0, 0xff, 0xc0, 0xff), # 27\n(tbl32_fpuD9_00BF, 3, 0x07, 0, 0xbf, 29), # 28\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_amd64.py",
"new_path": "envi/tests/test_arch_amd64.py",
"diff": "@@ -376,6 +376,11 @@ amd64MultiByteOpcodes = [\n('LDDQU', 'f2440ff0142541414141', 'lddqu xmm10,oword [0x41414141]', 'lddqu xmm10,oword [0x41414141]'),\n('LDDQU 1', 'f20ff0348531000000', 'lddqu xmm6,oword [0x00000031 + rax * 4]', 'lddqu xmm6,oword [0x00000031 + rax * 4]'),\n('MOVDQ2Q', 'f20fd6d9', 'movdq2q mm3,xmm1', 'movdq2q mm3,xmm1'),\n+ ('RDRAND', '0fc7f0', 'rdrand eax', 'rdrand eax'),\n+ ('RDSEED', '0fc7f8', 'rdseed eax', 'rdseed eax'),\n+ ('VMPTRST', '0fc73d41414141', 'vmptrst qword [rip + 1094795585]', 'vmptrst qword [rip + 1094795585]'),\n+ ('VMCLEAR', '0fc73541414141', 'vmptrld qword [rip + 1094795585]', 'vmptrld qword [rip + 1094795585]'),\n+ ('CMPXCHG', '0fb0d0', 'cmpxchg al,dl', 'cmpxchg al,dl'),\n# XXX: Here's a fun tidbit. In the intel docs for this instruction, it says to use REX.B\n# to index into the higher\n# xmm{8,15} registers. But the only xmm register in this are specifcally indexed by the\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_i386.py",
"new_path": "envi/tests/test_arch_i386.py",
"diff": "@@ -293,6 +293,11 @@ i386MultiByteOpcodes = [\n('PCLMULQDQ (MEM)', '660F3A441007', 0x40, 'pclmulqdq xmm2,oword [eax],7', 'pclmulqdq xmm2,oword [eax],7'),\n('PCLMULQDQ (MEM 2)', '660F3A4478119C', 0x40, 'pclmulqdq xmm7,oword [eax + 17],156', 'pclmulqdq xmm7,oword [eax + 17],156'),\n('PCLMULQDQ (MEM 3)', '660F3A443D41414141C6', 0x40, 'pclmulqdq xmm7,oword [0x41414141],198', 'pclmulqdq xmm7,oword [0x41414141],198'),\n+ ('RDRAND', '0fc7f0', 0x40, 'rdrand eax', 'rdrand eax'),\n+ ('RDSEED', '0fc7f8', 0x40, 'rdseed eax', 'rdseed eax'),\n+ ('VMPTRST', '0fc73d41414141', 0x40, 'vmptrst qword [0x41414141]', 'vmptrst qword [0x41414141]'),\n+ ('VMCLEAR', '0fc73541414141', 0x40, 'vmptrld qword [0x41414141]', 'vmptrld qword [0x41414141]'),\n+ ('CMPXCHG', '0fb0d0', 0x40, 'cmpxchg al,dl', 'cmpxchg al,dl'),\n]\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/common.py",
"new_path": "vivisect/symboliks/common.py",
"diff": "@@ -277,7 +277,7 @@ class SymbolikBase:\nreturn\n# invalidate the cache, but be careful not to repopulate it\n- todo = collections.OrderedDict({p._sym_id: p for p in oldkid.parents})\n+ todo = {p._sym_id: p for p in oldkid.parents}\ndone = set()\nwhile todo:\npid, parent = todo.popitem()\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Speed up for setSymKid, and a few decoding fixes (#332)
|
718,768 |
10.12.2020 09:51:37
| 25,200 |
14947a53c6781175f0aa83d49cc16c524a2e23a3
|
vivisect: don't configure logging within library code
this stomps on the configuration provided by applications
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -51,12 +51,6 @@ import vivisect.analysis.generic.emucode as v_emucode\nlogger = logging.getLogger(__name__)\n-e_common.setLogging(logger, 'WARNING')\n-\n-# FIXME: UGH. Due to our package structure, we have no centralized logging leve\n-# so we have to force it here and a few other places\n-elog = logging.getLogger(envi.__name__)\n-elog.setLevel(logger.getEffectiveLevel())\nSTOP_LOCS = (LOC_STRING, LOC_UNI, LOC_STRUCT, LOC_CLSID, LOC_VFTABLE, LOC_IMPORT, LOC_PAD, LOC_NUMBER)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
vivisect: don't configure logging within library code (#334)
this stomps on the configuration provided by applications
|
718,770 |
14.01.2021 11:44:52
| 18,000 |
15ceb5feb4499be00f91d30bf11bffcc3a8ba5ae
|
Bugfixes atlas 210113
* bugfix: thumb BX flags and parsing
* ihex sha256 bugfix
TODO: unit tests for both
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/disasm.py",
"new_path": "envi/archs/thumb16/disasm.py",
"diff": "@@ -133,15 +133,24 @@ def rt_pc_imm8d(va, value): # ldr\noper1 = ArmImmOffsetOper(REG_PC, imm, (va & 0xfffffffc))\nreturn COND_AL, (oper0, oper1), None\n+bx_flag_opts = (\n+ envi.IF_BRANCH | envi.IF_NOFALL,\n+ envi.IF_RET | envi.IF_NOFALL,\n+ envi.IF_CALL,\n+ envi.IF_CALL,\n+ )\ndef rm4_shift3(va, value): # bx/blx\niflags = None\notype, shval, mask = O_REG, 3, 0xf\noval = shmaskval(value, shval, mask)\noper = ArmRegOper((value >> shval) & mask, va=va)\n- if oval == REG_LR:\n- l = bool(value & 0b0000000010000000)\n- iflags = (envi.IF_RET | envi.IF_NOFALL, envi.IF_CALL)[l]\n+\n+ isLR = (oval == REG_LR) & 1 # convert to bit 0\n+ l = (value >> 6) & 2 # store in bit 1\n+\n+ iflags = bx_flag_opts[(isLR | l)]\n+\nreturn COND_AL, (oper,), iflags\n@@ -2008,8 +2017,7 @@ thumb_base = [\n('010001011', (INS_CMP, 'cmp', d1_rm4_rd3, 0)), # CMP<c> <Rn>,<Rm>\n('01000110', (INS_MOV, 'mov', d1_rm4_rd3, 0)), # MOV<c> <Rd>,<Rm>\n# BX<c> <Rm> # FIXME: check for IF_RET\n- ('010001101110000', (INS_BX, 'bx', rm4_shift3, envi.IF_NOFALL | envi.IF_RET)),\n- ('010001110', (INS_BL, 'bl', rm4_shift3, envi.IF_NOFALL | envi.IF_BRANCH)),\n+ ('010001110', (INS_BX, 'bx', rm4_shift3, 0)),\n('010001111', (INS_BLX, 'blx', rm4_shift3, envi.IF_CALL)), # BLX<c> <Rm>\n# Load from Litera7 Pool\n('01001', (INS_LDR, 'ldr', rt_pc_imm8d, 0)), # LDR<c> <Rt>,<label>\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/ihex.py",
"new_path": "vivisect/parsers/ihex.py",
"diff": "@@ -28,7 +28,7 @@ def parseFile(vw, filename, baseaddr=None):\n# might we make use of baseaddr, even though it's an IHEX? for now, no.\nfname = vw.addFile(filename, 0, v_parsers.md5File(filename))\n- vw.setFileMeta(filename, 'sha256', v_parsers.sha256File(filename))\n+ vw.setFileMeta(fname, 'sha256', v_parsers.sha256File(filename))\nihex = v_ihex.IHexFile()\nwith open(filename, 'rb') as f:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Bugfixes atlas 210113 (#337)
* bugfix: thumb BX flags and parsing
* ihex sha256 bugfix
TODO: unit tests for both
|
718,765 |
20.01.2021 16:41:06
| 18,000 |
5a6787659fea169bd57ef186239414788bc25d95
|
choose a different function that is less memory intensive
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/symboliks/tests/test_intel.py",
"new_path": "vivisect/symboliks/tests/test_intel.py",
"diff": "@@ -147,11 +147,12 @@ class IntelSymTests(unittest.TestCase):\ndef test_symbolik_paths_to(self):\nvw = self.i386_vw\n- fva = 0x8055bb0\n- tova = 0x8055dde\n+ fva = 0x80569d0\n+ tova = 0x08056b14\n+\nsctx = v_s_analysis.getSymbolikAnalysisContext(vw, consolve=False)\npaths = [x for x in sctx.getSymbolikPathsTo(fva, tova)]\n- self.assertEqual(26, len(paths))\n+ self.assertEqual(6, len(paths))\ndef test_symbolik_outputs(self):\nvw = self.i386_vw\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
choose a different function that is less memory intensive (#342)
|
718,768 |
29.01.2021 09:28:18
| 25,200 |
da1632a04e15c3ddd1a2c459059f6bb6eefcf852
|
pe: more robust relocation handling in the face of corrupt PE files
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/pe.py",
"new_path": "vivisect/parsers/pe.py",
"diff": "@@ -343,7 +343,20 @@ def loadPeIntoWorkspace(vw, pe, filename=None, baseaddr=None):\nlogger.info('Skipping PE Relocation type: %d at %d (no handler)', rtype, rva)\ncontinue\n+ try:\nmapoffset = vw.readMemoryPtr(rva + baseaddr) - baseaddr\n+ except:\n+ # the target adderss of the relocation is not accessible.\n+ # for example, it's not mapped, or split across sections, etc.\n+ # technically, the PE is corrupt.\n+ # by continuing on here, we are a bit more robust (but maybe incorrect)\n+ # than the Windows loader.\n+ #\n+ # discussed in:\n+ # https://github.com/vivisect/vivisect/issues/346\n+ logger.warning('Skipping invalid PE relocation: %d', rva)\n+ continue\n+ else:\nvw.addRelocation(rva + baseaddr, vtype, mapoffset)\nfor rva, lname, iname in pe.getImports():\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
pe: more robust relocation handling in the face of corrupt PE files (#347)
|
718,765 |
01.02.2021 23:11:05
| 18,000 |
6b2145268976e4748eabfb9470a4edcc19bf36ff
|
v0.2.0 release notes
Changelog Updates
|
[
{
"change_type": "MODIFY",
"old_path": "CHANGELOG.rst",
"new_path": "CHANGELOG.rst",
"diff": "Vivisect Changelog\n******************\n+\n+v0.2.0 - 2021-02-01\n+===================\n+\n+Features\n+--------\n+- More IMAGE_FILE defs and honoring NXCOMPAT in older PE files\n+ (`#319 <https://github.com/vivisect/vivisect/pull/319>`_)\n+- Msgpack backed storage module\n+ (`#321 <https://github.com/vivisect/vivisect/pull/321>`_)\n+- Substring location accesses\n+ (`#327 <https://github.com/vivisect/vivisect/pull/327>`_)\n+- Parse and return the delay import table\n+ (`#331 <https://github.com/vivisect/vivisect/pull/331>`_)\n+- New noret pass/several API refreshes/intel emulator fixes/emucode hyra function fixes\n+ (`#333 <https://github.com/vivisect/vivisect/pull/333>`_)\n+- Migrate to CircleCI for Continuous Integratoin\n+ (`#336 <https://github.com/vivisect/vivisect/pull/336>`_)\n+- Enhance UI extensions\n+ (`#341 <https://github.com/vivisect/vivisect/pull/341>`_)\n+- SREC file parsing support\n+ (`#343 <https://github.com/vivisect/vivisect/pull/343>`_)\n+\n+\n+Fixes\n+-----\n+- Import emulator to handle dynamic branches (switchcases) using only xrefs\n+ (`#314 <https://github.com/vivisect/vivisect/pull/314>`_)\n+- ARM Register access tweaks\n+ (`#315 <https://github.com/vivisect/vivisect/pull/315>`_)\n+- Normlize the return value/usage of i386's getOperAddr\n+ (`#316 <https://github.com/vivisect/vivisect/pull/316>`_)\n+- Bugfix for handling deleted codeblocks\n+ (`#317 <https://github.com/vivisect/vivisect/pull/317>`_)\n+- Syntax error fixes\n+ (`#318 <https://github.com/vivisect/vivisect/pull/318>`_)\n+- PE carving fix/makePointer call in makeOpcode fix\n+ (`#320 <https://github.com/vivisect/vivisect/pull/320>`_)\n+- More intel nop instruction decodings\n+ (`#326 <https://github.com/vivisect/vivisect/pull/326>`_)\n+- More intel decodings/Codeflow fixes/Enable ARM for PE/Address infinite loop/Metadata\n+ (`#329 <https://github.com/vivisect/vivisect/pull/329>`_)\n+- Cobra: not configuring logging for everyone upon import\n+ (`#330 <https://github.com/vivisect/vivisect/pull/330>`_)\n+- Speedup for symbolik's setSymKid and more intel decoding fixes\n+ (`#332 <https://github.com/vivisect/vivisect/pull/332>`_)\n+- Don't configure logging in vivisect module\n+ (`#334 <https://github.com/vivisect/vivisect/pull/334>`_)\n+- Slight ARM fixes for bx flags and IHEX fixes for meta info\n+ (`#337 <https://github.com/vivisect/vivisect/pull/337>`_)\n+- PE fixes for reading at high relative offsets\n+ (`#338 <https://github.com/vivisect/vivisect/pull/338>`_)\n+- Streamline ELF tests to reduce memory footprint\n+ (`#340 <https://github.com/vivisect/vivisect/pull/340>`_)\n+- Streamline Symboliks Tests to reduce memory footprint\n+ (`#342 <https://github.com/vivisect/vivisect/pull/342>`_)\n+- Remove unused cobra imports\n+ (`#344 <https://github.com/vivisect/vivisect/pull/344>`_)\n+- More robust location handling for corrupt PE files\n+ (`#347 <https://github.com/vivisect/vivisect/pull/347>`_)\n+\n+\nv0.1.0 - 2020-09-08\n===================\n+\nFeatures\n--------\n-- Symbolik Reduction Speedup.\n- (`#309 <https://github.com/vivisect/vivisect/pull/309>`)\n-- Codebase cleanup in preparation to move to python 3.\n- (`#293 <https://github.com/vivisect/vivisect/pull/293>`)\n-- Support for integrating with revsync.\n- (`#304 <https://github.com/vivisect/vivisect/pull/304>`)\n-- Expand unittest coverage.\n- (`#303 <https://github.com/vivisect/vivisect/pull/303>`)\n- ELF tweaks for ARM binaries.\n- (`#290 <https://github.com/vivisect/vivisect/pull/290>`)\n+ (`#290 <https://github.com/vivisect/vivisect/pull/290>`_)\n+- Codebase cleanup in preparation to move to python 3.\n+ (`#293 <https://github.com/vivisect/vivisect/pull/293>`_)\n- More opcode mappings for intel.\n- (`#299 <https://github.com/vivisect/vivisect/pull/299>`)\n+ (`#299 <https://github.com/vivisect/vivisect/pull/299>`_)\n- Upgrade cxxfilt.\n- (`#302 <https://github.com/vivisect/vivisect/pull/302>`)\n+ (`#302 <https://github.com/vivisect/vivisect/pull/302>`_)\n+- Expand unittest coverage.\n+ (`#303 <https://github.com/vivisect/vivisect/pull/303>`_)\n+- Support for integrating with revsync.\n+ (`#304 <https://github.com/vivisect/vivisect/pull/304>`_)\n+- Symbolik Reduction Speedup.\n+ (`#309 <https://github.com/vivisect/vivisect/pull/309>`_)\nFixes\n-----\n-- Make creation of $HOME/.viv directory user configurable.\n- (`#310 <https://github.com/vivisect/vivisect/pull/310>`)\n-- Msgpack strict_map_key bugfix.\n- (`#307 <https://github.com/vivisect/vivisect/pull/307>`)\n-- ARM disassembly and emulation bugfixes.\n- (`#305 <https://github.com/vivisect/vivisect/pull/305>`)\n- PyPI fix for vtrace.\n- (`#300 <https://github.com/vivisect/vivisect/pull/300>`)\n+ (`#300 <https://github.com/vivisect/vivisect/pull/300>`_)\n- Calling convention fixes\n- (`#301 <https://github.com/vivisect/vivisect/pull/301>`)\n+ (`#301 <https://github.com/vivisect/vivisect/pull/301>`_)\n+- ARM disassembly and emulation bugfixes.\n+ (`#305 <https://github.com/vivisect/vivisect/pull/305>`_)\n+- Msgpack strict_map_key bugfix.\n+ (`#307 <https://github.com/vivisect/vivisect/pull/307>`_)\n+- Make creation of $HOME/.viv directory user configurable.\n+ (`#310 <https://github.com/vivisect/vivisect/pull/310>`_)\nv0.1.0rc1 - 2020-07-30\n"
},
{
"change_type": "MODIFY",
"old_path": "setup.py",
"new_path": "setup.py",
"diff": "@@ -9,7 +9,7 @@ setup(\nname='vivisect',\nauthor='Vivisect',\nauthor_email='',\n- version='0.1.0',\n+ version='0.2.0',\nurl='https://github.com/vivisect/vivisect',\npackages=find_packages(),\nzip_safe=False,\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
v0.2.0 release notes (#335)
Changelog Updates
|
718,771 |
07.02.2021 04:55:10
| -7,200 |
43fca2f3150011ae1a130a39430c352e7cd841c2
|
fixed memory view render bugs.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/memcanvas/__init__.py",
"new_path": "envi/memcanvas/__init__.py",
"diff": "@@ -30,10 +30,11 @@ class MemoryRenderer(object):\ndef rendChars(self, mcanv, bytez):\nfor b in bytez:\n- val = ord(b)\n- bstr = \"%.2x\" % val\n- if val < 0x20 or val > 0x7e:\n+ bstr = \"%.2x\" % b\n+ if b < 0x20 or b > 0x7e:\nb = \".\"\n+ else:\n+ b = chr(b)\nmcanv.addNameText(b, bstr)\ndef render(self, mcanv, va):\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/memcanvas/renderers/__init__.py",
"new_path": "envi/memcanvas/renderers/__init__.py",
"diff": "@@ -3,6 +3,7 @@ Some of the basic/universal memory renderers.\n'''\nimport struct\n+import binascii\nimport envi.memory as e_mem\nimport envi.memcanvas as e_canvas\n@@ -18,20 +19,20 @@ class ByteRend(e_canvas.MemoryRenderer):\nif bigend:\nself.fmtbase = '>'\n- self.width = struct.calcsize('%s%s' % (self.fmtbase,self.__class__.__fmt_char__))\n+ self.width = struct.calcsize('%s%s' % (self.fmtbase, self.__fmt_char__))\nself.bformat = '%%.%dx' % (self.width * 2)\nself.pformat = '0x%s' % self.bformat\ndef render(self, mcanv, va, numbytes=16):\nbytez = mcanv.mem.readMemory(va, numbytes)\nif self.__pad__:\n- bytez = bytez.ljust(numbytes, '\\x00')\n+ bytez = bytez.ljust(numbytes, b'\\x00')\nmcanv.addVaText(self.pformat % va, va)\nmcanv.addText(' ')\n- cnt = len(bytez) / self.width\n- packfmt = self.fmtbase + (self.__class__.__fmt_char__ * cnt)\n+ cnt = len(bytez) // self.width\n+ packfmt = self.fmtbase + (self.__fmt_char__ * cnt)\nfor val in struct.unpack(packfmt, bytez):\nbstr = self.bformat % val\nif mcanv.mem.isValidPointer(val):\n@@ -65,22 +66,22 @@ class QuadRend(ByteRend):\n__fmt_char__ = 'Q'\n__pad__ = True\n-def isAscii(bytez):\n- bytez = bytez.split('\\x00')[0]\n+def isAscii(bytez: bytes):\n+ bytez = bytez.split(b'\\x00')[0]\nif len(bytez) < 4:\nreturn False, None\nfor i in range(len(bytez)):\n- o = ord(bytez[i])\n+ o = bytez[i]\nif o < 0x20 or o > 0x7e:\nreturn False, None\nreturn True, bytez\n-def isBasicUnicode(bytez):\n- bytez = bytez.split('\\x00\\x00')[0]\n+def isBasicUnicode(bytez: bytes):\n+ bytez = bytez.split(b'\\x00\\x00')[0]\nif len(bytez) < 8:\nreturn False, None\n- nonull = bytez.replace('\\x00', '')\n- if (len(bytez) / 2) - 1 != len(nonull):\n+ nonull = bytez.replace(b'\\x00', b'')\n+ if (len(bytez) // 2) - 1 != len(nonull):\nreturn False, None\nreturn isAscii(nonull)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/memory.py",
"new_path": "envi/memory.py",
"diff": "@@ -230,7 +230,7 @@ class IMemory:\nmap which contains the specified address (or None).\n'''\nfor mapva, size, perms, mname in self.getMemoryMaps():\n- if va >= mapva and va < (mapva+size):\n+ if mapva <= va < (mapva + size):\nreturn (mapva, size, perms, mname)\nreturn None\n@@ -277,7 +277,7 @@ class IMemory:\nmaptup = self.getMemoryMap(va)\nif maptup is None:\nreturn False\n- return bool(maptup[2] & MM_SHAR)\n+ return bool(maptup[2] & MM_SHARED)\ndef searchMemory(self, needle, regex=False):\n\"\"\"\n@@ -450,7 +450,7 @@ class MemoryObject(IMemory):\nGet the va,size,perms,fname tuple for this memory map\n\"\"\"\nfor mva, mmaxva, mmap, mbytes in self._map_defs:\n- if va >= mva and va < mmaxva:\n+ if mva <= va < mmaxva:\nreturn mmap\nreturn None\n@@ -460,7 +460,7 @@ class MemoryObject(IMemory):\ndef readMemory(self, va, size):\nfor mva, mmaxva, mmap, mbytes in self._map_defs:\n- if va >= mva and va < mmaxva:\n+ if mva <= va < mmaxva:\nmva, msize, mperms, mfname = mmap\nif not mperms & MM_READ:\nraise envi.SegmentationViolation(va)\n@@ -471,7 +471,7 @@ class MemoryObject(IMemory):\ndef writeMemory(self, va, bytes):\nfor mapdef in self._map_defs:\nmva, mmaxva, mmap, mbytes = mapdef\n- if va >= mva and va < mmaxva:\n+ if mva <= va < mmaxva:\nmva, msize, mperms, mfname = mmap\nif not (mperms & MM_WRITE or self._supervisor):\nraise envi.SegmentationViolation(va)\n@@ -491,7 +491,7 @@ class MemoryObject(IMemory):\n\"\"\"\nfor mapdef in self._map_defs:\nmva, mmaxva, mmap, mbytes = mapdef\n- if va >= mva and va < mmaxva:\n+ if mva <= va < mmaxva:\noffset = va - mva\nreturn (offset, mbytes)\nraise envi.SegmentationViolation(va)\n@@ -511,7 +511,7 @@ class MemoryObject(IMemory):\n'''\nfor mva, mmaxva, mmap, mbytes in self._map_defs:\n- if va >= mva and va < mmaxva:\n+ if mva <= va < mmaxva:\nmva, msize, mperms, mfname = mmap\nif not mperms & MM_READ:\nraise envi.SegmentationViolation(va)\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/qt.py",
"new_path": "vtrace/qt.py",
"diff": "@@ -526,6 +526,7 @@ class VQThreadsView(vq_tree.VQTreeView, VQTraceNotifier):\nself.selectthread = selectthread\ndef selectionChanged(self, selected, deselected):\n+ if len(self.selectedIndexes()) > 0:\nidx = self.selectedIndexes()[0]\nnode = idx.internalPointer()\nif node:\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
fixed memory view render bugs. (#352)
|
718,770 |
17.02.2021 15:54:25
| 18,000 |
9c41c7345a3a58de102c5b1b9fcd205883475778
|
bugs in imports in i386, amd64 and thumb.
* bugs in imports in i386, amd64 and thumb.
setup.py set to require Python 3+
* don't need python version stuff, it's in other PRs already.
|
[
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/disasm.py",
"new_path": "envi/archs/amd64/disasm.py",
"diff": "@@ -4,7 +4,7 @@ import envi\nimport envi.bits as e_bits\nimport envi.archs.i386 as e_i386\nimport envi.archs.i386.opconst as e_i386_const\n-import envi.archs.amd64.opcode64 as opcode86\n+from . import opcode64 as opcode86\nfrom envi.const import RMETA_NMASK\n@@ -13,7 +13,7 @@ from envi.archs.i386.disasm import iflag_lookup, operand_range, priv_lookup, \\\ni386SibOper, PREFIX_REPNZ, PREFIX_REP, PREFIX_OP_SIZE, PREFIX_ADDR_SIZE, \\\nMANDATORY_PREFIXES, PREFIX_REP_MASK, RMETA_LOW8, RMETA_LOW16\n-from envi.archs.amd64.regs import *\n+from .regs import *\nfrom envi.archs.i386.opconst import OP_EXTRA_MEMSIZES, OP_MEM_B, OP_MEM_W, OP_MEM_D, \\\nOP_MEM_Q, OP_MEM_DQ, OP_MEM_QQ, OP_MEMMASK, \\\nINS_VEXREQ, OP_NOVEXL\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "from envi.archs.i386.opconst import *\n-import envi.archs.amd64.regs as e_amd64_regs\n+from . import regs as e_amd64_regs\n# in order to be included, table name must be listed here.\ntablenames = [ None, # nexttable index 0 means NO TABLE!\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/disasm.py",
"new_path": "envi/archs/i386/disasm.py",
"diff": "@@ -10,10 +10,10 @@ import envi.bits as e_bits\n# Grab our register enums etc...\nfrom envi.const import *\n-from envi.archs.i386.regs import *\n+from .regs import *\n-import envi.archs.i386.opconst as opconst\n-import envi.archs.i386.opcode86 as opcode86\n+from . import opconst\n+from . import opcode86\nall_tables = opcode86.tables86\n# Our instruction prefix masks\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opcode86.py",
"new_path": "envi/archs/i386/opcode86.py",
"diff": "from envi.archs.i386.opconst import *\n-import envi.archs.i386.regs as e_i386_regs\n+from . import regs as e_i386_regs\n\"\"\"\n(optable, optype, operand 0, operand 1, operand 2, CPU required, \"opcodename\", op0Register, op1Register, op2Register)\n\"\"\"\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/thumb16/__init__.py",
"new_path": "envi/archs/thumb16/__init__.py",
"diff": "from envi.archs.arm import *\n-import envi.archs.thumb16.disasm as th_disasm\n+from . import disasm as th_disasm\nclass Thumb16Module(ThumbModule):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
bugs in imports in i386, amd64 and thumb. (#361)
* bugs in imports in i386, amd64 and thumb.
setup.py set to require Python 3+
* don't need python version stuff, it's in other PRs already.
|
718,770 |
18.02.2021 22:16:02
| 18,000 |
38a3fc23dbe79cd55335b57aa3587c05f3fb1d72
|
renderer fix: don't want to print hex for undefined bytes since the hex of the byte is already there.
debugging js addon.
|
[
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/memory.py",
"new_path": "vivisect/qt/memory.py",
"diff": "@@ -48,6 +48,7 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\nself.addHotKey('U', 'viv:undefine')\nself.addHotKey('ctrl+p', 'viv:preview:instr')\nself.addHotKey('B', 'viv:bookmark')\n+ self.addHotKey('ctrl+meta+J', 'viv:javascript')\nself.addHotKey('ctrl+1', 'viv:make:number:one')\nself.addHotKey('ctrl+2', 'viv:make:number:two')\n@@ -247,6 +248,12 @@ class VivCanvasBase(vq_hotkey.HotKeyMixin, e_mem_canvas.VQMemoryCanvas):\nvs = self.vw.makeStructure(curva, self._last_sname)\ncurva += len(vs)\n+ @vq_hotkey.hotkey('viv:javascript')\n+ def _hotkey_dbg_runjavascript(self, parent=None):\n+ js, ok = QInputDialog.getText(parent, 'Run Javascript', 'code:')\n+ if ok:\n+ self.page().runJavaScript(js)\n+\ndef makeStructAgainMulti(self, va, parent=None):\nif parent is None:\nparent = self\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/renderers/__init__.py",
"new_path": "vivisect/renderers/__init__.py",
"diff": "@@ -232,11 +232,12 @@ class WorkspaceRenderer(e_canvas.MemoryRenderer):\ntry:\nb = b.decode('utf-8')\n- except:\n- b = b.hex()\n-\nif b in string.printable:\nmcanv.addText(' %s' % repr(b), tag=cmnttag)\n+ except:\n+ # if we don't decode correctly, don't print it.\n+ pass\n+\nif cmnt is not None:\nmcanv.addText(' ;%s' % cmnt, tag=cmnttag)\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
renderer fix: don't want to print hex for undefined bytes since the hex of the byte is already there. (#364)
debugging js addon.
Co-authored-by: James Gross <45212823+rakuy0@users.noreply.github.com>
|
718,765 |
23.02.2021 17:17:22
| 18,000 |
6d31a212ad95c1364d42fb22401fc190eca76625
|
v1.0.0 release notes
Release notes and changelog for v1.0.0 (first python3 compatible release)
|
[
{
"change_type": "MODIFY",
"old_path": "CHANGELOG.rst",
"new_path": "CHANGELOG.rst",
"diff": "@@ -3,6 +3,39 @@ Vivisect Changelog\n******************\n+v1.0.0 - 2021-02-23\n+===================\n+\n+Features\n+--------\n+- Full Python 3 cutover\n+ (`#328 <https://github.com/vivisect/vivisect/pull/328>`_)\n+\n+Fixes\n+-----\n+- Make envi.codeflow stable when analyzing function\n+ (Wrapped in as part of #328)\n+- Fixing some issues with memory view rendering\n+ (`#352 https://github.com/vivisect/vivisect/pull/352`_)\n+- Python 3 Cleanup (for extensions/UI fixes/unicode detection/switchtable regression/ELF Parser)\n+ (`#353 https://github.com/vivisect/vivisect/pull/353`_)\n+- More memory render fixes\n+ (`#355 https://github.com/vivisect/vivisect/pull/355`_)\n+- More python3 fixes for API consistency and packed dll name exception handling\n+ (`#357 https://github.com/vivisect/vivisect/pull/357`_)\n+- Python3.6 specific import fixes\n+ (`#361 https://github.com/vivisect/vivisect/pull/361`_)\n+- Memory rendering tweaks to not double show bytes\n+ (`#364 https://github.com/vivisect/vivisect/pull/364`_)\n+- UI fixes for arrow keys, taint value fixes to prevent some infinity recursion\n+ (`#365 https://github.com/vivisect/vivisect/pull/365`_)\n+- Symbolik View was unusable\n+ (`#366 https://github.com/vivisect/vivisect/pull/366`_)\n+- DynamicBranches wasn't populating in py, and no return improvements\n+ (`#367 https://github.com/vivisect/vivisect/pull/367`_)\n+- Logging update for vivbin/vdbbin\n+ (`#368 https://github.com/vivisect/vivisect/pull/368`_)\n+\nv0.2.0 - 2021-02-01\n===================\n"
},
{
"change_type": "MODIFY",
"old_path": "README.md",
"new_path": "README.md",
"diff": "@@ -5,7 +5,7 @@ framework. More documentation is in the works :)\n## Vdb\n-As in previous vdb releases, the command ```python vdbbin``` from the\n+As in previous releases, the command ```python -m vdb.vdbbin``` from the\ncheckout directory will drop you into a debugger prompt on supported\nplatforms. ( Windows / Linux / FreeBSD / OSX... kinda? )\n@@ -27,7 +27,7 @@ To start with, you probably want to run a \"bulk analysis\" pass on a binary\nusing:\n```\n-python2 -m vivisect.vivbin -B <binaryfile>\n+python3 -m vivisect.vivbin -B <binaryfile>\n```\nwhich will leave you with <binaryfile>.viv\n@@ -35,95 +35,68 @@ which will leave you with <binaryfile>.viv\nThen run:\n```\n-python2 -m vivisect.vivbin <binaryfile>.viv\n+python3 -m vivisect.vivbin <binaryfile>.viv\n```\n-to open the GUI and begin reverse engineering. As with most vtoys, the ui\n-relies fairly heavily on right-click context menus and various memory\n-views.\n-\n-For the binary ninjas, all APIs used during automatic analysis ( and several\n-that aren't ) are directly accessible for use writing your own custom\n-research tools... The interface should be nearly the same when dealing with\n-a real process ( via vdb/vtrace ) and dealing with an emulator / viv workspace.\n-\n-## UI Dependencies\n-\n-The vivisect UI can be run under either PyQt4 and PyQt5\n-\n-For running via PyQt4, first you'll need to install Qt4 and Qt4-Webkit libraries. On Ubuntu, you can do this via:\n+to open the GUI and begin reverse engineering. Or, if you're impatient,\n+you can just run:\n```\n-sudo apt-get install libqt4-dev libqtwebkit-dev\n+python3 -m vivisect.vivbin <binaryfile>\n```\n-If you're on an older version of python, you may be able to pip install PyQt4 and SIP like so:\n+to do both simultaneously. You will have to hit <Ctrl-S> to manually save\n+the workspace file though.\n-```\n-pip install PyQt4 SIP\n-```\n+As with most vtoys, the ui relies fairly heavily on right-click context menus\n+and various memory views.\n-However, on recent (tested on 2.7.15 December 2018) versions of pip, that pip install fails. To get around this, you'll need to download the sources for both PyQt4 and SIP from Riverbank.\n-* SIP can be found [here](https://sourceforge.net/projects/pyqt/files/sip/sip-4.19.13/sip-4.19.13.tar.gz)\n-* PyQt4 can be found [here](http://sourceforge.net/projects/pyqt/files/PyQt4/PyQt-4.12.3/PyQt4_gpl_x11-4.12.3.tar.gz)\n+For the binary ninjas, all APIs used during automatic analysis (and several\n+that aren't) are directly accessible for use writing your own custom\n+research tools. The interface should be nearly the same when dealing with\n+a real process (via vdb/vtrace) and dealing with an emulator / viv workspace.\n-Untar them to their respective directories and cd in the directory for SIP:\n+## Installing\n-```\n-tar -xf sip-4.19.13.tar.gz\n-tar -xf PyQt4_gpl_x11-4.12.3.tar.gz\n-cd sip-4.19.13/\n-```\n+Unlike previous releases, version v1.x.x and up of vivisect/vdb should be entirely\n+pip installable, so just running `pip install vivisect` should get you the latest\n+release and all the dependencies.\n-Then build the SIP module. Due to the recent version of SIP we're using, we have to build it as a private module like so:\n+For convenience, setup.py for vivisect installs the main user facing scripts of\n+vivbin and vdbbin to the local path, so instead of having to run:\n```\n-python configure.py --sip-module PyQt4.sip\n-make\n-make install\n+python3 -m vivisect.vivbin <binaryfile>\n+python3 -m vdb.vdbbin\n```\n-Now cd back to the PyQt4 module and build that one:\n+You should just be able to run\n```\n-cd ../PyQt4_gpl_x11-4.12.3/\n-python configure-ng.py\n-make -j4\n-make install\n+vivbin -B <binaryfile>\n+vdbbin\n```\n-If you run into an `Error 2` status code on the `make install` line, replace that line with `sudo make install`, and things should work out fine.\n-\n-And then you should be able to open up your vivisect workspace with the vivbin script.\n+and have things work as normal.\n-### PyQt5\n+## Versioning\n-Installing PyQt5 via pip is not supported in Python 2.x. So similar steps must be followed to install PyQt5 to get the UI working that way as well.\n+All releases prior to v1.0.0 are python2 only. As of v1.0.0, vivisect/vdb/vstruct\n+are all python3 compatible. Please report any bugs/issues to the [issue tracker](https://github.com/vivisect/vivisect/issues)\n+or hit us up in the #vivisect room in the [synapse slack](http://slackinvite.vertex.link/)\n-Install qt5 and the webkit dependency:\n-```\n-sudo apt-get install qt5-default libqt5webkit5-dev\n-```\n-\n-Install the dependencies that PyQt5 needs:\n-```\n-pip install enum34\n-```\n+Please see v0.x.x-support branch for the current python2 version, or pip install\n+the v.0.2.x version of vivisect.\n-The rest of the build/install steps are the same, save for changing out the version numbers from PyQt4 to PyQt5.\n+## Upgrading\n-### Dependencies:\n-To enable proper networking:\n+Due to fun pickle shenanigans, old python2 vivisect workspaces are not typically\n+compatible with python3. In what will be one of (if not, the) final release of the\n+python2 compatible vivisect, v0.2.1 will include a conversion script that can migrate\n+the basicfile-based vivisect workspaces files to the msgpack-back ones, which should\n+be loadable in python3 vivisect.\n-```\n-pip install msgpack\n-```\n-\n-To enable Posix C++ demangling:\n-\n-```\n-pip install cxxfilt\n-```\n## Build Status\n+[](https://circleci.com/gh/vivisect/vivisect/tree/master)\n[](https://travis-ci.org/vivisect/vivisect)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/qt/memory.py",
"new_path": "envi/qt/memory.py",
"diff": "@@ -124,7 +124,8 @@ class VQMemoryWindow(vq_hotkey.HotKeyMixin, EnviNavMixin, vq_save.SaveableWidget\nself.mem_canvas = self.initMemoryCanvas(memobj, syms=syms)\nself.mem_canvas.setNavCallback(self.enviNavGoto)\n- QShortcut(QtGui.QKeySequence(\"Escape\"), self, activated=self._hotkey_histback)\n+ # https://doc.qt.io/qt-5/qt.html#ShortcutContext-enum\n+ QShortcut(QtGui.QKeySequence(\"Escape\"), self, activated=self._hotkey_histback, context=3)\nself.loadDefaultRenderers()\nself.loadRendSelect()\n"
},
{
"change_type": "MODIFY",
"old_path": "setup.py",
"new_path": "setup.py",
"diff": "@@ -9,7 +9,7 @@ setup(\nname='vivisect',\nauthor='Vivisect',\nauthor_email='',\n- version='0.2.0',\n+ version='1.0.0',\nurl='https://github.com/vivisect/vivisect',\npackages=find_packages(),\nzip_safe=False,\n@@ -32,12 +32,18 @@ setup(\n'cxxfilt==0.2.1',\n'msgpack==1.0.0',\n'pycparser==2.20',\n+ # TODO: There was a suggestion to break these out into a separate-ish install\n+ # like have these as optional dependencies so we can install viv headless. Worth?\n+ 'pyqt5==5.15.1',\n+ 'pyqtwebengine==5.15.1',\n],\nclassifiers=[\n'Topic :: Security',\n'Topic :: Software Development :: Disassemblers',\n'Topic :: Software Development :: Debuggers',\n- 'Programming Language :: Python :: 2',\n+ 'Programming Language :: Python :: 3.6',\n+ 'Programming Language :: Python :: 3.7',\n+ 'Programming Language :: Python :: 3.9',\n'License :: OSI Approved :: Apache Software License',\n],\npython_requires='>=3.6',\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -296,7 +296,7 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\nvwqgui.addEventCore(self)\nvwqgui.vivMemColorSignal.connect(self.mem_canvas._applyColorMap)\n- QtWidgets.QShortcut(QtGui.QKeySequence(\"Escape\"), self, activated=self._hotkey_histback)\n+ QtWidgets.QShortcut(QtGui.QKeySequence(\"Escape\"), self, activated=self._hotkey_histback, context=3)\n# TODO: Transition theses to the above pattern (since escape/ctrl-c\n# See: https://stackoverflow.com/questions/56890831/qwidget-cannot-catch-escape-backspace-or-c-x-key-press-events\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
v1.0.0 release notes (#369)
Release notes and changelog for v1.0.0 (first python3 compatible release)
|
718,770 |
29.03.2021 11:14:50
| 14,400 |
0fe14338a73e449de9218de3aa42b7b5b39dff65
|
Cleanup
* cleanup ELF parsing
* minor ARM (embedded) bugfix on infinite-loop detection
* cobra.cluster made usable after py3 upgrade.
converting from str to bytes for network comms, but leaving everything
as str's otherwise.
|
[
{
"change_type": "MODIFY",
"old_path": "cobra/cluster.py",
"new_path": "cobra/cluster.py",
"diff": "@@ -9,14 +9,14 @@ import time\nimport struct\nimport socket\nimport logging\n-import urllib2\nimport traceback\nimport threading\nimport subprocess\nimport multiprocessing\n+import urllib.request as url_req\nimport cobra\n-import dcode\n+from . import dcode\nlogger = logging.getLogger(__name__)\n@@ -316,7 +316,7 @@ class ClusterServer:\nelse:\nbuf = \"cobra:%s:%s:%d\" % (self.name, self.cobraname, self.cobrad.port)\n- self.sendsock.sendto(buf, (cluster_ip, cluster_port))\n+ self.sendsock.sendto(buf.encode('utf-8'), (cluster_ip, cluster_port))\ndef runServer(self, firethread=False):\n@@ -355,7 +355,7 @@ class ClusterServer:\n# If this work has no ID, give it one\nif work.id is None:\n- work.id = self.widiter.next()\n+ work.id = next(self.widiter)\nself.qcond.acquire()\nif self.maxsize is not None:\n@@ -502,7 +502,7 @@ class ClusterClient:\nself.sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)\nself.sock.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1)\nself.sock.bind((\"\",cluster_port))\n- mreq = struct.pack(\"4sL\", socket.inet_aton(cluster_ip), socket.INADDR_ANY)\n+ mreq = struct.pack(b\"4sL\", socket.inet_aton(cluster_ip), socket.INADDR_ANY)\nself.sock.setsockopt(socket.IPPROTO_IP, socket.IP_ADD_MEMBERSHIP, mreq)\ndef processWork(self):\n@@ -515,6 +515,9 @@ class ClusterClient:\nif self.width >= self.maxwidth:\ncontinue\n+ # make it a string again..\n+ buf = buf.decode('utf-8')\n+\nserver, svrport = sockaddr\nif not buf.startswith(\"cobra\"):\n@@ -531,6 +534,7 @@ class ClusterClient:\ncontinue\nif (self.name != name) and (self.name != \"*\"):\n+ logger.debug(\"skipping work, not me...(%r != %r)\", name, self.name)\ncontinue\nport = int(portstr)\n@@ -571,7 +575,7 @@ class ClusterQueen:\n# Get the host IP from the connection information\nhost, x = cobra.getCallerInfo()\nbuf = \"cobra:%s:%s:%d:%s\" % (name, cobraname, port, host)\n- self.sendsock.sendto(buf, (cluster_ip, cluster_port))\n+ self.sendsock.sendto(buf.encode('utf-8'), (cluster_ip, cluster_port))\ndef getHostPortFromUri(uri):\n\"\"\"\n@@ -579,9 +583,9 @@ def getHostPortFromUri(uri):\nhost and port for use in building the\ndcode uri.\n\"\"\"\n- x = urllib2.Request(uri)\n+ x = url_req.Request(uri)\nport = None\n- hparts = x.get_host().split(\":\")\n+ hparts = x.host.split(\":\")\nhost = hparts[0]\nif len(hparts):\nport = int(hparts[1])\n@@ -633,6 +637,7 @@ def runAndWaitWork(server, work):\ndef getAndDoWork(uri, docode=False):\n# If we wanna use dcode, set it up\n+ logger.debug(\"getAndDoWork: uri=\", uri)\ntry:\nif docode:\nhost,port = getHostPortFromUri(uri)\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/analysis/arm/emulation.py",
"new_path": "vivisect/analysis/arm/emulation.py",
"diff": "@@ -111,8 +111,8 @@ class AnalysisMonitor(viv_monitor.AnalysisMonitor):\nlogger.info(\"0x%x: +++++++++++++++ infinite loop +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\", op.va)\nif op.va not in self.infloops:\nself.infloops.append(op.va)\n- if 'InfiniteLoops' not in vw.getVaSetNames():\n- vw.addVaSet('InfiniteLoops', (('va', vivisect.VASET_ADDRESS, 'function', vivisect.VASET_STRING)))\n+ if 'InfiniteLoops' not in self.vw.getVaSetNames():\n+ self.vw.addVaSet('InfiniteLoops', (('va', vivisect.VASET_ADDRESS, 'function', vivisect.VASET_STRING)))\nself.vw.setVaSetRow('InfiniteLoops', (op.va, self.fva))\nexcept Exception as e:\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/parsers/elf.py",
"new_path": "vivisect/parsers/elf.py",
"diff": "@@ -597,7 +597,7 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nvw.makeImport(rlva, \"*\", dmglname)\nvw.setComment(rlva, name)\n- elif rtype in (Elf.R_386_32, Elf.R_386_COPY):\n+ elif rtype in (Elf.R_386_32, Elf.R_386_COPY, Elf.R_X86_64_TPOFF64):\npass\nelse:\n@@ -754,6 +754,9 @@ def applyRelocs(elf, vw, addbase=False, baseaddr=0):\nvw.makeName(rlva, dmglname, makeuniq=True)\nvw.setComment(rlva, name)\n+ elif rtype == Elf.R_ARM_COPY:\n+ pass\n+\nelse:\nlogger.warning('unknown reloc type: %d %s (at %s)', rtype, name, hex(rlva))\nlogger.info(r.tree())\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Cleanup (#385)
* cleanup ELF parsing
* minor ARM (embedded) bugfix on infinite-loop detection
* cobra.cluster made usable after py3 upgrade.
converting from str to bytes for network comms, but leaving everything
as str's otherwise.
|
718,765 |
05.04.2021 11:59:12
| 14,400 |
bed78fd01526db0e506af909688c4b136f70f257
|
v1.0.1 prep
|
[
{
"change_type": "MODIFY",
"old_path": "CHANGELOG.rst",
"new_path": "CHANGELOG.rst",
"diff": "Vivisect Changelog\n******************\n+v1.0.1 - 2021-04-05\n+===================\n+\n+Features\n+--------\n+- Dynamic dialog box/Extension docs\n+ (`#376 <https://github.com/vivisect/vivisect/pull/376>`_)\n+- ELF Checksec and metadata additions\n+ (`#379 <https://github.com/vivisect/vivisect/pull/379>`_)\n+- ARM Fixes/CLI Fixes/GUI Helpers\n+ (`#380 <https://github.com/vivisect/vivisect/pull/380>`_)\n+\n+Fixes\n+-----\n+- Callgraph/PE/vtrace fixes and pip installation update\n+ (`#372 <https://github.com/vivisect/vivisect/pull/373>`_)\n+- Extensions improvements\n+ (`#374 <https://github.com/vivisect/vivisect/pull/374>`_)\n+- Migration Doc and script/Cobra fixes/Data pointer improvement/Remote fixes\n+ (`#377 <https://github.com/vivisect/vivisect/pull/377>`_)\n+- Intel addrsize prefix fix/decoding fixes/emulator and symboliks updates/vdb fixes\n+ (`#384 <https://github.com/vivisect/vivisect/pull/384>`_)\n+- Cobra cluster updates/ARM analysis fixes/Elf parser fix\n+ (`#385 <https://github.com/vivisect/vivisect/pull/385>`_)\n+- v1.0.1 release/Intel decoding update/vtrace linux ps fix\n+ (`#386 <https://github.com/vivisect/vivisect/pull/386>`_)\n+\nv1.0.0 - 2021-02-23\n===================\n@@ -16,25 +43,25 @@ Fixes\n- Make envi.codeflow stable when analyzing function\n(Wrapped in as part of #328)\n- Fixing some issues with memory view rendering\n- (`#352 https://github.com/vivisect/vivisect/pull/352`_)\n+ (`#352 <https://github.com/vivisect/vivisect/pull/352>`_)\n- Python 3 Cleanup (for extensions/UI fixes/unicode detection/switchtable regression/ELF Parser)\n- (`#353 https://github.com/vivisect/vivisect/pull/353`_)\n+ (`#353 <https://github.com/vivisect/vivisect/pull/353>`_)\n- More memory render fixes\n- (`#355 https://github.com/vivisect/vivisect/pull/355`_)\n+ (`#355 <https://github.com/vivisect/vivisect/pull/355>`_)\n- More python3 fixes for API consistency and packed dll name exception handling\n- (`#357 https://github.com/vivisect/vivisect/pull/357`_)\n+ (`#357 <https://github.com/vivisect/vivisect/pull/357>`_)\n- Python3.6 specific import fixes\n- (`#361 https://github.com/vivisect/vivisect/pull/361`_)\n+ (`#361 <https://github.com/vivisect/vivisect/pull/361>`_)\n- Memory rendering tweaks to not double show bytes\n- (`#364 https://github.com/vivisect/vivisect/pull/364`_)\n+ (`#364 <https://github.com/vivisect/vivisect/pull/364>`_)\n- UI fixes for arrow keys, taint value fixes to prevent some infinity recursion\n- (`#365 https://github.com/vivisect/vivisect/pull/365`_)\n+ (`#365 <https://github.com/vivisect/vivisect/pull/365>`_)\n- Symbolik View was unusable\n- (`#366 https://github.com/vivisect/vivisect/pull/366`_)\n+ (`#366 <https://github.com/vivisect/vivisect/pull/366>`_)\n- DynamicBranches wasn't populating in py, and no return improvements\n- (`#367 https://github.com/vivisect/vivisect/pull/367`_)\n+ (`#367 <https://github.com/vivisect/vivisect/pull/367>`_)\n- Logging update for vivbin/vdbbin\n- (`#368 https://github.com/vivisect/vivisect/pull/368`_)\n+ (`#368 <https://github.com/vivisect/vivisect/pull/368>`_)\nv0.2.0 - 2021-02-01\n===================\n@@ -49,7 +76,7 @@ Features\n(`#327 <https://github.com/vivisect/vivisect/pull/327>`_)\n- Parse and return the delay import table\n(`#331 <https://github.com/vivisect/vivisect/pull/331>`_)\n-- New noret pass/several API refreshes/intel emulator fixes/emucode hyra function fixes\n+- New noret pass/several API refreshes/intel emulator fixes/emucode hydra function fixes\n(`#333 <https://github.com/vivisect/vivisect/pull/333>`_)\n- Migrate to CircleCI for Continuous Integratoin\n(`#336 <https://github.com/vivisect/vivisect/pull/336>`_)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/amd64/opcode64.py",
"new_path": "envi/archs/amd64/opcode64.py",
"diff": "@@ -1017,7 +1017,7 @@ tbl32_660F38[0x0c] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | O\ntbl32_660F38[0x0d] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"permilpd\", 0, 0, 0)\ntbl32_660F38[0x0e] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"testps\", 0, 0, 0)\ntbl32_660F38[0x0f] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, \"testpd\", 0, 0, 0)\n-tbl32_660F38[0x10] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ARG_NONE, cpu_AMD64, ARG_NONE, \"pblendvb\", 0, 0, 0)\n+tbl32_660F38[0x10] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AMD64, ARG_NONE, \"pblendvb\", 0, 0, 0)\ntbl32_660F38[0x13] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"cvtph2ps\", 0, 0, 0)\ntbl32_660F38[0x14] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_VEXSKIP | ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_VEXSKIP | ADDRMETH_V | OPTYPE_b | OP_R, cpu_AMD64, \"blendvps\", 0, 0, 0)\n@@ -1028,9 +1028,9 @@ tbl32_660F38[0x17] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W |\ntbl32_660F38[0x18] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ss | OP_R | OP_NOVEXL | OP_MEM_D, ARG_NONE, ARG_NONE, cpu_AMD64, \"broadcastss\", 0, 0, 0)\ntbl32_660F38[0x19] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_qq | OP_W, ADDRMETH_W | OPTYPE_ss | OP_R | OP_NOVEXL | OP_MEM_Q, ARG_NONE, ARG_NONE, cpu_AMD64, \"broadcastsd\", 0, 0, 0)\ntbl32_660F38[0x1a] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_qq | OP_W, ADDRMETH_M | OPTYPE_dq | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"broadcastf128\", 0, 0, 0)\n-tbl32_660F38[0x1c] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"pabsb\", 0, 0, 0)\n-tbl32_660F38[0x1d] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"pabsw\", 0, 0, 0)\n-tbl32_660F38[0x1e] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"pabsd\", 0, 0, 0)\n+tbl32_660F38[0x1c] = (0, INS_ABS, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"pabsb\", 0, 0, 0)\n+tbl32_660F38[0x1d] = (0, INS_ABS, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"pabsw\", 0, 0, 0)\n+tbl32_660F38[0x1e] = (0, INS_ABS, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, ARG_NONE, cpu_AMD64, \"pabsd\", 0, 0, 0)\n# TODO: There's a ymm version on this one that has a memory size of 128. Dammit. Though that only happens in vex256 land, it's still annoying\ntbl32_660F38[0x20] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_ps | OP_R | OP_MEM_Q | OP_NOVEXL, ARG_NONE, ARG_NONE, cpu_AMD64, \"pmovsxbw\", 0, 0, 0)\n@@ -1208,6 +1208,7 @@ tbl32_660F3A[0x46] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_qq | OP_W, ADDRMETH_H |\ntbl32_660F3A[0x4a] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ADDRMETH_L | OPTYPE_x | OP_R, cpu_AMD64, \"blendvps\", 0, 0, 0)\ntbl32_660F3A[0x4b] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ADDRMETH_L | OPTYPE_x | OP_R, cpu_AMD64, \"blendvpd\", 0, 0, 0)\n+tbl32_660F3A[0x4c] = (0, INS_VEXREQ | INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_H | OPTYPE_x | OP_R, ADDRMETH_W | OPTYPE_x | OP_R, ADDRMETH_L | OPTYPE_x | OP_R, cpu_AMD64, \"pblendvb\", 0, 0, 0)\ntbl32_660F3A[0x60] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_AMD64, \"pcmpestrm\", 0, 0, 0)\ntbl32_660F3A[0x61] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_W | OPTYPE_dq | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_AMD64, \"pcmpestri\", 0, 0, 0)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opcode86.py",
"new_path": "envi/archs/i386/opcode86.py",
"diff": "@@ -875,21 +875,21 @@ tbl32_0F18 = [\n(optable, optype, operand 0, operand 1, operand 2, CPU required, \"opcodename\", op0Register, op1Register, op2Register)\n\"\"\"\ntbl32_0F38 = [(0, 0, 0, 0, 0, 0, 0, 0, 0, 0) for x in range(256)]\n-tbl32_0F38[0x0] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pshufb\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x1] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phaddw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x2] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phaddd\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x3] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phaddsw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x4] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmaddubsw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x5] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phsubw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x6] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phsubd\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x7] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phsubsw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x8] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"psignb\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x9] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"psignw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0xa] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"psignd\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0xb] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmulhrsw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x1c] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsb\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x1d] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsw\", 0, 0, 0) # 66 prefix does different things...\n-tbl32_0F38[0x1e] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsd\", 0, 0, 0) # 66 prefix does different things...\n+tbl32_0F38[0x0] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pshufb\", 0, 0, 0)\n+tbl32_0F38[0x1] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phaddw\", 0, 0, 0)\n+tbl32_0F38[0x2] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phaddd\", 0, 0, 0)\n+tbl32_0F38[0x3] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phaddsw\", 0, 0, 0)\n+tbl32_0F38[0x4] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmaddubsw\", 0, 0, 0)\n+tbl32_0F38[0x5] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phsubw\", 0, 0, 0)\n+tbl32_0F38[0x6] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phsubd\", 0, 0, 0)\n+tbl32_0F38[0x7] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"phsubsw\", 0, 0, 0)\n+tbl32_0F38[0x8] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"psignb\", 0, 0, 0)\n+tbl32_0F38[0x9] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"psignw\", 0, 0, 0)\n+tbl32_0F38[0xa] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"psignd\", 0, 0, 0)\n+tbl32_0F38[0xb] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmulhrsw\", 0, 0, 0)\n+tbl32_0F38[0x1c] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsb\", 0, 0, 0)\n+tbl32_0F38[0x1d] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsw\", 0, 0, 0)\n+tbl32_0F38[0x1e] = (0, INS_OTHER, ADDRMETH_P | OPTYPE_q | OP_W, ADDRMETH_Q | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pabsd\", 0, 0, 0)\ntbl32_0F38[0xf0] = (0, INS_MOV, ADDRMETH_G | OPTYPE_z | OP_W, ADDRMETH_M | OPTYPE_z | OP_R, ARG_NONE, cpu_PENTIUM, \"movbe\", 0, 0, 0)\ntbl32_0F38[0xf1] = (0, INS_MOV, ADDRMETH_M | OPTYPE_z | OP_W, ADDRMETH_G | OPTYPE_z | OP_R, ARG_NONE, cpu_PENTIUM, \"movbe\", 0, 0, 0)\n@@ -917,19 +917,23 @@ tbl32_660F38[0xc] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0xd] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0xe] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0xf] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n-tbl32_660F38[0x10] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n+tbl32_660F38[0x10] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_W, ARG_NONE, cpu_PENTMMX, \"pblendvb\", 0, 0, 0)\ntbl32_660F38[0x11] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0x12] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0x13] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n-tbl32_660F38[0x14] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n-tbl32_660F38[0x15] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n+tbl32_660F38[0x14] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_PENTMMX, \"blendvps\", 0, 0, 0)\n+tbl32_660F38[0x15] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_PENTMMX, \"blendvpd\", 0, 0, 0)\ntbl32_660F38[0x16] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n-tbl32_660F38[0x17] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n+tbl32_660F38[0x17] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_PENTMMX, \"ptest\", 0, 0, 0)\ntbl32_660F38[0x18] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0x19] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0x1a] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\ntbl32_660F38[0x1b] = (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)\n+tbl32_660F38[0x1c] = (0, INS_ABS, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pabsb\", 0, 0, 0)\n+tbl32_660F38[0x1d] = (0, INS_ABS, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pabsw\", 0, 0, 0)\n+tbl32_660F38[0x1e] = (0, INS_ABS, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_x | OP_R, ARG_NONE, cpu_AVX, \"pabsd\", 0, 0, 0)\n+\ntbl32_660F38[0x20] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_q | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovsxbw\", 0, 0, 0)\ntbl32_660F38[0x21] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_d | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovsxbd\", 0, 0, 0)\ntbl32_660F38[0x22] = (0, INS_OTHER, ADDRMETH_V | OPTYPE_x | OP_W, ADDRMETH_W | OPTYPE_w | OP_R, ARG_NONE, cpu_PENTIUM2, \"pmovsxbq\", 0, 0, 0)\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/archs/i386/opconst.py",
"new_path": "envi/archs/i386/opconst.py",
"diff": "@@ -128,6 +128,7 @@ INS_SHL = INS_ARITH | 0x07\nINS_SHR = INS_ARITH | 0x08\nINS_ROL = INS_ARITH | 0x09\nINS_ROR = INS_ARITH | 0x0A\n+INS_ABS = INS_ARITH | 0x0B\nINS_AND = INS_LOGIC | 0x01\nINS_OR = INS_LOGIC | 0x02\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_amd64.py",
"new_path": "envi/tests/test_arch_amd64.py",
"diff": "@@ -524,6 +524,8 @@ amd64MultiByteOpcodes = [\n]\namd64VexOpcodes = [\n+ ('vpblendvb', 'C4E3694CCB40', 'vpblendvb xmm1,xmm2,xmm3,xmm4', 'vpblendvb xmm1,xmm2,xmm3,xmm4'),\n+ ('vpblendvb (256)', 'C4E36D4CCB40', 'vpblendvb ymm1,ymm2,ymm3,ymm4', 'vpblendvb ymm1,ymm2,ymm3,ymm4'),\n('SARX 1', 'c4e272f7c3', 'sarx eax,ebx,ecx', 'sarx eax,ebx,ecx'),\n('SARX 2', 'c4e2f2f7c3', 'sarx rax,rbx,rcx', 'sarx rax,rbx,rcx'),\n('SARX 3', 'c4e262f7042541414141', 'sarx eax,dword [0x41414141],ebx', 'sarx eax,dword [0x41414141],ebx'),\n"
},
{
"change_type": "MODIFY",
"old_path": "envi/tests/test_arch_i386.py",
"new_path": "envi/tests/test_arch_i386.py",
"diff": "@@ -276,6 +276,11 @@ i386MultiByteOpcodes = [\n('MFENCE', '0faef0', 0x40, 'mfence ', 'mfence '),\n('XSAVE', '0FAE2541414141', 0x40, 'xsave dword [0x41414141]', 'xsave dword [0x41414141]'),\n+ ('ptest', '660F3817242541414141', 0x40, 'ptest xmm4,oword [0x41414141]', 'ptest xmm4,oword [0x41414141]'),\n+ # TODO: Should we add the implicit xmm0 to these? It's only in non-vex mode\n+ ('blendvps', '660F3814CB', 0x40, 'blendvps xmm1,xmm3', 'blendvps xmm1,xmm3'),\n+ ('pblendvb', '660F3815CB', 0x40, 'blendvpd xmm1,xmm3', 'blendvpd xmm1,xmm3'),\n+\n# AES-NI feature set\n('AESENC', '660F38DCEA', 0x40, 'aesenc xmm5,xmm2', 'aesenc xmm5,xmm2'),\n('AESENC (MEM)', '660f38DC3A', 0x40, 'aesenc xmm7,oword [edx]', 'aesenc xmm7,oword [edx]'),\n"
},
{
"change_type": "MODIFY",
"old_path": "vtrace/platforms/linux.py",
"new_path": "vtrace/platforms/linux.py",
"diff": "@@ -419,10 +419,10 @@ class LinuxMixin(v_posix.PtraceMixin, v_posix.PosixMixin):\nif not dname.isdigit():\ncontinue\ncmdline = self.platformReadFile('/proc/%s/cmdline' % dname)\n- cmdline = cmdline.replace(\"\\x00\", \" \")\n+ cmdline = cmdline.replace(b\"\\x00\", b\" \")\nif len(cmdline) > 0:\n- pslist.append((int(dname), cmdline))\n- except:\n+ pslist.append((int(dname), cmdline.decode('utf-8')))\n+ except Exception as e:\npass # Permissions... quick process... whatev.\nreturn pslist\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
v1.0.1 prep (#386)
|
718,765 |
06.04.2021 17:17:37
| 14,400 |
b7b00f2d03defef28b4b8c912e3a8016e956c5f7
|
Version Engineering
Make verion bumping easier.
|
[
{
"change_type": "ADD",
"old_path": null,
"new_path": ".bumpversion.cfg",
"diff": "+[bumpversion]\n+current_version = 1.0.1\n+commit = True\n+tag = True\n+tag_message =\n+\n+[bumpversion:file:setup.py]\n+search = VERSION = '{current_version}'\n+replace = VERSION = '{new_version}'\n+\n+[bumpversion:file:vivisect/__init__.py]\n+serialize = {major}, {minor}, {patch}\n+parse = (?P<major>\\d+),\\s(?P<minor>\\d+),\\s(?P<patch>\\d+)\n+\n+[bumpversion:file:vdb/__init__.py]\n+serialize = {major}, {minor}, {patch}\n+parse = (?P<major>\\d+),\\s(?P<minor>\\d+),\\s(?P<patch>\\d+)\n"
},
{
"change_type": "MODIFY",
"old_path": "CHANGELOG.rst",
"new_path": "CHANGELOG.rst",
"diff": "@@ -78,7 +78,7 @@ Features\n(`#331 <https://github.com/vivisect/vivisect/pull/331>`_)\n- New noret pass/several API refreshes/intel emulator fixes/emucode hydra function fixes\n(`#333 <https://github.com/vivisect/vivisect/pull/333>`_)\n-- Migrate to CircleCI for Continuous Integratoin\n+- Migrate to CircleCI for Continuous Integration\n(`#336 <https://github.com/vivisect/vivisect/pull/336>`_)\n- Enhance UI extensions\n(`#341 <https://github.com/vivisect/vivisect/pull/341>`_)\n"
},
{
"change_type": "ADD",
"old_path": null,
"new_path": "requirements_dev.txt",
"diff": "+-r requirements.txt\n+bump2version>=1.0.0,<1.1.0\n"
},
{
"change_type": "MODIFY",
"old_path": "setup.py",
"new_path": "setup.py",
"diff": "from setuptools import find_packages, setup\nfrom os import path\n+VERSION = '1.0.1'\n+\ndirn = path.abspath(path.dirname(__file__))\nwith open(path.join(dirn, 'README.md'), 'r') as fd:\ndesc = fd.read()\nsetup(\nname='vivisect',\n- author='Vivisect',\n+ author='The Vivisect Peeps',\nauthor_email='',\n- version='1.0.1',\n+ version=VERSION,\nurl='https://github.com/vivisect/vivisect',\npackages=find_packages(),\nzip_safe=False,\n"
},
{
"change_type": "MODIFY",
"old_path": "vdb/__init__.py",
"new_path": "vdb/__init__.py",
"diff": "@@ -2287,3 +2287,10 @@ class Vdb(e_cli.EnviMutableCli, v_notif.Notifier, v_util.TraceManager):\nif not text:\nreturn libnames\nreturn [ i for i in libnames if i.startswith( text ) ]\n+\n+##############################################################################\n+# The following are touched during the release process by bump2version.\n+# You should have no reason to modify these yourself\n+version = (1, 0, 1)\n+verstring = '.'.join([str(x) for x in version])\n+commit = ''\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/__init__.py",
"new_path": "vivisect/__init__.py",
"diff": "@@ -44,7 +44,6 @@ from vivisect.defconfig import *\nimport vivisect.analysis.generic.emucode as v_emucode\n-\nlogger = logging.getLogger(__name__)\nSTOP_LOCS = (LOC_STRING, LOC_UNI, LOC_STRUCT, LOC_CLSID, LOC_VFTABLE, LOC_IMPORT, LOC_PAD, LOC_NUMBER)\n@@ -3083,3 +3082,9 @@ def getVivPath(*pathents):\nreturn os.path.join(dname, *pathents)\n+##############################################################################\n+# The following are touched during the release process by bump2version.\n+# You should have no reason to modify these directly\n+version = (1, 0, 1)\n+verstring = '.'.join([str(x) for x in version])\n+commit = ''\n"
},
{
"change_type": "MODIFY",
"old_path": "vivisect/qt/funcgraph.py",
"new_path": "vivisect/qt/funcgraph.py",
"diff": "@@ -449,7 +449,9 @@ class VQVivFuncgraphView(vq_hotkey.HotKeyMixin, e_qt_memory.EnviNavMixin, QWidge\nreturn\nself.mem_canvas.page().runJavaScript('''\nvar node = document.getElementsByName(\"viv:0x%.8x\")[0];\n+ if (node != null) {\nnode.scrollIntoView();\n+ }\n''' % addr, self._finishFuncRender)\ndef _layoutEdges(self, data):\n"
}
] |
Python
|
Apache License 2.0
|
vivisect/vivisect
|
Version Engineering (#388)
Make verion bumping easier.
|
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