map_spare_cells

ECO command. Map all new created cells to spare cells (LLM: metal only)
Usage: $status = map_spare_cells;
$status: 0: the mapping is successful
         non zero: the mapping fails 
@options:
    -help: Print this information.
    -syn Synthesis_command_line: 
            By default, the built-in Synthesis Engine is used.
            External Synthesis tool can be picked by this option
            RTL Compiler and Design Compiler are supported. 
            E.G. "map_spare_cells('-syn', 'rc')" to pick RTL compiler
                 "map_spare_cells('-syn', 'dc_shell')" to pick Design Compiler 
            User can specify more values in the synthesis command
            E.G. '-rc', "rc -E -use_lic RTL_Compiler_Physical"
    -lib_header file_name: This option is Valid when '-syn' option is present. To insert the content of 
                           file 'file_name' to the header of synthesis tcl script. So that '.lib' file to
                           '.db' conversion can be avoided in Design Compiler case. 
                           For example, in Design Compiler case, the file content should have
                             set_search_path [list /project/lib/synopsys_db]
                             set_target_library [list art40_hvt art40_svt]
                             set link_library [list art40_hvt art40_svt]
    -nofreed: Don't add freed gates for synthesis. 
    -nobuf: Don't insert buffers/repeaters in long wires. 
    -notielow: Don't tie low of the input pins of output floating gates, delete them instead
    -pause: Pause the tool before apply the patch
    -exact: Map to the exact name of spare cell, by default the tool picks up a spare cell with 
            the same function, for example, pick up 'INVX2' for 'INVX4'
    -gcmp: Use GOF compiler
    -nospare_mapping: Don't map to physical spare gates even DEF file is loaded
Note: A DEF file is needed for mapping to exact spare instances.

Examples:

#1. Map to spare cells and use the built-in Synthesis Engine
my $status = map_spare_cells;

#2. Use extra 'rc' option
map_spare_cells('-syn', "rc -E -use_lic RTL_Compiler_Physical")

#3. Don't add freed cells for synthesis
map_spare_cells('-syn', "rc -E -use_lic RTL_Compiler_Physical", "-nofreed")