src_en/man.geco_formalityhelp.txt

<h3>2.2.19 Formality help files generation</h3>
<p>GOF LEC logic equivalence checking can be performed on any two netlists or on the results after GOF ECO run. Subsequently, Formality help files can be generated for use in Formality, significantly enhancing the success rate of the Formality tool.</p>
<p>Formality help files generation:</p>
<div class='gofscript'><pre><a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.lib"</span>);
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.v"</span>); <span style='color:#b34c0a'># Reference netlist</span>
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"eco_netlist.v"</span>); <span style='color:#b34c0a'># ECOed netlist</span>
<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"CHIP_TOP"</span>);
<a class='n' href='#___run_lec'>run_lec</a>(); <span style='color:#b34c0a'># Run GOF LEC</span>
<a class='n' href='#___write_compare_points'>write_compare_points</a>(<span style='color:#63ac0a'>"compare_points.report"</span>);
<a class='n' href='#___write_formality_help_files'>write_formality_help_files</a>(<span style='color:#63ac0a'>"fm_dir/formality_help"</span>); <span style='color:#b34c0a'># formality_help files are generated in fm_dir folder</span>
</pre></div>
<p>In the above example, the assistance configuration file "fm_dir/formality_help.config.tcl" contains a compilation of set_user_match, rewire_connection, and set_constant commands designed to aid Formality in successfully achieving logic equivalence checking.</p>
<p>Integrated the file into Formality script:</p>
<div class='gofscript'><pre><span style='color:#b34c0a'># Formality netlist vs netlist script</span>
read_db -tech tsmc.db
read_verilog -r reference.v
read_verilog -i eco_netlist.v
<span style='color:#b34c0a'>#Setup constraint</span>
<span style='color:#b34c0a'>#Read in the help config file </span>
source fm_dir/formality_help.config.tcl
match
verify
</pre></div>
<h3>2.2.20 RTL Guided ECO Flow</h3>
<p>RTL-guided ECO employs two approaches: utilizing the built-in RTL logic equivalence checking engine of GOF or incorporating results from third-party LEC tools to pinpoint areas needing ECO adjustments. The advantage of the internal RTL LEC is its speed and efficiency. However, a drawback arises when hierarchies mismatch with synthesized netlists, particularly in designs with extensive SystemVerilog statements. To address this, third-party RTL LEC tool results can be utilized to resolve hierarchy inconsistencies. For example, GOF ECO can process a list file of non-equivalent results from tools like Synopsys Formality, allowing it to concentrate ECO efforts solely on identified areas.</p>
<h3>2.2.21 Internal RTL to RTL Guidance</h3>
<p>The RTL Guided ECO Flow is an additional step in the netlist ECO process, which involves comparing RTL designs to identify any discrepancies. Unlike Gate to Gate comparison, this method is faster and more targeted. The ECO process can be slowed down by the insertion of DFT logic and boundary optimization, making gate-to-gate comparison more complicated. Additionally, the use of RTL comparison can prevent the generation of redundant ECO fixes during patch generation.</p>
<p>Figure 15 illustrates how RTL to RTL comparison runs parallel to the key-point mapping of two gate-level netlists. If the non-equivalent points identified by RTL comparison have been integrated into the ECO flow successfully, gate-to-gate comparison can be bypassed.</p>
<div><img class='img-fluid' src='tp_image/rtl2rtl/RTL_ECO.png' /></div>
<p><b>Figure 15: RTL Guided ECO Flow</b></p>
<h4>2.2.21.1 Files and data requirements in RTL guided ECO</h4>
<ul>
  <li>Liberty files with extension '.lib'</li>
  <li>Other Verilog libraries files for modules not covered in '.lib' files</li>
  <li>Implementation SVF and Reference SVF file, required for designs with multibit flops</li>
  <li>Implementation Netlist on which ECO will be done</li>
  <li>Reference Netlist synthesized with the same constraints as the pre-layout netlist</li>
  <li>Implementation RTL which is logically equivalent to the Implementation Netlist</li>
  <li>Reference RTL which is logically equivalent to the Reference Netlist</li>
  <li>The top level module name under ECO</li>
</ul>
<h4>2.2.21.2 Steps to do RTL guided ECO</h4>
<ul>
  <li>Modify the original RTL</li>
  <li>Synthesize the new RTL to get Reference Netlist or synthesize sub-modules only and re-assemble the top level netlist</li>
  <li>Create GOF ECO script:
    <ul>
      <li>Specify ECO name in 'setup_eco'</li>
      <li>Load Liberty files and Verilog libraries</li>
      <li>Load Reference RTL (the modified RTL) and Implementation RTL (the original RTL)</li>
      <li>Check non-equivalent points by 'rtl_compare'</li>
      <li>Load the Reference Netlist and the Implementation Netlist</li>
      <li>Fix the design by 'fix_design'</li>
      <li>Report ECO status and write out ECO results</li>
    </ul>
  </li>
  <li>Run the above ECO script by "gof -run eco_script.pl"</li>
</ul>
<h4>2.2.21.3 RTL guided ECO example script</h4>
<p>GOF script has the exact same syntax as Perl script and runs the exported APIs that access the netlist database and modify the netlist.</p>
<p>The following is the example script for RTL guided ECO:</p>
<div class='gofscript'><pre><span style='color:#b34c0a'># GOF ECO script, rtl_guided.pl</span>
use strict;
<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"rtl_guided_eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span>
<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
my $rtl2rtl = 1;
if($rtl2rtl){
  <a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"SYNTHESIS"</span>);
  <a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"NO_SIM"</span>);
  <a class='n' href='#___set_inc_dirs'>set_inc_dirs</a>(<span style='color:#63ac0a'>"/project/nd900/vlib/include"</span>, <span style='color:#63ac0a'>"/project/nd900/IPS/include"</span>);
  <a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>"ref0.sv"</span>, <span style='color:#63ac0a'>"ref1.sv"</span>, <span style='color:#63ac0a'>"ref2.sv"</span>);
  <a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>"imp0.sv"</span>, <span style='color:#63ac0a'>"imp1.sv"</span>, <span style='color:#63ac0a'>"imp2.sv"</span>);
  <a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);
  <a class='n' href='#___rtl_compare'>rtl_compare</a>;
}
<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.svf.txt"</span>);       <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
<span style='color:#b34c0a'># Preserve DFT Test Logic</span>
<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
<a class='n' href='#___fix_design'>fix_design</a>;
<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span>
<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span>
<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span>
<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span>
exit; <span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears</span>
</pre></div>
<h4>2.2.21.4 Synthesize Reference RTL to Reference Netlist</h4>
<p>If Reference Netlist is not provided, it can be synthesized from Reference RTL by 'synthesize' command.</p>
<p>As shown in Figure 16, Reference RTL is directly synthesized into Reference Netlist and used in the ECO.</p>
<div><img class='img-fluid' src='tp_image/rtl2rtl/RTL_GUIDE_SYN.png' /></div>
<p><b>Figure 16: RTL Guided ECO Flow</b></p>
<p>The following is the example script for Reference RTL synthesis in RTL guided ECO:</p>
<div class='gofscript'><pre><span style='color:#b34c0a'># GOF ECO script, rtl_guided_synthesis.pl</span>
use strict;
<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"rtl_guided_eco_example"</span>);<span style='color:#b34c0a'># Setup ECO name</span>
<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"art.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"SYNTHESIS"</span>);
<a class='n' href='#___set_define'>set_define</a>(<span style='color:#63ac0a'>"NO_SIM"</span>);
<a class='n' href='#___set_inc_dirs'>set_inc_dirs</a>(<span style='color:#63ac0a'>"/project/nd900/vlib/include"</span>, <span style='color:#63ac0a'>"/project/nd900/IPS/include"</span>);
<a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-ref'</span>, <span style='color:#63ac0a'>"ref0.sv"</span>, <span style='color:#63ac0a'>"ref1.sv"</span>, <span style='color:#63ac0a'>"ref2.sv"</span>);
<a class='n' href='#___read_rtl'>read_rtl</a>(<span style='color:#63ac0a'>'-imp'</span>, <span style='color:#63ac0a'>"imp0.sv"</span>, <span style='color:#63ac0a'>"imp1.sv"</span>, <span style='color:#63ac0a'>"imp2.sv"</span>);
<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);
<a class='n' href='#___rtl_compare'>rtl_compare</a>;

<a class='n' href='#___read_svf'>read_svf</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.svf.txt"</span>);  <span style='color:#b34c0a'># Optional, must be loaded before read_design, must be in text format</span>
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"topmod"</span>);<span style='color:#b34c0a'># Set the top module</span>
<a class='n' href='#___elaborate'>elaborate</a>; <span style='color:#b34c0a'># The command synthesizes the Reference RTL to Reference Netlist </span>
<span style='color:#b34c0a'># Preserve DFT Test Logic</span>
<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"scan_out*"</span>);
<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_enable"</span>, 0);
<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_mode"</span>, 0);
<a class='n' href='#___fix_design'>fix_design</a>;
<a class='n' href='#___save_session'>save_session</a>(<span style='color:#63ac0a'>"current_eco_name"</span>); <span style='color:#b34c0a'># Save a session for future restoration</span>
<a class='n' href='#___report_eco'>report_eco</a>(); <span style='color:#b34c0a'># ECO report</span>
<a class='n' href='#___check_design'>check_design</a>(<span style='color:#63ac0a'>"-eco"</span>);<span style='color:#b34c0a'># Check if the ECO causes any issue, like floating</span>
<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);<span style='color:#b34c0a'># Write out ECO result in Verilog</span>
exit; <span style='color:#b34c0a'># Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears</span>
</pre></div>
<h3>2.2.22 Third Party RTL LEC Result Processing</h3>
<p>GOF ECO has the capability to ingest a list of ECO points, enabling it to concentrate exclusively on the items specified in the list. The format of the list file comprises a type designation followed by one or multiple spaces and then the non-equivalence point.</p>
<div class='gofscript'>
<pre>
inst yak_zcvg_inst/skip_pix_reg
port te_coord[5]
inst yak_hah_inst/x_start_pa_reg_31_
inst yak_hah_inst/x_end_pa_reg_30_
inst yak_hah_inst/x_end_pa_reg_29_
inst yak_hah_inst/x_end_pa_reg_28_
inst yak_hah_inst/x_end_pa_reg_27_
inst yak_hah_inst/x_end_pa_reg_26_
pin yak_hah_inst/u_sync_cell/D
</pre>
</div>
<p>The ECO list file is incorporated using the '-list_file' option within the 'read_design' command. It can be generated from a Third Party LEC non-equivalence result file. For instance, in Synopsys Formality, the command 'report_failing_points > formality_non_eq.report' generates such a file. In a GOF ECO script, this report file is then read in and converted into the list file.</p>
<p>Below is an example script demonstrating the conversion of Third Party LEC results and execution of GOF ECO with the 'list_file' option:</p>
<div class='gofscript'><pre>use strict;
my $list_cont = <span style='color:#63ac0a'>""</span>;
open(FIN, <span style='color:#63ac0a'>"formality_non_eq.report"</span>);
while(&lt;FIN&gt;){
  if(m/Ref\s+(\w+)\s+r:\/\w+\/\w+\/(.+)/){
    my $fm_type = $1;
    my $point = $2;
    my $gof_type = <span style='color:#63ac0a'>"inst"</span>;
    if($fm_type =~ m/Pin/){
      $gof_type = <span style='color:#63ac0a'>"pin"</span>;
    }elsif($fm_type =~ m/Port/){
      $gof_type = <span style='color:#63ac0a'>"port"</span>;
    }else{
      <span style='color:#b34c0a'># For instance type</span>
      $point =~ s/\[/_/g; <span style='color:#b34c0a'># Mostly abc_reg[0] has name changed to abc_reg_0_ in the netlist</span>
      $point =~ s/\]/_/g;
    }
    $list_cont .= <span style='color:#63ac0a'>"$gof_type $point\n"</span>;
  }
}
close(FIN);
open(FOUT, <span style='color:#63ac0a'>">eco_list.txt"</span>);
print FOUT $list_cont;
<a class='n' href='#___setup_eco'>setup_eco</a>(<span style='color:#63ac0a'>"eco_list_file"</span>); <span style='color:#b34c0a'># Setup ECO name</span>
<a class='n' href='#___set_log_file'>set_log_file</a>(<span style='color:#63ac0a'>"eco_list_file.log"</span>);
<a class='n' href='#___read_library'>read_library</a>(<span style='color:#63ac0a'>"tsmc.5nm.lib"</span>);<span style='color:#b34c0a'># Read in standard library</span>
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-ref"</span>, <span style='color:#63ac0a'>"reference.gv"</span>);<span style='color:#b34c0a'># Read in Reference Netlist</span>
<a class='n' href='#___read_design'>read_design</a>(<span style='color:#63ac0a'>"-imp"</span>, <span style='color:#63ac0a'>"implementation.gv"</span>);<span style='color:#b34c0a'># Read in Implementation Netlist Which is under ECO</span>
<a class='n' href='#___set_top'>set_top</a>(<span style='color:#63ac0a'>"SOC_TOP"</span>);
<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"test_mode"</span>, 0);
<a class='n' href='#___set_pin_constant'>set_pin_constant</a>(<span style='color:#63ac0a'>"scan_en"</span>, 0);
<a class='n' href='#___set_ignore_output'>set_ignore_output</a>(<span style='color:#63ac0a'>"test_so*"</span>);
<a class='n' href='#___fix_design'>fix_design</a>(<span style='color:#63ac0a'>"-list_file"</span>, <span style='color:#63ac0a'>"eco_list.txt"</span>); <span style='color:#b34c0a'># -list_file option to read in the ECO list file with the ECO points</span>
<a class='n' href='#___report_eco'>report_eco</a>();
<a class='n' href='#___write_verilog'>write_verilog</a>(<span style='color:#63ac0a'>"eco_verilog.v"</span>);
exit;
</pre></div>