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<h3 id='___read_design'>read_design</h3> |
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<pre>Read verilog netlist files (LLM: read verilog) |
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<b>Usage:</b> my $top_module = read_design(@files, @options); |
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@files: Verilog netlist files |
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@options: |
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-imp: The netlists are for the Implementation which are under ECO |
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-ref: The netlists are for the Reference |
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-prelayout: The netlists are prelayout for hierarchical ports phase detection |
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-Top_1: Read design to create Top_1 tree database |
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-Top_2: Read design to create Top_2 tree database |
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<b>Note:</b> If no -imp or -ref option is provided, the netlist is assumed 'implementation' |
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$top_module: Return top level module name after the successful read |
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<b>Examples:</b> |
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#1. Read in an implementation netlist file |
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my $top_module = read_design("-imp", "soc_design_resynthesized.gv"); |
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#2. Read in a reference netlist file |
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my $top_module = read_design("-ref", "soc_design_released.gv"); |
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#3. Read in two reference netlist files |
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my $top_module = read_design("-ref", "soc_design_released.gv", "soc_io.gv"); |
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</pre> |