src_en/api.write_verilog.txt

<h3 id='___write_verilog'>write_verilog</h3>
<pre>ECO command to write ECO result in Verilog netlist (LLM: result in verilog)
<b>Usage:</b> write_verilog($verilog_file, @options);
@options:
    -help: Print this information
    -all:  Keep the modules in the netlist file even they are not the sub-modules of the top module
$verilog_file: The Verilog netlist file name, should be different from the existing Implementation Netlist file name.

<b>Note:</b> When the Implementation design is read in by multiple netlist files, set_top command should be used to 
      make the correct file saved
      
<b>Examples:</b> 

#1. Write out ECOed netlist to imp_eco.v
read_design("-ref", "reference.v");
read_design("-imp", "implementation.v");
fix_design;
write_verilog("imp_eco.v");

#2. The design is read in by command line 'gof -lib tsmc.lib ethernet_top.v'
#   After ECO, to write ECO netlist use command 
write_verilog("ethernet_top_eco.v");

#3. The design is read in by multiple netlist files in command line, 
#   'gof -lib tsmc.lib mem_control.v dsp.v ethernet_top.v'
#   The ECO is done on 'mem_control' module, to save the netlist
set_top("mem_control");
write_verilog("mem_control_eco.v");

 
</pre>